1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-or-later 2*724ba675SRob Herring/* 3*724ba675SRob Herring * DTS file for all SPEAr1310 SoCs 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright 2012 Viresh Kumar <vireshk@kernel.org> 6*724ba675SRob Herring */ 7*724ba675SRob Herring 8*724ba675SRob Herring/include/ "spear13xx.dtsi" 9*724ba675SRob Herring 10*724ba675SRob Herring/ { 11*724ba675SRob Herring compatible = "st,spear1310"; 12*724ba675SRob Herring 13*724ba675SRob Herring ahb { 14*724ba675SRob Herring spics: spics@e0700000{ 15*724ba675SRob Herring compatible = "st,spear-spics-gpio"; 16*724ba675SRob Herring reg = <0xe0700000 0x1000>; 17*724ba675SRob Herring st-spics,peripcfg-reg = <0x3b0>; 18*724ba675SRob Herring st-spics,sw-enable-bit = <12>; 19*724ba675SRob Herring st-spics,cs-value-bit = <11>; 20*724ba675SRob Herring st-spics,cs-enable-mask = <3>; 21*724ba675SRob Herring st-spics,cs-enable-shift = <8>; 22*724ba675SRob Herring gpio-controller; 23*724ba675SRob Herring #gpio-cells = <2>; 24*724ba675SRob Herring }; 25*724ba675SRob Herring 26*724ba675SRob Herring miphy0: miphy@eb800000 { 27*724ba675SRob Herring compatible = "st,spear1310-miphy"; 28*724ba675SRob Herring reg = <0xeb800000 0x4000>; 29*724ba675SRob Herring misc = <&misc>; 30*724ba675SRob Herring phy-id = <0>; 31*724ba675SRob Herring #phy-cells = <1>; 32*724ba675SRob Herring status = "disabled"; 33*724ba675SRob Herring }; 34*724ba675SRob Herring 35*724ba675SRob Herring miphy1: miphy@eb804000 { 36*724ba675SRob Herring compatible = "st,spear1310-miphy"; 37*724ba675SRob Herring reg = <0xeb804000 0x4000>; 38*724ba675SRob Herring misc = <&misc>; 39*724ba675SRob Herring phy-id = <1>; 40*724ba675SRob Herring #phy-cells = <1>; 41*724ba675SRob Herring status = "disabled"; 42*724ba675SRob Herring }; 43*724ba675SRob Herring 44*724ba675SRob Herring miphy2: miphy@eb808000 { 45*724ba675SRob Herring compatible = "st,spear1310-miphy"; 46*724ba675SRob Herring reg = <0xeb808000 0x4000>; 47*724ba675SRob Herring misc = <&misc>; 48*724ba675SRob Herring phy-id = <2>; 49*724ba675SRob Herring #phy-cells = <1>; 50*724ba675SRob Herring status = "disabled"; 51*724ba675SRob Herring }; 52*724ba675SRob Herring 53*724ba675SRob Herring ahci0: ahci@b1000000 { 54*724ba675SRob Herring compatible = "snps,spear-ahci"; 55*724ba675SRob Herring reg = <0xb1000000 0x10000>; 56*724ba675SRob Herring interrupts = <0 68 0x4>; 57*724ba675SRob Herring phys = <&miphy0 0>; 58*724ba675SRob Herring phy-names = "sata-phy"; 59*724ba675SRob Herring status = "disabled"; 60*724ba675SRob Herring }; 61*724ba675SRob Herring 62*724ba675SRob Herring ahci1: ahci@b1800000 { 63*724ba675SRob Herring compatible = "snps,spear-ahci"; 64*724ba675SRob Herring reg = <0xb1800000 0x10000>; 65*724ba675SRob Herring interrupts = <0 69 0x4>; 66*724ba675SRob Herring phys = <&miphy1 0>; 67*724ba675SRob Herring phy-names = "sata-phy"; 68*724ba675SRob Herring status = "disabled"; 69*724ba675SRob Herring }; 70*724ba675SRob Herring 71*724ba675SRob Herring ahci2: ahci@b4000000 { 72*724ba675SRob Herring compatible = "snps,spear-ahci"; 73*724ba675SRob Herring reg = <0xb4000000 0x10000>; 74*724ba675SRob Herring interrupts = <0 70 0x4>; 75*724ba675SRob Herring phys = <&miphy2 0>; 76*724ba675SRob Herring phy-names = "sata-phy"; 77*724ba675SRob Herring status = "disabled"; 78*724ba675SRob Herring }; 79*724ba675SRob Herring 80*724ba675SRob Herring pcie0: pcie@b1000000 { 81*724ba675SRob Herring compatible = "st,spear1340-pcie", "snps,dw-pcie"; 82*724ba675SRob Herring reg = <0xb1000000 0x4000>, <0x80000000 0x20000>; 83*724ba675SRob Herring reg-names = "dbi", "config"; 84*724ba675SRob Herring interrupts = <0 68 0x4>; 85*724ba675SRob Herring num-lanes = <1>; 86*724ba675SRob Herring phys = <&miphy0 1>; 87*724ba675SRob Herring phy-names = "pcie-phy"; 88*724ba675SRob Herring #address-cells = <3>; 89*724ba675SRob Herring #size-cells = <2>; 90*724ba675SRob Herring device_type = "pci"; 91*724ba675SRob Herring ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ 92*724ba675SRob Herring 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ 93*724ba675SRob Herring bus-range = <0x00 0xff>; 94*724ba675SRob Herring status = "disabled"; 95*724ba675SRob Herring }; 96*724ba675SRob Herring 97*724ba675SRob Herring pcie1: pcie@b1800000 { 98*724ba675SRob Herring compatible = "st,spear1340-pcie", "snps,dw-pcie"; 99*724ba675SRob Herring reg = <0xb1800000 0x4000>, <0x90000000 0x20000>; 100*724ba675SRob Herring reg-names = "dbi", "config"; 101*724ba675SRob Herring interrupts = <0 69 0x4>; 102*724ba675SRob Herring num-lanes = <1>; 103*724ba675SRob Herring phys = <&miphy1 1>; 104*724ba675SRob Herring phy-names = "pcie-phy"; 105*724ba675SRob Herring #address-cells = <3>; 106*724ba675SRob Herring #size-cells = <2>; 107*724ba675SRob Herring device_type = "pci"; 108*724ba675SRob Herring ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */ 109*724ba675SRob Herring 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */ 110*724ba675SRob Herring bus-range = <0x00 0xff>; 111*724ba675SRob Herring status = "disabled"; 112*724ba675SRob Herring }; 113*724ba675SRob Herring 114*724ba675SRob Herring pcie2: pcie@b4000000 { 115*724ba675SRob Herring compatible = "st,spear1340-pcie", "snps,dw-pcie"; 116*724ba675SRob Herring reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>; 117*724ba675SRob Herring reg-names = "dbi", "config"; 118*724ba675SRob Herring interrupts = <0 70 0x4>; 119*724ba675SRob Herring num-lanes = <1>; 120*724ba675SRob Herring phys = <&miphy2 1>; 121*724ba675SRob Herring phy-names = "pcie-phy"; 122*724ba675SRob Herring #address-cells = <3>; 123*724ba675SRob Herring #size-cells = <2>; 124*724ba675SRob Herring device_type = "pci"; 125*724ba675SRob Herring ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */ 126*724ba675SRob Herring 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ 127*724ba675SRob Herring bus-range = <0x00 0xff>; 128*724ba675SRob Herring status = "disabled"; 129*724ba675SRob Herring }; 130*724ba675SRob Herring 131*724ba675SRob Herring gmac1: eth@5c400000 { 132*724ba675SRob Herring compatible = "st,spear600-gmac"; 133*724ba675SRob Herring reg = <0x5c400000 0x8000>; 134*724ba675SRob Herring interrupts = <0 95 0x4>; 135*724ba675SRob Herring interrupt-names = "macirq"; 136*724ba675SRob Herring phy-mode = "mii"; 137*724ba675SRob Herring status = "disabled"; 138*724ba675SRob Herring }; 139*724ba675SRob Herring 140*724ba675SRob Herring gmac2: eth@5c500000 { 141*724ba675SRob Herring compatible = "st,spear600-gmac"; 142*724ba675SRob Herring reg = <0x5c500000 0x8000>; 143*724ba675SRob Herring interrupts = <0 96 0x4>; 144*724ba675SRob Herring interrupt-names = "macirq"; 145*724ba675SRob Herring phy-mode = "mii"; 146*724ba675SRob Herring status = "disabled"; 147*724ba675SRob Herring }; 148*724ba675SRob Herring 149*724ba675SRob Herring gmac3: eth@5c600000 { 150*724ba675SRob Herring compatible = "st,spear600-gmac"; 151*724ba675SRob Herring reg = <0x5c600000 0x8000>; 152*724ba675SRob Herring interrupts = <0 97 0x4>; 153*724ba675SRob Herring interrupt-names = "macirq"; 154*724ba675SRob Herring phy-mode = "rmii"; 155*724ba675SRob Herring status = "disabled"; 156*724ba675SRob Herring }; 157*724ba675SRob Herring 158*724ba675SRob Herring gmac4: eth@5c700000 { 159*724ba675SRob Herring compatible = "st,spear600-gmac"; 160*724ba675SRob Herring reg = <0x5c700000 0x8000>; 161*724ba675SRob Herring interrupts = <0 98 0x4>; 162*724ba675SRob Herring interrupt-names = "macirq"; 163*724ba675SRob Herring phy-mode = "rgmii"; 164*724ba675SRob Herring status = "disabled"; 165*724ba675SRob Herring }; 166*724ba675SRob Herring 167*724ba675SRob Herring pinmux: pinmux@e0700000 { 168*724ba675SRob Herring compatible = "st,spear1310-pinmux"; 169*724ba675SRob Herring reg = <0xe0700000 0x1000>; 170*724ba675SRob Herring #gpio-range-cells = <3>; 171*724ba675SRob Herring }; 172*724ba675SRob Herring 173*724ba675SRob Herring apb { 174*724ba675SRob Herring i2c1: i2c@5cd00000 { 175*724ba675SRob Herring #address-cells = <1>; 176*724ba675SRob Herring #size-cells = <0>; 177*724ba675SRob Herring compatible = "snps,designware-i2c"; 178*724ba675SRob Herring reg = <0x5cd00000 0x1000>; 179*724ba675SRob Herring interrupts = <0 87 0x4>; 180*724ba675SRob Herring status = "disabled"; 181*724ba675SRob Herring }; 182*724ba675SRob Herring 183*724ba675SRob Herring i2c2: i2c@5ce00000 { 184*724ba675SRob Herring #address-cells = <1>; 185*724ba675SRob Herring #size-cells = <0>; 186*724ba675SRob Herring compatible = "snps,designware-i2c"; 187*724ba675SRob Herring reg = <0x5ce00000 0x1000>; 188*724ba675SRob Herring interrupts = <0 88 0x4>; 189*724ba675SRob Herring status = "disabled"; 190*724ba675SRob Herring }; 191*724ba675SRob Herring 192*724ba675SRob Herring i2c3: i2c@5cf00000 { 193*724ba675SRob Herring #address-cells = <1>; 194*724ba675SRob Herring #size-cells = <0>; 195*724ba675SRob Herring compatible = "snps,designware-i2c"; 196*724ba675SRob Herring reg = <0x5cf00000 0x1000>; 197*724ba675SRob Herring interrupts = <0 89 0x4>; 198*724ba675SRob Herring status = "disabled"; 199*724ba675SRob Herring }; 200*724ba675SRob Herring 201*724ba675SRob Herring i2c4: i2c@5d000000 { 202*724ba675SRob Herring #address-cells = <1>; 203*724ba675SRob Herring #size-cells = <0>; 204*724ba675SRob Herring compatible = "snps,designware-i2c"; 205*724ba675SRob Herring reg = <0x5d000000 0x1000>; 206*724ba675SRob Herring interrupts = <0 90 0x4>; 207*724ba675SRob Herring status = "disabled"; 208*724ba675SRob Herring }; 209*724ba675SRob Herring 210*724ba675SRob Herring i2c5: i2c@5d100000 { 211*724ba675SRob Herring #address-cells = <1>; 212*724ba675SRob Herring #size-cells = <0>; 213*724ba675SRob Herring compatible = "snps,designware-i2c"; 214*724ba675SRob Herring reg = <0x5d100000 0x1000>; 215*724ba675SRob Herring interrupts = <0 91 0x4>; 216*724ba675SRob Herring status = "disabled"; 217*724ba675SRob Herring }; 218*724ba675SRob Herring 219*724ba675SRob Herring i2c6: i2c@5d200000 { 220*724ba675SRob Herring #address-cells = <1>; 221*724ba675SRob Herring #size-cells = <0>; 222*724ba675SRob Herring compatible = "snps,designware-i2c"; 223*724ba675SRob Herring reg = <0x5d200000 0x1000>; 224*724ba675SRob Herring interrupts = <0 92 0x4>; 225*724ba675SRob Herring status = "disabled"; 226*724ba675SRob Herring }; 227*724ba675SRob Herring 228*724ba675SRob Herring i2c7: i2c@5d300000 { 229*724ba675SRob Herring #address-cells = <1>; 230*724ba675SRob Herring #size-cells = <0>; 231*724ba675SRob Herring compatible = "snps,designware-i2c"; 232*724ba675SRob Herring reg = <0x5d300000 0x1000>; 233*724ba675SRob Herring interrupts = <0 93 0x4>; 234*724ba675SRob Herring status = "disabled"; 235*724ba675SRob Herring }; 236*724ba675SRob Herring 237*724ba675SRob Herring spi1: spi@5d400000 { 238*724ba675SRob Herring compatible = "arm,pl022", "arm,primecell"; 239*724ba675SRob Herring reg = <0x5d400000 0x1000>; 240*724ba675SRob Herring interrupts = <0 99 0x4>; 241*724ba675SRob Herring #address-cells = <1>; 242*724ba675SRob Herring #size-cells = <0>; 243*724ba675SRob Herring status = "disabled"; 244*724ba675SRob Herring }; 245*724ba675SRob Herring 246*724ba675SRob Herring serial@5c800000 { 247*724ba675SRob Herring compatible = "arm,pl011", "arm,primecell"; 248*724ba675SRob Herring reg = <0x5c800000 0x1000>; 249*724ba675SRob Herring interrupts = <0 82 0x4>; 250*724ba675SRob Herring status = "disabled"; 251*724ba675SRob Herring }; 252*724ba675SRob Herring 253*724ba675SRob Herring serial@5c900000 { 254*724ba675SRob Herring compatible = "arm,pl011", "arm,primecell"; 255*724ba675SRob Herring reg = <0x5c900000 0x1000>; 256*724ba675SRob Herring interrupts = <0 83 0x4>; 257*724ba675SRob Herring status = "disabled"; 258*724ba675SRob Herring }; 259*724ba675SRob Herring 260*724ba675SRob Herring serial@5ca00000 { 261*724ba675SRob Herring compatible = "arm,pl011", "arm,primecell"; 262*724ba675SRob Herring reg = <0x5ca00000 0x1000>; 263*724ba675SRob Herring interrupts = <0 84 0x4>; 264*724ba675SRob Herring status = "disabled"; 265*724ba675SRob Herring }; 266*724ba675SRob Herring 267*724ba675SRob Herring serial@5cb00000 { 268*724ba675SRob Herring compatible = "arm,pl011", "arm,primecell"; 269*724ba675SRob Herring reg = <0x5cb00000 0x1000>; 270*724ba675SRob Herring interrupts = <0 85 0x4>; 271*724ba675SRob Herring status = "disabled"; 272*724ba675SRob Herring }; 273*724ba675SRob Herring 274*724ba675SRob Herring serial@5cc00000 { 275*724ba675SRob Herring compatible = "arm,pl011", "arm,primecell"; 276*724ba675SRob Herring reg = <0x5cc00000 0x1000>; 277*724ba675SRob Herring interrupts = <0 86 0x4>; 278*724ba675SRob Herring status = "disabled"; 279*724ba675SRob Herring }; 280*724ba675SRob Herring 281*724ba675SRob Herring thermal@e07008c4 { 282*724ba675SRob Herring st,thermal-flags = <0x7000>; 283*724ba675SRob Herring }; 284*724ba675SRob Herring 285*724ba675SRob Herring gpiopinctrl: gpio@d8400000 { 286*724ba675SRob Herring compatible = "st,spear-plgpio"; 287*724ba675SRob Herring reg = <0xd8400000 0x1000>; 288*724ba675SRob Herring interrupts = <0 100 0x4>; 289*724ba675SRob Herring #interrupt-cells = <1>; 290*724ba675SRob Herring interrupt-controller; 291*724ba675SRob Herring gpio-controller; 292*724ba675SRob Herring #gpio-cells = <2>; 293*724ba675SRob Herring gpio-ranges = <&pinmux 0 0 246>; 294*724ba675SRob Herring status = "disabled"; 295*724ba675SRob Herring 296*724ba675SRob Herring st-plgpio,ngpio = <246>; 297*724ba675SRob Herring st-plgpio,enb-reg = <0xd0>; 298*724ba675SRob Herring st-plgpio,wdata-reg = <0x90>; 299*724ba675SRob Herring st-plgpio,dir-reg = <0xb0>; 300*724ba675SRob Herring st-plgpio,ie-reg = <0x30>; 301*724ba675SRob Herring st-plgpio,rdata-reg = <0x70>; 302*724ba675SRob Herring st-plgpio,mis-reg = <0x10>; 303*724ba675SRob Herring st-plgpio,eit-reg = <0x50>; 304*724ba675SRob Herring }; 305*724ba675SRob Herring }; 306*724ba675SRob Herring }; 307*724ba675SRob Herring}; 308