1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 3*724ba675SRob Herring#include <dt-bindings/input/input.h> 4*724ba675SRob Herring#include <dt-bindings/gpio/gpio.h> 5*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 6*724ba675SRob Herring 7*724ba675SRob Herring/ { 8*724ba675SRob Herring compatible = "socionext,sc2000a"; 9*724ba675SRob Herring interrupt-parent = <&gic>; 10*724ba675SRob Herring #address-cells = <1>; 11*724ba675SRob Herring #size-cells = <1>; 12*724ba675SRob Herring 13*724ba675SRob Herring cpus { 14*724ba675SRob Herring #address-cells = <1>; 15*724ba675SRob Herring #size-cells = <0>; 16*724ba675SRob Herring enable-method = "socionext,milbeaut-m10v-smp"; 17*724ba675SRob Herring cpu@f00 { 18*724ba675SRob Herring device_type = "cpu"; 19*724ba675SRob Herring compatible = "arm,cortex-a7"; 20*724ba675SRob Herring reg = <0xf00>; 21*724ba675SRob Herring }; 22*724ba675SRob Herring cpu@f01 { 23*724ba675SRob Herring device_type = "cpu"; 24*724ba675SRob Herring compatible = "arm,cortex-a7"; 25*724ba675SRob Herring reg = <0xf01>; 26*724ba675SRob Herring }; 27*724ba675SRob Herring cpu@f02 { 28*724ba675SRob Herring device_type = "cpu"; 29*724ba675SRob Herring compatible = "arm,cortex-a7"; 30*724ba675SRob Herring reg = <0xf02>; 31*724ba675SRob Herring }; 32*724ba675SRob Herring cpu@f03 { 33*724ba675SRob Herring device_type = "cpu"; 34*724ba675SRob Herring compatible = "arm,cortex-a7"; 35*724ba675SRob Herring reg = <0xf03>; 36*724ba675SRob Herring }; 37*724ba675SRob Herring }; 38*724ba675SRob Herring 39*724ba675SRob Herring timer { /* The Generic Timer */ 40*724ba675SRob Herring compatible = "arm,armv7-timer"; 41*724ba675SRob Herring interrupts = <GIC_PPI 13 42*724ba675SRob Herring (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 43*724ba675SRob Herring <GIC_PPI 14 44*724ba675SRob Herring (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 45*724ba675SRob Herring <GIC_PPI 11 46*724ba675SRob Herring (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 47*724ba675SRob Herring <GIC_PPI 10 48*724ba675SRob Herring (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 49*724ba675SRob Herring clock-frequency = <40000000>; 50*724ba675SRob Herring always-on; 51*724ba675SRob Herring }; 52*724ba675SRob Herring 53*724ba675SRob Herring soc { 54*724ba675SRob Herring compatible = "simple-bus"; 55*724ba675SRob Herring #address-cells = <1>; 56*724ba675SRob Herring #size-cells = <1>; 57*724ba675SRob Herring ranges; 58*724ba675SRob Herring interrupt-parent = <&gic>; 59*724ba675SRob Herring 60*724ba675SRob Herring gic: interrupt-controller@1d000000 { 61*724ba675SRob Herring compatible = "arm,cortex-a7-gic"; 62*724ba675SRob Herring interrupt-controller; 63*724ba675SRob Herring #interrupt-cells = <3>; 64*724ba675SRob Herring reg = <0x1d001000 0x1000>, 65*724ba675SRob Herring <0x1d002000 0x1000>; /* CPU I/f base and size */ 66*724ba675SRob Herring }; 67*724ba675SRob Herring 68*724ba675SRob Herring clk: clock-ctrl@1d021000 { 69*724ba675SRob Herring compatible = "socionext,milbeaut-m10v-ccu"; 70*724ba675SRob Herring #clock-cells = <1>; 71*724ba675SRob Herring reg = <0x1d021000 0x1000>; 72*724ba675SRob Herring clocks = <&uclk40xi>; 73*724ba675SRob Herring }; 74*724ba675SRob Herring 75*724ba675SRob Herring timer@1e000050 { /* 32-bit Reload Timers */ 76*724ba675SRob Herring compatible = "socionext,milbeaut-timer"; 77*724ba675SRob Herring reg = <0x1e000050 0x20>; 78*724ba675SRob Herring interrupts = <0 91 4>; 79*724ba675SRob Herring clocks = <&clk 4>; 80*724ba675SRob Herring }; 81*724ba675SRob Herring 82*724ba675SRob Herring uart1: serial@1e700010 { /* PE4, PE5 */ 83*724ba675SRob Herring /* Enable this as ttyUSI0 */ 84*724ba675SRob Herring compatible = "socionext,milbeaut-usio-uart"; 85*724ba675SRob Herring reg = <0x1e700010 0x10>; 86*724ba675SRob Herring interrupts = <0 141 0x4>, <0 149 0x4>; 87*724ba675SRob Herring interrupt-names = "rx", "tx"; 88*724ba675SRob Herring clocks = <&clk 2>; 89*724ba675SRob Herring }; 90*724ba675SRob Herring 91*724ba675SRob Herring }; 92*724ba675SRob Herring 93*724ba675SRob Herring sram@0 { 94*724ba675SRob Herring compatible = "mmio-sram"; 95*724ba675SRob Herring reg = <0x0 0x10000>; 96*724ba675SRob Herring #address-cells = <1>; 97*724ba675SRob Herring #size-cells = <1>; 98*724ba675SRob Herring ranges = <0 0x0 0x10000>; 99*724ba675SRob Herring smp-sram@f100 { 100*724ba675SRob Herring compatible = "socionext,milbeaut-smp-sram"; 101*724ba675SRob Herring reg = <0xf100 0x20>; 102*724ba675SRob Herring }; 103*724ba675SRob Herring }; 104*724ba675SRob Herring}; 105