1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-or-later 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (c) 2020 thingy.jp. 4*724ba675SRob Herring * Author: Daniel Palmer <daniel@thingy.jp> 5*724ba675SRob Herring */ 6*724ba675SRob Herring 7*724ba675SRob Herring#include "mstar-infinity.dtsi" 8*724ba675SRob Herring 9*724ba675SRob Herring&cpu0_opp_table { 10*724ba675SRob Herring opp-1008000000 { 11*724ba675SRob Herring opp-hz = /bits/ 64 <1008000000>; 12*724ba675SRob Herring opp-microvolt = <1000000>; 13*724ba675SRob Herring clock-latency-ns = <300000>; 14*724ba675SRob Herring }; 15*724ba675SRob Herring 16*724ba675SRob Herring // overclock frequencies below, shown to work fine up to 1.3 GHz 17*724ba675SRob Herring opp-108000000 { 18*724ba675SRob Herring opp-hz = /bits/ 64 <1080000000>; 19*724ba675SRob Herring opp-microvolt = <1000000>; 20*724ba675SRob Herring clock-latency-ns = <300000>; 21*724ba675SRob Herring turbo-mode; 22*724ba675SRob Herring }; 23*724ba675SRob Herring 24*724ba675SRob Herring opp-1188000000 { 25*724ba675SRob Herring opp-hz = /bits/ 64 <1188000000>; 26*724ba675SRob Herring opp-microvolt = <1000000>; 27*724ba675SRob Herring clock-latency-ns = <300000>; 28*724ba675SRob Herring turbo-mode; 29*724ba675SRob Herring }; 30*724ba675SRob Herring 31*724ba675SRob Herring opp-1296000000 { 32*724ba675SRob Herring opp-hz = /bits/ 64 <1296000000>; 33*724ba675SRob Herring opp-microvolt = <1000000>; 34*724ba675SRob Herring clock-latency-ns = <300000>; 35*724ba675SRob Herring turbo-mode; 36*724ba675SRob Herring }; 37*724ba675SRob Herring 38*724ba675SRob Herring opp-1350000000 { 39*724ba675SRob Herring opp-hz = /bits/ 64 <1350000000>; 40*724ba675SRob Herring opp-microvolt = <1000000>; 41*724ba675SRob Herring clock-latency-ns = <300000>; 42*724ba675SRob Herring turbo-mode; 43*724ba675SRob Herring }; 44*724ba675SRob Herring 45*724ba675SRob Herring opp-1404000000 { 46*724ba675SRob Herring opp-hz = /bits/ 64 <1404000000>; 47*724ba675SRob Herring opp-microvolt = <1000000>; 48*724ba675SRob Herring clock-latency-ns = <300000>; 49*724ba675SRob Herring turbo-mode; 50*724ba675SRob Herring }; 51*724ba675SRob Herring 52*724ba675SRob Herring opp-1458000000 { 53*724ba675SRob Herring opp-hz = /bits/ 64 <1458000000>; 54*724ba675SRob Herring opp-microvolt = <1000000>; 55*724ba675SRob Herring clock-latency-ns = <300000>; 56*724ba675SRob Herring turbo-mode; 57*724ba675SRob Herring }; 58*724ba675SRob Herring 59*724ba675SRob Herring opp-1512000000 { 60*724ba675SRob Herring opp-hz = /bits/ 64 <1512000000>; 61*724ba675SRob Herring opp-microvolt = <1000000>; 62*724ba675SRob Herring clock-latency-ns = <300000>; 63*724ba675SRob Herring turbo-mode; 64*724ba675SRob Herring }; 65*724ba675SRob Herring}; 66*724ba675SRob Herring 67*724ba675SRob Herring&imi { 68*724ba675SRob Herring reg = <0xa0000000 0x20000>; 69*724ba675SRob Herring}; 70