1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Samsung S3C6410 based SMDK6410 board device tree source. 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> 6*724ba675SRob Herring * 7*724ba675SRob Herring * Device tree source file for Samsung SMDK6410 board which is based on 8*724ba675SRob Herring * Samsung's S3C6410 SoC. 9*724ba675SRob Herring */ 10*724ba675SRob Herring 11*724ba675SRob Herring/dts-v1/; 12*724ba675SRob Herring 13*724ba675SRob Herring#include <dt-bindings/gpio/gpio.h> 14*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 15*724ba675SRob Herring 16*724ba675SRob Herring#include "s3c6410.dtsi" 17*724ba675SRob Herring 18*724ba675SRob Herring/ { 19*724ba675SRob Herring model = "Samsung SMDK6410 board based on S3C6410"; 20*724ba675SRob Herring compatible = "samsung,smdk6410", "samsung,s3c6410"; 21*724ba675SRob Herring 22*724ba675SRob Herring memory@50000000 { 23*724ba675SRob Herring device_type = "memory"; 24*724ba675SRob Herring reg = <0x50000000 0x8000000>; 25*724ba675SRob Herring }; 26*724ba675SRob Herring 27*724ba675SRob Herring chosen { 28*724ba675SRob Herring bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; 29*724ba675SRob Herring }; 30*724ba675SRob Herring 31*724ba675SRob Herring fin_pll: oscillator-0 { 32*724ba675SRob Herring compatible = "fixed-clock"; 33*724ba675SRob Herring clock-frequency = <12000000>; 34*724ba675SRob Herring clock-output-names = "fin_pll"; 35*724ba675SRob Herring #clock-cells = <0>; 36*724ba675SRob Herring }; 37*724ba675SRob Herring 38*724ba675SRob Herring xusbxti: oscillator-1 { 39*724ba675SRob Herring compatible = "fixed-clock"; 40*724ba675SRob Herring clock-output-names = "xusbxti"; 41*724ba675SRob Herring clock-frequency = <48000000>; 42*724ba675SRob Herring #clock-cells = <0>; 43*724ba675SRob Herring }; 44*724ba675SRob Herring 45*724ba675SRob Herring srom-cs1-bus@18000000 { 46*724ba675SRob Herring compatible = "simple-bus"; 47*724ba675SRob Herring #address-cells = <1>; 48*724ba675SRob Herring #size-cells = <1>; 49*724ba675SRob Herring reg = <0x18000000 0x8000000>; 50*724ba675SRob Herring ranges; 51*724ba675SRob Herring 52*724ba675SRob Herring ethernet@18000000 { 53*724ba675SRob Herring compatible = "smsc,lan9115"; 54*724ba675SRob Herring reg = <0x18000000 0x10000>; 55*724ba675SRob Herring interrupt-parent = <&gpn>; 56*724ba675SRob Herring interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 57*724ba675SRob Herring phy-mode = "mii"; 58*724ba675SRob Herring reg-io-width = <4>; 59*724ba675SRob Herring smsc,force-internal-phy; 60*724ba675SRob Herring }; 61*724ba675SRob Herring }; 62*724ba675SRob Herring}; 63*724ba675SRob Herring 64*724ba675SRob Herring&clocks { 65*724ba675SRob Herring clocks = <&fin_pll>; 66*724ba675SRob Herring}; 67*724ba675SRob Herring 68*724ba675SRob Herring&sdhci0 { 69*724ba675SRob Herring pinctrl-names = "default"; 70*724ba675SRob Herring pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; 71*724ba675SRob Herring bus-width = <4>; 72*724ba675SRob Herring status = "okay"; 73*724ba675SRob Herring}; 74*724ba675SRob Herring 75*724ba675SRob Herring&uart0 { 76*724ba675SRob Herring pinctrl-names = "default"; 77*724ba675SRob Herring pinctrl-0 = <&uart0_data>, <&uart0_fctl>; 78*724ba675SRob Herring status = "okay"; 79*724ba675SRob Herring}; 80*724ba675SRob Herring 81*724ba675SRob Herring&uart1 { 82*724ba675SRob Herring pinctrl-names = "default"; 83*724ba675SRob Herring pinctrl-0 = <&uart1_data>; 84*724ba675SRob Herring status = "okay"; 85*724ba675SRob Herring}; 86*724ba675SRob Herring 87*724ba675SRob Herring&uart2 { 88*724ba675SRob Herring pinctrl-names = "default"; 89*724ba675SRob Herring pinctrl-0 = <&uart2_data>; 90*724ba675SRob Herring status = "okay"; 91*724ba675SRob Herring}; 92*724ba675SRob Herring 93*724ba675SRob Herring&uart3 { 94*724ba675SRob Herring pinctrl-names = "default"; 95*724ba675SRob Herring pinctrl-0 = <&uart3_data>; 96*724ba675SRob Herring status = "okay"; 97*724ba675SRob Herring}; 98