1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Samsung Exynos5410 SoC device tree source 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (c) 2013 Samsung Electronics Co., Ltd. 6*724ba675SRob Herring * http://www.samsung.com 7*724ba675SRob Herring * 8*724ba675SRob Herring * Samsung Exynos5410 SoC device nodes are listed in this file. 9*724ba675SRob Herring * Exynos5410 based board files can include this file and provide 10*724ba675SRob Herring * values for board specific bindings. 11*724ba675SRob Herring */ 12*724ba675SRob Herring 13*724ba675SRob Herring#include "exynos54xx.dtsi" 14*724ba675SRob Herring#include <dt-bindings/clock/exynos5410.h> 15*724ba675SRob Herring#include <dt-bindings/clock/exynos-audss-clk.h> 16*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 17*724ba675SRob Herring 18*724ba675SRob Herring/ { 19*724ba675SRob Herring compatible = "samsung,exynos5410", "samsung,exynos5"; 20*724ba675SRob Herring interrupt-parent = <&gic>; 21*724ba675SRob Herring 22*724ba675SRob Herring aliases { 23*724ba675SRob Herring pinctrl0 = &pinctrl_0; 24*724ba675SRob Herring pinctrl1 = &pinctrl_1; 25*724ba675SRob Herring pinctrl2 = &pinctrl_2; 26*724ba675SRob Herring pinctrl3 = &pinctrl_3; 27*724ba675SRob Herring }; 28*724ba675SRob Herring 29*724ba675SRob Herring cpus { 30*724ba675SRob Herring #address-cells = <1>; 31*724ba675SRob Herring #size-cells = <0>; 32*724ba675SRob Herring 33*724ba675SRob Herring cpu0: cpu@0 { 34*724ba675SRob Herring device_type = "cpu"; 35*724ba675SRob Herring compatible = "arm,cortex-a15"; 36*724ba675SRob Herring reg = <0x0>; 37*724ba675SRob Herring clock-frequency = <1600000000>; 38*724ba675SRob Herring }; 39*724ba675SRob Herring 40*724ba675SRob Herring cpu1: cpu@1 { 41*724ba675SRob Herring device_type = "cpu"; 42*724ba675SRob Herring compatible = "arm,cortex-a15"; 43*724ba675SRob Herring reg = <0x1>; 44*724ba675SRob Herring clock-frequency = <1600000000>; 45*724ba675SRob Herring }; 46*724ba675SRob Herring 47*724ba675SRob Herring cpu2: cpu@2 { 48*724ba675SRob Herring device_type = "cpu"; 49*724ba675SRob Herring compatible = "arm,cortex-a15"; 50*724ba675SRob Herring reg = <0x2>; 51*724ba675SRob Herring clock-frequency = <1600000000>; 52*724ba675SRob Herring }; 53*724ba675SRob Herring 54*724ba675SRob Herring cpu3: cpu@3 { 55*724ba675SRob Herring device_type = "cpu"; 56*724ba675SRob Herring compatible = "arm,cortex-a15"; 57*724ba675SRob Herring reg = <0x3>; 58*724ba675SRob Herring clock-frequency = <1600000000>; 59*724ba675SRob Herring }; 60*724ba675SRob Herring }; 61*724ba675SRob Herring 62*724ba675SRob Herring soc: soc { 63*724ba675SRob Herring compatible = "simple-bus"; 64*724ba675SRob Herring #address-cells = <1>; 65*724ba675SRob Herring #size-cells = <1>; 66*724ba675SRob Herring ranges; 67*724ba675SRob Herring 68*724ba675SRob Herring pmu_system_controller: system-controller@10040000 { 69*724ba675SRob Herring compatible = "samsung,exynos5410-pmu", "syscon"; 70*724ba675SRob Herring reg = <0x10040000 0x5000>; 71*724ba675SRob Herring clock-names = "clkout16"; 72*724ba675SRob Herring clocks = <&fin_pll>; 73*724ba675SRob Herring #clock-cells = <1>; 74*724ba675SRob Herring }; 75*724ba675SRob Herring 76*724ba675SRob Herring clock: clock-controller@10010000 { 77*724ba675SRob Herring compatible = "samsung,exynos5410-clock"; 78*724ba675SRob Herring reg = <0x10010000 0x30000>; 79*724ba675SRob Herring #clock-cells = <1>; 80*724ba675SRob Herring }; 81*724ba675SRob Herring 82*724ba675SRob Herring clock_audss: audss-clock-controller@3810000 { 83*724ba675SRob Herring compatible = "samsung,exynos5410-audss-clock"; 84*724ba675SRob Herring reg = <0x03810000 0x0c>; 85*724ba675SRob Herring #clock-cells = <1>; 86*724ba675SRob Herring clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>; 87*724ba675SRob Herring clock-names = "pll_ref", "pll_in"; 88*724ba675SRob Herring }; 89*724ba675SRob Herring 90*724ba675SRob Herring tmu_cpu0: tmu@10060000 { 91*724ba675SRob Herring compatible = "samsung,exynos5420-tmu"; 92*724ba675SRob Herring reg = <0x10060000 0x100>; 93*724ba675SRob Herring interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 94*724ba675SRob Herring clocks = <&clock CLK_TMU>; 95*724ba675SRob Herring clock-names = "tmu_apbif"; 96*724ba675SRob Herring #thermal-sensor-cells = <0>; 97*724ba675SRob Herring }; 98*724ba675SRob Herring 99*724ba675SRob Herring tmu_cpu1: tmu@10064000 { 100*724ba675SRob Herring compatible = "samsung,exynos5420-tmu"; 101*724ba675SRob Herring reg = <0x10064000 0x100>; 102*724ba675SRob Herring interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 103*724ba675SRob Herring clocks = <&clock CLK_TMU>; 104*724ba675SRob Herring clock-names = "tmu_apbif"; 105*724ba675SRob Herring #thermal-sensor-cells = <0>; 106*724ba675SRob Herring }; 107*724ba675SRob Herring 108*724ba675SRob Herring tmu_cpu2: tmu@10068000 { 109*724ba675SRob Herring compatible = "samsung,exynos5420-tmu"; 110*724ba675SRob Herring reg = <0x10068000 0x100>; 111*724ba675SRob Herring interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 112*724ba675SRob Herring clocks = <&clock CLK_TMU>; 113*724ba675SRob Herring clock-names = "tmu_apbif"; 114*724ba675SRob Herring #thermal-sensor-cells = <0>; 115*724ba675SRob Herring }; 116*724ba675SRob Herring 117*724ba675SRob Herring tmu_cpu3: tmu@1006c000 { 118*724ba675SRob Herring compatible = "samsung,exynos5420-tmu"; 119*724ba675SRob Herring reg = <0x1006c000 0x100>; 120*724ba675SRob Herring interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 121*724ba675SRob Herring clocks = <&clock CLK_TMU>; 122*724ba675SRob Herring clock-names = "tmu_apbif"; 123*724ba675SRob Herring #thermal-sensor-cells = <0>; 124*724ba675SRob Herring }; 125*724ba675SRob Herring 126*724ba675SRob Herring mmc_0: mmc@12200000 { 127*724ba675SRob Herring compatible = "samsung,exynos5250-dw-mshc"; 128*724ba675SRob Herring reg = <0x12200000 0x1000>; 129*724ba675SRob Herring interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 130*724ba675SRob Herring #address-cells = <1>; 131*724ba675SRob Herring #size-cells = <0>; 132*724ba675SRob Herring clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; 133*724ba675SRob Herring clock-names = "biu", "ciu"; 134*724ba675SRob Herring fifo-depth = <0x80>; 135*724ba675SRob Herring status = "disabled"; 136*724ba675SRob Herring }; 137*724ba675SRob Herring 138*724ba675SRob Herring mmc_1: mmc@12210000 { 139*724ba675SRob Herring compatible = "samsung,exynos5250-dw-mshc"; 140*724ba675SRob Herring reg = <0x12210000 0x1000>; 141*724ba675SRob Herring interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 142*724ba675SRob Herring #address-cells = <1>; 143*724ba675SRob Herring #size-cells = <0>; 144*724ba675SRob Herring clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; 145*724ba675SRob Herring clock-names = "biu", "ciu"; 146*724ba675SRob Herring fifo-depth = <0x80>; 147*724ba675SRob Herring status = "disabled"; 148*724ba675SRob Herring }; 149*724ba675SRob Herring 150*724ba675SRob Herring mmc_2: mmc@12220000 { 151*724ba675SRob Herring compatible = "samsung,exynos5250-dw-mshc"; 152*724ba675SRob Herring reg = <0x12220000 0x1000>; 153*724ba675SRob Herring interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 154*724ba675SRob Herring #address-cells = <1>; 155*724ba675SRob Herring #size-cells = <0>; 156*724ba675SRob Herring clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; 157*724ba675SRob Herring clock-names = "biu", "ciu"; 158*724ba675SRob Herring fifo-depth = <0x80>; 159*724ba675SRob Herring status = "disabled"; 160*724ba675SRob Herring }; 161*724ba675SRob Herring 162*724ba675SRob Herring pinctrl_0: pinctrl@13400000 { 163*724ba675SRob Herring compatible = "samsung,exynos5410-pinctrl"; 164*724ba675SRob Herring reg = <0x13400000 0x1000>; 165*724ba675SRob Herring interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 166*724ba675SRob Herring 167*724ba675SRob Herring wakeup-interrupt-controller { 168*724ba675SRob Herring compatible = "samsung,exynos4210-wakeup-eint"; 169*724ba675SRob Herring interrupt-parent = <&gic>; 170*724ba675SRob Herring interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 171*724ba675SRob Herring }; 172*724ba675SRob Herring }; 173*724ba675SRob Herring 174*724ba675SRob Herring pinctrl_1: pinctrl@14000000 { 175*724ba675SRob Herring compatible = "samsung,exynos5410-pinctrl"; 176*724ba675SRob Herring reg = <0x14000000 0x1000>; 177*724ba675SRob Herring interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 178*724ba675SRob Herring }; 179*724ba675SRob Herring 180*724ba675SRob Herring pinctrl_2: pinctrl@10d10000 { 181*724ba675SRob Herring compatible = "samsung,exynos5410-pinctrl"; 182*724ba675SRob Herring reg = <0x10d10000 0x1000>; 183*724ba675SRob Herring interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 184*724ba675SRob Herring }; 185*724ba675SRob Herring 186*724ba675SRob Herring pinctrl_3: pinctrl@3860000 { 187*724ba675SRob Herring compatible = "samsung,exynos5410-pinctrl"; 188*724ba675SRob Herring reg = <0x03860000 0x1000>; 189*724ba675SRob Herring interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 190*724ba675SRob Herring }; 191*724ba675SRob Herring 192*724ba675SRob Herring pdma0: dma-controller@121a0000 { 193*724ba675SRob Herring compatible = "arm,pl330", "arm,primecell"; 194*724ba675SRob Herring reg = <0x121a0000 0x1000>; 195*724ba675SRob Herring interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 196*724ba675SRob Herring clocks = <&clock CLK_PDMA0>; 197*724ba675SRob Herring clock-names = "apb_pclk"; 198*724ba675SRob Herring #dma-cells = <1>; 199*724ba675SRob Herring }; 200*724ba675SRob Herring 201*724ba675SRob Herring pdma1: dma-controller@121b0000 { 202*724ba675SRob Herring compatible = "arm,pl330", "arm,primecell"; 203*724ba675SRob Herring reg = <0x121b0000 0x1000>; 204*724ba675SRob Herring interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 205*724ba675SRob Herring clocks = <&clock CLK_PDMA1>; 206*724ba675SRob Herring clock-names = "apb_pclk"; 207*724ba675SRob Herring #dma-cells = <1>; 208*724ba675SRob Herring }; 209*724ba675SRob Herring 210*724ba675SRob Herring audi2s0: i2s@3830000 { 211*724ba675SRob Herring compatible = "samsung,exynos5420-i2s"; 212*724ba675SRob Herring reg = <0x03830000 0x100>; 213*724ba675SRob Herring dmas = <&pdma0 10>, 214*724ba675SRob Herring <&pdma0 9>, 215*724ba675SRob Herring <&pdma0 8>; 216*724ba675SRob Herring dma-names = "tx", "rx", "tx-sec"; 217*724ba675SRob Herring clocks = <&clock_audss EXYNOS_I2S_BUS>, 218*724ba675SRob Herring <&clock_audss EXYNOS_I2S_BUS>, 219*724ba675SRob Herring <&clock_audss EXYNOS_SCLK_I2S>; 220*724ba675SRob Herring clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 221*724ba675SRob Herring #clock-cells = <1>; 222*724ba675SRob Herring clock-output-names = "i2s_cdclk0"; 223*724ba675SRob Herring #sound-dai-cells = <1>; 224*724ba675SRob Herring samsung,idma-addr = <0x03000000>; 225*724ba675SRob Herring pinctrl-names = "default"; 226*724ba675SRob Herring pinctrl-0 = <&audi2s0_bus>; 227*724ba675SRob Herring status = "disabled"; 228*724ba675SRob Herring }; 229*724ba675SRob Herring }; 230*724ba675SRob Herring 231*724ba675SRob Herring thermal-zones { 232*724ba675SRob Herring cpu0_thermal: cpu0-thermal { 233*724ba675SRob Herring thermal-sensors = <&tmu_cpu0>; 234*724ba675SRob Herring #include "exynos5420-trip-points.dtsi" 235*724ba675SRob Herring }; 236*724ba675SRob Herring cpu1_thermal: cpu1-thermal { 237*724ba675SRob Herring thermal-sensors = <&tmu_cpu1>; 238*724ba675SRob Herring #include "exynos5420-trip-points.dtsi" 239*724ba675SRob Herring }; 240*724ba675SRob Herring cpu2_thermal: cpu2-thermal { 241*724ba675SRob Herring thermal-sensors = <&tmu_cpu2>; 242*724ba675SRob Herring #include "exynos5420-trip-points.dtsi" 243*724ba675SRob Herring }; 244*724ba675SRob Herring cpu3_thermal: cpu3-thermal { 245*724ba675SRob Herring thermal-sensors = <&tmu_cpu3>; 246*724ba675SRob Herring #include "exynos5420-trip-points.dtsi" 247*724ba675SRob Herring }; 248*724ba675SRob Herring }; 249*724ba675SRob Herring}; 250*724ba675SRob Herring 251*724ba675SRob Herring&adc { 252*724ba675SRob Herring clocks = <&clock CLK_TSADC>; 253*724ba675SRob Herring clock-names = "adc"; 254*724ba675SRob Herring samsung,syscon-phandle = <&pmu_system_controller>; 255*724ba675SRob Herring}; 256*724ba675SRob Herring 257*724ba675SRob Herring&arm_a15_pmu { 258*724ba675SRob Herring interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 259*724ba675SRob Herring status = "okay"; 260*724ba675SRob Herring}; 261*724ba675SRob Herring 262*724ba675SRob Herring&i2c_0 { 263*724ba675SRob Herring clocks = <&clock CLK_I2C0>; 264*724ba675SRob Herring clock-names = "i2c"; 265*724ba675SRob Herring pinctrl-names = "default"; 266*724ba675SRob Herring pinctrl-0 = <&i2c0_bus>; 267*724ba675SRob Herring}; 268*724ba675SRob Herring 269*724ba675SRob Herring&i2c_1 { 270*724ba675SRob Herring clocks = <&clock CLK_I2C1>; 271*724ba675SRob Herring clock-names = "i2c"; 272*724ba675SRob Herring pinctrl-names = "default"; 273*724ba675SRob Herring pinctrl-0 = <&i2c1_bus>; 274*724ba675SRob Herring}; 275*724ba675SRob Herring 276*724ba675SRob Herring&i2c_2 { 277*724ba675SRob Herring clocks = <&clock CLK_I2C2>; 278*724ba675SRob Herring clock-names = "i2c"; 279*724ba675SRob Herring pinctrl-names = "default"; 280*724ba675SRob Herring pinctrl-0 = <&i2c2_bus>; 281*724ba675SRob Herring}; 282*724ba675SRob Herring 283*724ba675SRob Herring&i2c_3 { 284*724ba675SRob Herring clocks = <&clock CLK_I2C3>; 285*724ba675SRob Herring clock-names = "i2c"; 286*724ba675SRob Herring pinctrl-names = "default"; 287*724ba675SRob Herring pinctrl-0 = <&i2c3_bus>; 288*724ba675SRob Herring}; 289*724ba675SRob Herring 290*724ba675SRob Herring&hsi2c_4 { 291*724ba675SRob Herring clocks = <&clock CLK_USI0>; 292*724ba675SRob Herring clock-names = "hsi2c"; 293*724ba675SRob Herring pinctrl-names = "default"; 294*724ba675SRob Herring pinctrl-0 = <&i2c4_hs_bus>; 295*724ba675SRob Herring}; 296*724ba675SRob Herring 297*724ba675SRob Herring&hsi2c_5 { 298*724ba675SRob Herring clocks = <&clock CLK_USI1>; 299*724ba675SRob Herring clock-names = "hsi2c"; 300*724ba675SRob Herring pinctrl-names = "default"; 301*724ba675SRob Herring pinctrl-0 = <&i2c5_hs_bus>; 302*724ba675SRob Herring}; 303*724ba675SRob Herring 304*724ba675SRob Herring&hsi2c_6 { 305*724ba675SRob Herring clocks = <&clock CLK_USI2>; 306*724ba675SRob Herring clock-names = "hsi2c"; 307*724ba675SRob Herring pinctrl-names = "default"; 308*724ba675SRob Herring pinctrl-0 = <&i2c6_hs_bus>; 309*724ba675SRob Herring}; 310*724ba675SRob Herring 311*724ba675SRob Herring&hsi2c_7 { 312*724ba675SRob Herring clocks = <&clock CLK_USI3>; 313*724ba675SRob Herring clock-names = "hsi2c"; 314*724ba675SRob Herring pinctrl-names = "default"; 315*724ba675SRob Herring pinctrl-0 = <&i2c7_hs_bus>; 316*724ba675SRob Herring}; 317*724ba675SRob Herring 318*724ba675SRob Herring&mct { 319*724ba675SRob Herring clocks = <&fin_pll>, <&clock CLK_MCT>; 320*724ba675SRob Herring clock-names = "fin_pll", "mct"; 321*724ba675SRob Herring}; 322*724ba675SRob Herring 323*724ba675SRob Herring&prng { 324*724ba675SRob Herring clocks = <&clock CLK_SSS>; 325*724ba675SRob Herring clock-names = "secss"; 326*724ba675SRob Herring}; 327*724ba675SRob Herring 328*724ba675SRob Herring&pwm { 329*724ba675SRob Herring clocks = <&clock CLK_PWM>; 330*724ba675SRob Herring clock-names = "timers"; 331*724ba675SRob Herring}; 332*724ba675SRob Herring 333*724ba675SRob Herring&rtc { 334*724ba675SRob Herring clocks = <&clock CLK_RTC>; 335*724ba675SRob Herring clock-names = "rtc"; 336*724ba675SRob Herring status = "disabled"; 337*724ba675SRob Herring}; 338*724ba675SRob Herring 339*724ba675SRob Herring&serial_0 { 340*724ba675SRob Herring clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 341*724ba675SRob Herring clock-names = "uart", "clk_uart_baud0"; 342*724ba675SRob Herring dmas = <&pdma0 13>, <&pdma0 14>; 343*724ba675SRob Herring dma-names = "rx", "tx"; 344*724ba675SRob Herring}; 345*724ba675SRob Herring 346*724ba675SRob Herring&serial_1 { 347*724ba675SRob Herring clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 348*724ba675SRob Herring clock-names = "uart", "clk_uart_baud0"; 349*724ba675SRob Herring dmas = <&pdma1 15>, <&pdma1 16>; 350*724ba675SRob Herring dma-names = "rx", "tx"; 351*724ba675SRob Herring}; 352*724ba675SRob Herring 353*724ba675SRob Herring&serial_2 { 354*724ba675SRob Herring clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 355*724ba675SRob Herring clock-names = "uart", "clk_uart_baud0"; 356*724ba675SRob Herring dmas = <&pdma0 15>, <&pdma0 16>; 357*724ba675SRob Herring dma-names = "rx", "tx"; 358*724ba675SRob Herring}; 359*724ba675SRob Herring 360*724ba675SRob Herring&serial_3 { 361*724ba675SRob Herring clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 362*724ba675SRob Herring clock-names = "uart", "clk_uart_baud0"; 363*724ba675SRob Herring dmas = <&pdma1 17>, <&pdma1 18>; 364*724ba675SRob Herring dma-names = "rx", "tx"; 365*724ba675SRob Herring}; 366*724ba675SRob Herring 367*724ba675SRob Herring&sss { 368*724ba675SRob Herring clocks = <&clock CLK_SSS>; 369*724ba675SRob Herring clock-names = "secss"; 370*724ba675SRob Herring}; 371*724ba675SRob Herring 372*724ba675SRob Herring&sromc { 373*724ba675SRob Herring #address-cells = <2>; 374*724ba675SRob Herring #size-cells = <1>; 375*724ba675SRob Herring ranges = <0 0 0x04000000 0x20000 376*724ba675SRob Herring 1 0 0x05000000 0x20000 377*724ba675SRob Herring 2 0 0x06000000 0x20000 378*724ba675SRob Herring 3 0 0x07000000 0x20000>; 379*724ba675SRob Herring}; 380*724ba675SRob Herring 381*724ba675SRob Herring&trng { 382*724ba675SRob Herring clocks = <&clock CLK_SSS>; 383*724ba675SRob Herring clock-names = "secss"; 384*724ba675SRob Herring}; 385*724ba675SRob Herring 386*724ba675SRob Herring&usbdrd3_0 { 387*724ba675SRob Herring clocks = <&clock CLK_USBD300>; 388*724ba675SRob Herring clock-names = "usbdrd30"; 389*724ba675SRob Herring pinctrl-names = "default"; 390*724ba675SRob Herring pinctrl-0 = <&usb3_0_oc>, <&usb3_0_vbusctrl>; 391*724ba675SRob Herring}; 392*724ba675SRob Herring 393*724ba675SRob Herring&usbdrd_phy0 { 394*724ba675SRob Herring clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; 395*724ba675SRob Herring clock-names = "phy", "ref"; 396*724ba675SRob Herring samsung,pmu-syscon = <&pmu_system_controller>; 397*724ba675SRob Herring}; 398*724ba675SRob Herring 399*724ba675SRob Herring&usbdrd3_1 { 400*724ba675SRob Herring clocks = <&clock CLK_USBD301>; 401*724ba675SRob Herring clock-names = "usbdrd30"; 402*724ba675SRob Herring pinctrl-names = "default"; 403*724ba675SRob Herring pinctrl-0 = <&usb3_1_oc>, <&usb3_1_vbusctrl>; 404*724ba675SRob Herring}; 405*724ba675SRob Herring 406*724ba675SRob Herring&usbdrd_dwc3_1 { 407*724ba675SRob Herring interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 408*724ba675SRob Herring}; 409*724ba675SRob Herring 410*724ba675SRob Herring&usbdrd_phy1 { 411*724ba675SRob Herring clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; 412*724ba675SRob Herring clock-names = "phy", "ref"; 413*724ba675SRob Herring samsung,pmu-syscon = <&pmu_system_controller>; 414*724ba675SRob Herring}; 415*724ba675SRob Herring 416*724ba675SRob Herring&usbhost1 { 417*724ba675SRob Herring clocks = <&clock CLK_USBH20>; 418*724ba675SRob Herring clock-names = "usbhost"; 419*724ba675SRob Herring}; 420*724ba675SRob Herring 421*724ba675SRob Herring&usbhost2 { 422*724ba675SRob Herring clocks = <&clock CLK_USBH20>; 423*724ba675SRob Herring clock-names = "usbhost"; 424*724ba675SRob Herring}; 425*724ba675SRob Herring 426*724ba675SRob Herring&usb2_phy { 427*724ba675SRob Herring clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; 428*724ba675SRob Herring clock-names = "phy", "ref"; 429*724ba675SRob Herring samsung,sysreg-phandle = <&sysreg_system_controller>; 430*724ba675SRob Herring samsung,pmureg-phandle = <&pmu_system_controller>; 431*724ba675SRob Herring}; 432*724ba675SRob Herring 433*724ba675SRob Herring&watchdog { 434*724ba675SRob Herring clocks = <&clock CLK_WDT>; 435*724ba675SRob Herring clock-names = "watchdog"; 436*724ba675SRob Herring samsung,syscon-phandle = <&pmu_system_controller>; 437*724ba675SRob Herring}; 438*724ba675SRob Herring 439*724ba675SRob Herring#include "exynos5410-pinctrl.dtsi" 440*724ba675SRob Herring#include "exynos-syscon-restart.dtsi" 441