1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Samsung Exynos5260 SoC device tree source 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (c) 2013 Samsung Electronics Co., Ltd. 6*724ba675SRob Herring * http://www.samsung.com 7*724ba675SRob Herring */ 8*724ba675SRob Herring 9*724ba675SRob Herring#include <dt-bindings/clock/exynos5260-clk.h> 10*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 11*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 12*724ba675SRob Herring 13*724ba675SRob Herring/ { 14*724ba675SRob Herring compatible = "samsung,exynos5260", "samsung,exynos5"; 15*724ba675SRob Herring interrupt-parent = <&gic>; 16*724ba675SRob Herring #address-cells = <1>; 17*724ba675SRob Herring #size-cells = <1>; 18*724ba675SRob Herring 19*724ba675SRob Herring aliases { 20*724ba675SRob Herring i2c0 = &hsi2c_0; 21*724ba675SRob Herring i2c1 = &hsi2c_1; 22*724ba675SRob Herring i2c2 = &hsi2c_2; 23*724ba675SRob Herring i2c3 = &hsi2c_3; 24*724ba675SRob Herring pinctrl0 = &pinctrl_0; 25*724ba675SRob Herring pinctrl1 = &pinctrl_1; 26*724ba675SRob Herring pinctrl2 = &pinctrl_2; 27*724ba675SRob Herring serial0 = &uart0; 28*724ba675SRob Herring serial1 = &uart1; 29*724ba675SRob Herring serial2 = &uart2; 30*724ba675SRob Herring serial3 = &uart3; 31*724ba675SRob Herring }; 32*724ba675SRob Herring 33*724ba675SRob Herring cpus { 34*724ba675SRob Herring #address-cells = <1>; 35*724ba675SRob Herring #size-cells = <0>; 36*724ba675SRob Herring 37*724ba675SRob Herring cpu-map { 38*724ba675SRob Herring cluster0 { 39*724ba675SRob Herring core0 { 40*724ba675SRob Herring cpu = <&cpu0>; 41*724ba675SRob Herring }; 42*724ba675SRob Herring core1 { 43*724ba675SRob Herring cpu = <&cpu1>; 44*724ba675SRob Herring }; 45*724ba675SRob Herring }; 46*724ba675SRob Herring 47*724ba675SRob Herring cluster1 { 48*724ba675SRob Herring core0 { 49*724ba675SRob Herring cpu = <&cpu2>; 50*724ba675SRob Herring }; 51*724ba675SRob Herring core1 { 52*724ba675SRob Herring cpu = <&cpu3>; 53*724ba675SRob Herring }; 54*724ba675SRob Herring core2 { 55*724ba675SRob Herring cpu = <&cpu4>; 56*724ba675SRob Herring }; 57*724ba675SRob Herring core3 { 58*724ba675SRob Herring cpu = <&cpu5>; 59*724ba675SRob Herring }; 60*724ba675SRob Herring }; 61*724ba675SRob Herring }; 62*724ba675SRob Herring 63*724ba675SRob Herring cpu0: cpu@0 { 64*724ba675SRob Herring device_type = "cpu"; 65*724ba675SRob Herring compatible = "arm,cortex-a15"; 66*724ba675SRob Herring reg = <0x0>; 67*724ba675SRob Herring cci-control-port = <&cci_control1>; 68*724ba675SRob Herring }; 69*724ba675SRob Herring 70*724ba675SRob Herring cpu1: cpu@1 { 71*724ba675SRob Herring device_type = "cpu"; 72*724ba675SRob Herring compatible = "arm,cortex-a15"; 73*724ba675SRob Herring reg = <0x1>; 74*724ba675SRob Herring cci-control-port = <&cci_control1>; 75*724ba675SRob Herring }; 76*724ba675SRob Herring 77*724ba675SRob Herring cpu2: cpu@100 { 78*724ba675SRob Herring device_type = "cpu"; 79*724ba675SRob Herring compatible = "arm,cortex-a7"; 80*724ba675SRob Herring reg = <0x100>; 81*724ba675SRob Herring cci-control-port = <&cci_control0>; 82*724ba675SRob Herring }; 83*724ba675SRob Herring 84*724ba675SRob Herring cpu3: cpu@101 { 85*724ba675SRob Herring device_type = "cpu"; 86*724ba675SRob Herring compatible = "arm,cortex-a7"; 87*724ba675SRob Herring reg = <0x101>; 88*724ba675SRob Herring cci-control-port = <&cci_control0>; 89*724ba675SRob Herring }; 90*724ba675SRob Herring 91*724ba675SRob Herring cpu4: cpu@102 { 92*724ba675SRob Herring device_type = "cpu"; 93*724ba675SRob Herring compatible = "arm,cortex-a7"; 94*724ba675SRob Herring reg = <0x102>; 95*724ba675SRob Herring cci-control-port = <&cci_control0>; 96*724ba675SRob Herring }; 97*724ba675SRob Herring 98*724ba675SRob Herring cpu5: cpu@103 { 99*724ba675SRob Herring device_type = "cpu"; 100*724ba675SRob Herring compatible = "arm,cortex-a7"; 101*724ba675SRob Herring reg = <0x103>; 102*724ba675SRob Herring cci-control-port = <&cci_control0>; 103*724ba675SRob Herring }; 104*724ba675SRob Herring }; 105*724ba675SRob Herring 106*724ba675SRob Herring soc: soc { 107*724ba675SRob Herring compatible = "simple-bus"; 108*724ba675SRob Herring #address-cells = <1>; 109*724ba675SRob Herring #size-cells = <1>; 110*724ba675SRob Herring ranges; 111*724ba675SRob Herring 112*724ba675SRob Herring clock_top: clock-controller@10010000 { 113*724ba675SRob Herring compatible = "samsung,exynos5260-clock-top"; 114*724ba675SRob Herring reg = <0x10010000 0x10000>; 115*724ba675SRob Herring #clock-cells = <1>; 116*724ba675SRob Herring clocks = <&fin_pll>, 117*724ba675SRob Herring <&clock_mif MIF_DOUT_MEM_PLL>, 118*724ba675SRob Herring <&clock_mif MIF_DOUT_BUS_PLL>, 119*724ba675SRob Herring <&clock_mif MIF_DOUT_MEDIA_PLL>; 120*724ba675SRob Herring clock-names = "fin_pll", 121*724ba675SRob Herring "dout_mem_pll", 122*724ba675SRob Herring "dout_bus_pll", 123*724ba675SRob Herring "dout_media_pll"; 124*724ba675SRob Herring }; 125*724ba675SRob Herring 126*724ba675SRob Herring clock_peri: clock-controller@10200000 { 127*724ba675SRob Herring compatible = "samsung,exynos5260-clock-peri"; 128*724ba675SRob Herring reg = <0x10200000 0x10000>; 129*724ba675SRob Herring #clock-cells = <1>; 130*724ba675SRob Herring clocks = <&fin_pll>, 131*724ba675SRob Herring <&ioclk_pcm>, 132*724ba675SRob Herring <&ioclk_i2s>, 133*724ba675SRob Herring <&ioclk_spdif>, 134*724ba675SRob Herring <&fin_pll>, 135*724ba675SRob Herring <&clock_top TOP_DOUT_ACLK_PERI_66>, 136*724ba675SRob Herring <&clock_top TOP_DOUT_SCLK_PERI_UART0>, 137*724ba675SRob Herring <&clock_top TOP_DOUT_SCLK_PERI_UART1>, 138*724ba675SRob Herring <&clock_top TOP_DOUT_SCLK_PERI_UART2>, 139*724ba675SRob Herring <&clock_top TOP_DOUT_SCLK_PERI_SPI0_B>, 140*724ba675SRob Herring <&clock_top TOP_DOUT_SCLK_PERI_SPI1_B>, 141*724ba675SRob Herring <&clock_top TOP_DOUT_SCLK_PERI_SPI2_B>, 142*724ba675SRob Herring <&clock_top TOP_DOUT_ACLK_PERI_AUD>; 143*724ba675SRob Herring clock-names = "fin_pll", 144*724ba675SRob Herring "ioclk_pcm_extclk", 145*724ba675SRob Herring "ioclk_i2s_cdclk", 146*724ba675SRob Herring "ioclk_spdif_extclk", 147*724ba675SRob Herring "phyclk_hdmi_phy_ref_cko", 148*724ba675SRob Herring "dout_aclk_peri_66", 149*724ba675SRob Herring "dout_sclk_peri_uart0", 150*724ba675SRob Herring "dout_sclk_peri_uart1", 151*724ba675SRob Herring "dout_sclk_peri_uart2", 152*724ba675SRob Herring "dout_sclk_peri_spi0_b", 153*724ba675SRob Herring "dout_sclk_peri_spi1_b", 154*724ba675SRob Herring "dout_sclk_peri_spi2_b", 155*724ba675SRob Herring "dout_aclk_peri_aud"; 156*724ba675SRob Herring }; 157*724ba675SRob Herring 158*724ba675SRob Herring clock_egl: clock-controller@10600000 { 159*724ba675SRob Herring compatible = "samsung,exynos5260-clock-egl"; 160*724ba675SRob Herring reg = <0x10600000 0x10000>; 161*724ba675SRob Herring #clock-cells = <1>; 162*724ba675SRob Herring clocks = <&fin_pll>, 163*724ba675SRob Herring <&clock_mif MIF_DOUT_BUS_PLL>; 164*724ba675SRob Herring clock-names = "fin_pll", 165*724ba675SRob Herring "dout_bus_pll"; 166*724ba675SRob Herring }; 167*724ba675SRob Herring 168*724ba675SRob Herring clock_kfc: clock-controller@10700000 { 169*724ba675SRob Herring compatible = "samsung,exynos5260-clock-kfc"; 170*724ba675SRob Herring reg = <0x10700000 0x10000>; 171*724ba675SRob Herring #clock-cells = <1>; 172*724ba675SRob Herring clocks = <&fin_pll>, 173*724ba675SRob Herring <&clock_mif MIF_DOUT_MEDIA_PLL>; 174*724ba675SRob Herring clock-names = "fin_pll", 175*724ba675SRob Herring "dout_media_pll"; 176*724ba675SRob Herring }; 177*724ba675SRob Herring 178*724ba675SRob Herring clock_g2d: clock-controller@10a00000 { 179*724ba675SRob Herring compatible = "samsung,exynos5260-clock-g2d"; 180*724ba675SRob Herring reg = <0x10a00000 0x10000>; 181*724ba675SRob Herring #clock-cells = <1>; 182*724ba675SRob Herring clocks = <&fin_pll>, 183*724ba675SRob Herring <&clock_top TOP_DOUT_ACLK_G2D_333>; 184*724ba675SRob Herring clock-names = "fin_pll", 185*724ba675SRob Herring "dout_aclk_g2d_333"; 186*724ba675SRob Herring }; 187*724ba675SRob Herring 188*724ba675SRob Herring clock_mif: clock-controller@10ce0000 { 189*724ba675SRob Herring compatible = "samsung,exynos5260-clock-mif"; 190*724ba675SRob Herring reg = <0x10ce0000 0x10000>; 191*724ba675SRob Herring #clock-cells = <1>; 192*724ba675SRob Herring clocks = <&fin_pll>; 193*724ba675SRob Herring clock-names = "fin_pll"; 194*724ba675SRob Herring }; 195*724ba675SRob Herring 196*724ba675SRob Herring clock_mfc: clock-controller@11090000 { 197*724ba675SRob Herring compatible = "samsung,exynos5260-clock-mfc"; 198*724ba675SRob Herring reg = <0x11090000 0x10000>; 199*724ba675SRob Herring #clock-cells = <1>; 200*724ba675SRob Herring clocks = <&fin_pll>, 201*724ba675SRob Herring <&clock_top TOP_DOUT_ACLK_MFC_333>; 202*724ba675SRob Herring clock-names = "fin_pll", 203*724ba675SRob Herring "dout_aclk_mfc_333"; 204*724ba675SRob Herring }; 205*724ba675SRob Herring 206*724ba675SRob Herring clock_g3d: clock-controller@11830000 { 207*724ba675SRob Herring compatible = "samsung,exynos5260-clock-g3d"; 208*724ba675SRob Herring reg = <0x11830000 0x10000>; 209*724ba675SRob Herring #clock-cells = <1>; 210*724ba675SRob Herring clocks = <&fin_pll>; 211*724ba675SRob Herring clock-names = "fin_pll"; 212*724ba675SRob Herring }; 213*724ba675SRob Herring 214*724ba675SRob Herring clock_fsys: clock-controller@122e0000 { 215*724ba675SRob Herring compatible = "samsung,exynos5260-clock-fsys"; 216*724ba675SRob Herring reg = <0x122e0000 0x10000>; 217*724ba675SRob Herring #clock-cells = <1>; 218*724ba675SRob Herring clocks = <&fin_pll>, 219*724ba675SRob Herring <&fin_pll>, 220*724ba675SRob Herring <&fin_pll>, 221*724ba675SRob Herring <&fin_pll>, 222*724ba675SRob Herring <&fin_pll>, 223*724ba675SRob Herring <&fin_pll>, 224*724ba675SRob Herring <&clock_top TOP_DOUT_ACLK_FSYS_200>; 225*724ba675SRob Herring clock-names = "fin_pll", 226*724ba675SRob Herring "phyclk_usbhost20_phy_phyclock", 227*724ba675SRob Herring "phyclk_usbhost20_phy_freeclk", 228*724ba675SRob Herring "phyclk_usbhost20_phy_clk48mohci", 229*724ba675SRob Herring "phyclk_usbdrd30_udrd30_pipe_pclk", 230*724ba675SRob Herring "phyclk_usbdrd30_udrd30_phyclock", 231*724ba675SRob Herring "dout_aclk_fsys_200"; 232*724ba675SRob Herring }; 233*724ba675SRob Herring 234*724ba675SRob Herring clock_aud: clock-controller@128c0000 { 235*724ba675SRob Herring compatible = "samsung,exynos5260-clock-aud"; 236*724ba675SRob Herring reg = <0x128c0000 0x10000>; 237*724ba675SRob Herring #clock-cells = <1>; 238*724ba675SRob Herring clocks = <&fin_pll>, 239*724ba675SRob Herring <&clock_top TOP_FOUT_AUD_PLL>, 240*724ba675SRob Herring <&ioclk_i2s>, 241*724ba675SRob Herring <&ioclk_pcm>; 242*724ba675SRob Herring clock-names = "fin_pll", 243*724ba675SRob Herring "fout_aud_pll", 244*724ba675SRob Herring "ioclk_i2s_cdclk", 245*724ba675SRob Herring "ioclk_pcm_extclk"; 246*724ba675SRob Herring }; 247*724ba675SRob Herring 248*724ba675SRob Herring clock_isp: clock-controller@133c0000 { 249*724ba675SRob Herring compatible = "samsung,exynos5260-clock-isp"; 250*724ba675SRob Herring reg = <0x133c0000 0x10000>; 251*724ba675SRob Herring #clock-cells = <1>; 252*724ba675SRob Herring clocks = <&fin_pll>, 253*724ba675SRob Herring <&clock_top TOP_DOUT_ACLK_ISP1_266>, 254*724ba675SRob Herring <&clock_top TOP_DOUT_ACLK_ISP1_400>, 255*724ba675SRob Herring <&clock_top TOP_MOUT_ACLK_ISP1_266>; 256*724ba675SRob Herring clock-names = "fin_pll", 257*724ba675SRob Herring "dout_aclk_isp1_266", 258*724ba675SRob Herring "dout_aclk_isp1_400", 259*724ba675SRob Herring "mout_aclk_isp1_266"; 260*724ba675SRob Herring }; 261*724ba675SRob Herring 262*724ba675SRob Herring clock_gscl: clock-controller@13f00000 { 263*724ba675SRob Herring compatible = "samsung,exynos5260-clock-gscl"; 264*724ba675SRob Herring reg = <0x13f00000 0x10000>; 265*724ba675SRob Herring #clock-cells = <1>; 266*724ba675SRob Herring clocks = <&fin_pll>, 267*724ba675SRob Herring <&clock_top TOP_DOUT_ACLK_GSCL_400>, 268*724ba675SRob Herring <&clock_top TOP_DOUT_ACLK_GSCL_333>; 269*724ba675SRob Herring clock-names = "fin_pll", 270*724ba675SRob Herring "dout_aclk_gscl_400", 271*724ba675SRob Herring "dout_aclk_gscl_333"; 272*724ba675SRob Herring }; 273*724ba675SRob Herring 274*724ba675SRob Herring clock_disp: clock-controller@14550000 { 275*724ba675SRob Herring compatible = "samsung,exynos5260-clock-disp"; 276*724ba675SRob Herring reg = <0x14550000 0x10000>; 277*724ba675SRob Herring #clock-cells = <1>; 278*724ba675SRob Herring clocks = <&fin_pll>, 279*724ba675SRob Herring <&fin_pll>, 280*724ba675SRob Herring <&fin_pll>, 281*724ba675SRob Herring <&fin_pll>, 282*724ba675SRob Herring <&fin_pll>, 283*724ba675SRob Herring <&fin_pll>, 284*724ba675SRob Herring <&fin_pll>, 285*724ba675SRob Herring <&fin_pll>, 286*724ba675SRob Herring <&fin_pll>, 287*724ba675SRob Herring <&fin_pll>, 288*724ba675SRob Herring <&fin_pll>, 289*724ba675SRob Herring <&fin_pll>, 290*724ba675SRob Herring <&fin_pll>, 291*724ba675SRob Herring <&fin_pll>, 292*724ba675SRob Herring <&ioclk_spdif>, 293*724ba675SRob Herring <&clock_top TOP_DOUT_ACLK_PERI_AUD>, 294*724ba675SRob Herring <&clock_top TOP_DOUT_ACLK_DISP_222>, 295*724ba675SRob Herring <&clock_top TOP_DOUT_SCLK_DISP_PIXEL>, 296*724ba675SRob Herring <&clock_top TOP_DOUT_ACLK_DISP_333>; 297*724ba675SRob Herring clock-names = "fin_pll", 298*724ba675SRob Herring "phyclk_dptx_phy_ch3_txd_clk", 299*724ba675SRob Herring "phyclk_dptx_phy_ch2_txd_clk", 300*724ba675SRob Herring "phyclk_dptx_phy_ch1_txd_clk", 301*724ba675SRob Herring "phyclk_dptx_phy_ch0_txd_clk", 302*724ba675SRob Herring "phyclk_hdmi_phy_tmds_clko", 303*724ba675SRob Herring "phyclk_hdmi_phy_ref_clko", 304*724ba675SRob Herring "phyclk_hdmi_phy_pixel_clko", 305*724ba675SRob Herring "phyclk_hdmi_link_o_tmds_clkhi", 306*724ba675SRob Herring "phyclk_mipi_dphy_4l_m_txbyte_clkhs", 307*724ba675SRob Herring "phyclk_dptx_phy_o_ref_clk_24m", 308*724ba675SRob Herring "phyclk_dptx_phy_clk_div2", 309*724ba675SRob Herring "phyclk_mipi_dphy_4l_m_rxclkesc0", 310*724ba675SRob Herring "phyclk_hdmi_phy_ref_cko", 311*724ba675SRob Herring "ioclk_spdif_extclk", 312*724ba675SRob Herring "dout_aclk_peri_aud", 313*724ba675SRob Herring "dout_aclk_disp_222", 314*724ba675SRob Herring "dout_sclk_disp_pixel", 315*724ba675SRob Herring "dout_aclk_disp_333"; 316*724ba675SRob Herring }; 317*724ba675SRob Herring 318*724ba675SRob Herring gic: interrupt-controller@10481000 { 319*724ba675SRob Herring compatible = "arm,gic-400", "arm,cortex-a15-gic"; 320*724ba675SRob Herring #interrupt-cells = <3>; 321*724ba675SRob Herring interrupt-controller; 322*724ba675SRob Herring reg = <0x10481000 0x1000>, 323*724ba675SRob Herring <0x10482000 0x2000>, 324*724ba675SRob Herring <0x10484000 0x2000>, 325*724ba675SRob Herring <0x10486000 0x2000>; 326*724ba675SRob Herring interrupts = <GIC_PPI 9 327*724ba675SRob Herring (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 328*724ba675SRob Herring }; 329*724ba675SRob Herring 330*724ba675SRob Herring chipid: chipid@10000000 { 331*724ba675SRob Herring compatible = "samsung,exynos4210-chipid"; 332*724ba675SRob Herring reg = <0x10000000 0x100>; 333*724ba675SRob Herring }; 334*724ba675SRob Herring 335*724ba675SRob Herring mct: timer@100b0000 { 336*724ba675SRob Herring compatible = "samsung,exynos5260-mct", 337*724ba675SRob Herring "samsung,exynos4210-mct"; 338*724ba675SRob Herring reg = <0x100b0000 0x1000>; 339*724ba675SRob Herring clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; 340*724ba675SRob Herring clock-names = "fin_pll", "mct"; 341*724ba675SRob Herring interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 342*724ba675SRob Herring <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 343*724ba675SRob Herring <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 344*724ba675SRob Herring <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 345*724ba675SRob Herring <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 346*724ba675SRob Herring <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 347*724ba675SRob Herring <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 348*724ba675SRob Herring <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 349*724ba675SRob Herring <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 350*724ba675SRob Herring <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 351*724ba675SRob Herring <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 352*724ba675SRob Herring <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 353*724ba675SRob Herring }; 354*724ba675SRob Herring 355*724ba675SRob Herring cci: cci@10f00000 { 356*724ba675SRob Herring compatible = "arm,cci-400"; 357*724ba675SRob Herring #address-cells = <1>; 358*724ba675SRob Herring #size-cells = <1>; 359*724ba675SRob Herring reg = <0x10f00000 0x1000>; 360*724ba675SRob Herring ranges = <0x0 0x10f00000 0x6000>; 361*724ba675SRob Herring 362*724ba675SRob Herring cci_control0: slave-if@4000 { 363*724ba675SRob Herring compatible = "arm,cci-400-ctrl-if"; 364*724ba675SRob Herring interface-type = "ace"; 365*724ba675SRob Herring reg = <0x4000 0x1000>; 366*724ba675SRob Herring }; 367*724ba675SRob Herring 368*724ba675SRob Herring cci_control1: slave-if@5000 { 369*724ba675SRob Herring compatible = "arm,cci-400-ctrl-if"; 370*724ba675SRob Herring interface-type = "ace"; 371*724ba675SRob Herring reg = <0x5000 0x1000>; 372*724ba675SRob Herring }; 373*724ba675SRob Herring }; 374*724ba675SRob Herring 375*724ba675SRob Herring pinctrl_0: pinctrl@11600000 { 376*724ba675SRob Herring compatible = "samsung,exynos5260-pinctrl"; 377*724ba675SRob Herring reg = <0x11600000 0x1000>; 378*724ba675SRob Herring interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 379*724ba675SRob Herring 380*724ba675SRob Herring wakeup-interrupt-controller { 381*724ba675SRob Herring compatible = "samsung,exynos4210-wakeup-eint"; 382*724ba675SRob Herring interrupt-parent = <&gic>; 383*724ba675SRob Herring interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 384*724ba675SRob Herring }; 385*724ba675SRob Herring }; 386*724ba675SRob Herring 387*724ba675SRob Herring pinctrl_1: pinctrl@12290000 { 388*724ba675SRob Herring compatible = "samsung,exynos5260-pinctrl"; 389*724ba675SRob Herring reg = <0x12290000 0x1000>; 390*724ba675SRob Herring interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 391*724ba675SRob Herring }; 392*724ba675SRob Herring 393*724ba675SRob Herring pinctrl_2: pinctrl@128b0000 { 394*724ba675SRob Herring compatible = "samsung,exynos5260-pinctrl"; 395*724ba675SRob Herring reg = <0x128b0000 0x1000>; 396*724ba675SRob Herring interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 397*724ba675SRob Herring }; 398*724ba675SRob Herring 399*724ba675SRob Herring pmu_system_controller: system-controller@10d50000 { 400*724ba675SRob Herring compatible = "samsung,exynos5260-pmu", "syscon"; 401*724ba675SRob Herring reg = <0x10d50000 0x10000>; 402*724ba675SRob Herring }; 403*724ba675SRob Herring 404*724ba675SRob Herring uart0: serial@12c00000 { 405*724ba675SRob Herring compatible = "samsung,exynos4210-uart"; 406*724ba675SRob Herring reg = <0x12c00000 0x100>; 407*724ba675SRob Herring interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 408*724ba675SRob Herring clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>; 409*724ba675SRob Herring clock-names = "uart", "clk_uart_baud0"; 410*724ba675SRob Herring status = "disabled"; 411*724ba675SRob Herring }; 412*724ba675SRob Herring 413*724ba675SRob Herring uart1: serial@12c10000 { 414*724ba675SRob Herring compatible = "samsung,exynos4210-uart"; 415*724ba675SRob Herring reg = <0x12c10000 0x100>; 416*724ba675SRob Herring interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 417*724ba675SRob Herring clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>; 418*724ba675SRob Herring clock-names = "uart", "clk_uart_baud0"; 419*724ba675SRob Herring status = "disabled"; 420*724ba675SRob Herring }; 421*724ba675SRob Herring 422*724ba675SRob Herring uart2: serial@12c20000 { 423*724ba675SRob Herring compatible = "samsung,exynos4210-uart"; 424*724ba675SRob Herring reg = <0x12c20000 0x100>; 425*724ba675SRob Herring interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 426*724ba675SRob Herring clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>; 427*724ba675SRob Herring clock-names = "uart", "clk_uart_baud0"; 428*724ba675SRob Herring status = "disabled"; 429*724ba675SRob Herring }; 430*724ba675SRob Herring 431*724ba675SRob Herring uart3: serial@12860000 { 432*724ba675SRob Herring compatible = "samsung,exynos4210-uart"; 433*724ba675SRob Herring reg = <0x12860000 0x100>; 434*724ba675SRob Herring interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 435*724ba675SRob Herring clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>; 436*724ba675SRob Herring clock-names = "uart", "clk_uart_baud0"; 437*724ba675SRob Herring status = "disabled"; 438*724ba675SRob Herring }; 439*724ba675SRob Herring 440*724ba675SRob Herring mmc_0: mmc@12140000 { 441*724ba675SRob Herring compatible = "samsung,exynos5250-dw-mshc"; 442*724ba675SRob Herring reg = <0x12140000 0x2000>; 443*724ba675SRob Herring interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 444*724ba675SRob Herring #address-cells = <1>; 445*724ba675SRob Herring #size-cells = <0>; 446*724ba675SRob Herring clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>; 447*724ba675SRob Herring clock-names = "biu", "ciu"; 448*724ba675SRob Herring assigned-clocks = 449*724ba675SRob Herring <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>, 450*724ba675SRob Herring <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B>, 451*724ba675SRob Herring <&clock_top TOP_SCLK_MMC0>; 452*724ba675SRob Herring assigned-clock-parents = 453*724ba675SRob Herring <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, 454*724ba675SRob Herring <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>; 455*724ba675SRob Herring assigned-clock-rates = <0>, <0>, <800000000>; 456*724ba675SRob Herring fifo-depth = <64>; 457*724ba675SRob Herring status = "disabled"; 458*724ba675SRob Herring }; 459*724ba675SRob Herring 460*724ba675SRob Herring mmc_1: mmc@12150000 { 461*724ba675SRob Herring compatible = "samsung,exynos5250-dw-mshc"; 462*724ba675SRob Herring reg = <0x12150000 0x2000>; 463*724ba675SRob Herring interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 464*724ba675SRob Herring #address-cells = <1>; 465*724ba675SRob Herring #size-cells = <0>; 466*724ba675SRob Herring clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>; 467*724ba675SRob Herring clock-names = "biu", "ciu"; 468*724ba675SRob Herring assigned-clocks = 469*724ba675SRob Herring <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>, 470*724ba675SRob Herring <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B>, 471*724ba675SRob Herring <&clock_top TOP_SCLK_MMC1>; 472*724ba675SRob Herring assigned-clock-parents = 473*724ba675SRob Herring <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, 474*724ba675SRob Herring <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>; 475*724ba675SRob Herring assigned-clock-rates = <0>, <0>, <800000000>; 476*724ba675SRob Herring fifo-depth = <64>; 477*724ba675SRob Herring status = "disabled"; 478*724ba675SRob Herring }; 479*724ba675SRob Herring 480*724ba675SRob Herring mmc_2: mmc@12160000 { 481*724ba675SRob Herring compatible = "samsung,exynos5250-dw-mshc"; 482*724ba675SRob Herring reg = <0x12160000 0x2000>; 483*724ba675SRob Herring interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 484*724ba675SRob Herring #address-cells = <1>; 485*724ba675SRob Herring #size-cells = <0>; 486*724ba675SRob Herring clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>; 487*724ba675SRob Herring clock-names = "biu", "ciu"; 488*724ba675SRob Herring assigned-clocks = 489*724ba675SRob Herring <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>, 490*724ba675SRob Herring <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B>, 491*724ba675SRob Herring <&clock_top TOP_SCLK_MMC2>; 492*724ba675SRob Herring assigned-clock-parents = 493*724ba675SRob Herring <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, 494*724ba675SRob Herring <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>; 495*724ba675SRob Herring assigned-clock-rates = <0>, <0>, <800000000>; 496*724ba675SRob Herring fifo-depth = <64>; 497*724ba675SRob Herring status = "disabled"; 498*724ba675SRob Herring }; 499*724ba675SRob Herring 500*724ba675SRob Herring hsi2c_0: i2c@12da0000 { 501*724ba675SRob Herring compatible = "samsung,exynos5260-hsi2c"; 502*724ba675SRob Herring reg = <0x12da0000 0x1000>; 503*724ba675SRob Herring interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 504*724ba675SRob Herring #address-cells = <1>; 505*724ba675SRob Herring #size-cells = <0>; 506*724ba675SRob Herring pinctrl-names = "default"; 507*724ba675SRob Herring pinctrl-0 = <&i2c0_hs_bus>; 508*724ba675SRob Herring clocks = <&clock_peri PERI_CLK_HSIC0>; 509*724ba675SRob Herring clock-names = "hsi2c"; 510*724ba675SRob Herring status = "disabled"; 511*724ba675SRob Herring }; 512*724ba675SRob Herring 513*724ba675SRob Herring hsi2c_1: i2c@12db0000 { 514*724ba675SRob Herring compatible = "samsung,exynos5260-hsi2c"; 515*724ba675SRob Herring reg = <0x12db0000 0x1000>; 516*724ba675SRob Herring interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 517*724ba675SRob Herring #address-cells = <1>; 518*724ba675SRob Herring #size-cells = <0>; 519*724ba675SRob Herring pinctrl-names = "default"; 520*724ba675SRob Herring pinctrl-0 = <&i2c1_hs_bus>; 521*724ba675SRob Herring clocks = <&clock_peri PERI_CLK_HSIC1>; 522*724ba675SRob Herring clock-names = "hsi2c"; 523*724ba675SRob Herring status = "disabled"; 524*724ba675SRob Herring }; 525*724ba675SRob Herring 526*724ba675SRob Herring hsi2c_2: i2c@12dc0000 { 527*724ba675SRob Herring compatible = "samsung,exynos5260-hsi2c"; 528*724ba675SRob Herring reg = <0x12dc0000 0x1000>; 529*724ba675SRob Herring interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 530*724ba675SRob Herring #address-cells = <1>; 531*724ba675SRob Herring #size-cells = <0>; 532*724ba675SRob Herring pinctrl-names = "default"; 533*724ba675SRob Herring pinctrl-0 = <&i2c2_hs_bus>; 534*724ba675SRob Herring clocks = <&clock_peri PERI_CLK_HSIC2>; 535*724ba675SRob Herring clock-names = "hsi2c"; 536*724ba675SRob Herring status = "disabled"; 537*724ba675SRob Herring }; 538*724ba675SRob Herring 539*724ba675SRob Herring hsi2c_3: i2c@12dd0000 { 540*724ba675SRob Herring compatible = "samsung,exynos5260-hsi2c"; 541*724ba675SRob Herring reg = <0x12dd0000 0x1000>; 542*724ba675SRob Herring interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 543*724ba675SRob Herring #address-cells = <1>; 544*724ba675SRob Herring #size-cells = <0>; 545*724ba675SRob Herring pinctrl-names = "default"; 546*724ba675SRob Herring pinctrl-0 = <&i2c3_hs_bus>; 547*724ba675SRob Herring clocks = <&clock_peri PERI_CLK_HSIC3>; 548*724ba675SRob Herring clock-names = "hsi2c"; 549*724ba675SRob Herring status = "disabled"; 550*724ba675SRob Herring }; 551*724ba675SRob Herring }; 552*724ba675SRob Herring}; 553*724ba675SRob Herring 554*724ba675SRob Herring#include "exynos5260-pinctrl.dtsi" 555