1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Samsung's Exynos3250 SoC device tree source 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (c) 2014 Samsung Electronics Co., Ltd. 6*724ba675SRob Herring * http://www.samsung.com 7*724ba675SRob Herring * 8*724ba675SRob Herring * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250 9*724ba675SRob Herring * based board files can include this file and provide values for board specific 10*724ba675SRob Herring * bindings. 11*724ba675SRob Herring * 12*724ba675SRob Herring * Note: This file does not include device nodes for all the controllers in 13*724ba675SRob Herring * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional 14*724ba675SRob Herring * nodes can be added to this file. 15*724ba675SRob Herring */ 16*724ba675SRob Herring 17*724ba675SRob Herring#include "exynos4-cpu-thermal.dtsi" 18*724ba675SRob Herring#include <dt-bindings/clock/exynos3250.h> 19*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 20*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 21*724ba675SRob Herring 22*724ba675SRob Herring/ { 23*724ba675SRob Herring compatible = "samsung,exynos3250"; 24*724ba675SRob Herring interrupt-parent = <&gic>; 25*724ba675SRob Herring #address-cells = <1>; 26*724ba675SRob Herring #size-cells = <1>; 27*724ba675SRob Herring 28*724ba675SRob Herring aliases { 29*724ba675SRob Herring pinctrl0 = &pinctrl_0; 30*724ba675SRob Herring pinctrl1 = &pinctrl_1; 31*724ba675SRob Herring spi0 = &spi_0; 32*724ba675SRob Herring spi1 = &spi_1; 33*724ba675SRob Herring i2c0 = &i2c_0; 34*724ba675SRob Herring i2c1 = &i2c_1; 35*724ba675SRob Herring i2c2 = &i2c_2; 36*724ba675SRob Herring i2c3 = &i2c_3; 37*724ba675SRob Herring i2c4 = &i2c_4; 38*724ba675SRob Herring i2c5 = &i2c_5; 39*724ba675SRob Herring i2c6 = &i2c_6; 40*724ba675SRob Herring i2c7 = &i2c_7; 41*724ba675SRob Herring serial0 = &serial_0; 42*724ba675SRob Herring serial1 = &serial_1; 43*724ba675SRob Herring serial2 = &serial_2; 44*724ba675SRob Herring }; 45*724ba675SRob Herring 46*724ba675SRob Herring bus_dmc: bus-dmc { 47*724ba675SRob Herring compatible = "samsung,exynos-bus"; 48*724ba675SRob Herring clocks = <&cmu_dmc CLK_DIV_DMC>; 49*724ba675SRob Herring clock-names = "bus"; 50*724ba675SRob Herring operating-points-v2 = <&bus_dmc_opp_table>; 51*724ba675SRob Herring status = "disabled"; 52*724ba675SRob Herring 53*724ba675SRob Herring bus_dmc_opp_table: opp-table { 54*724ba675SRob Herring compatible = "operating-points-v2"; 55*724ba675SRob Herring 56*724ba675SRob Herring opp-50000000 { 57*724ba675SRob Herring opp-hz = /bits/ 64 <50000000>; 58*724ba675SRob Herring opp-microvolt = <800000>; 59*724ba675SRob Herring }; 60*724ba675SRob Herring opp-100000000 { 61*724ba675SRob Herring opp-hz = /bits/ 64 <100000000>; 62*724ba675SRob Herring opp-microvolt = <800000>; 63*724ba675SRob Herring }; 64*724ba675SRob Herring opp-134000000 { 65*724ba675SRob Herring opp-hz = /bits/ 64 <134000000>; 66*724ba675SRob Herring opp-microvolt = <800000>; 67*724ba675SRob Herring }; 68*724ba675SRob Herring opp-200000000 { 69*724ba675SRob Herring opp-hz = /bits/ 64 <200000000>; 70*724ba675SRob Herring opp-microvolt = <825000>; 71*724ba675SRob Herring }; 72*724ba675SRob Herring opp-400000000 { 73*724ba675SRob Herring opp-hz = /bits/ 64 <400000000>; 74*724ba675SRob Herring opp-microvolt = <875000>; 75*724ba675SRob Herring }; 76*724ba675SRob Herring }; 77*724ba675SRob Herring }; 78*724ba675SRob Herring 79*724ba675SRob Herring bus_fsys: bus-fsys { 80*724ba675SRob Herring compatible = "samsung,exynos-bus"; 81*724ba675SRob Herring clocks = <&cmu CLK_DIV_ACLK_200>; 82*724ba675SRob Herring clock-names = "bus"; 83*724ba675SRob Herring operating-points-v2 = <&bus_leftbus_opp_table>; 84*724ba675SRob Herring status = "disabled"; 85*724ba675SRob Herring }; 86*724ba675SRob Herring 87*724ba675SRob Herring bus_isp: bus-isp { 88*724ba675SRob Herring compatible = "samsung,exynos-bus"; 89*724ba675SRob Herring clocks = <&cmu CLK_DIV_ACLK_266>; 90*724ba675SRob Herring clock-names = "bus"; 91*724ba675SRob Herring operating-points-v2 = <&bus_isp_opp_table>; 92*724ba675SRob Herring status = "disabled"; 93*724ba675SRob Herring 94*724ba675SRob Herring bus_isp_opp_table: opp-table { 95*724ba675SRob Herring compatible = "operating-points-v2"; 96*724ba675SRob Herring 97*724ba675SRob Herring opp-50000000 { 98*724ba675SRob Herring opp-hz = /bits/ 64 <50000000>; 99*724ba675SRob Herring }; 100*724ba675SRob Herring opp-80000000 { 101*724ba675SRob Herring opp-hz = /bits/ 64 <80000000>; 102*724ba675SRob Herring }; 103*724ba675SRob Herring opp-100000000 { 104*724ba675SRob Herring opp-hz = /bits/ 64 <100000000>; 105*724ba675SRob Herring }; 106*724ba675SRob Herring opp-200000000 { 107*724ba675SRob Herring opp-hz = /bits/ 64 <200000000>; 108*724ba675SRob Herring }; 109*724ba675SRob Herring opp-300000000 { 110*724ba675SRob Herring opp-hz = /bits/ 64 <300000000>; 111*724ba675SRob Herring }; 112*724ba675SRob Herring }; 113*724ba675SRob Herring }; 114*724ba675SRob Herring 115*724ba675SRob Herring bus_lcd0: bus-lcd0 { 116*724ba675SRob Herring compatible = "samsung,exynos-bus"; 117*724ba675SRob Herring clocks = <&cmu CLK_DIV_ACLK_160>; 118*724ba675SRob Herring clock-names = "bus"; 119*724ba675SRob Herring operating-points-v2 = <&bus_leftbus_opp_table>; 120*724ba675SRob Herring status = "disabled"; 121*724ba675SRob Herring }; 122*724ba675SRob Herring 123*724ba675SRob Herring bus_leftbus: bus-leftbus { 124*724ba675SRob Herring compatible = "samsung,exynos-bus"; 125*724ba675SRob Herring clocks = <&cmu CLK_DIV_GDL>; 126*724ba675SRob Herring clock-names = "bus"; 127*724ba675SRob Herring operating-points-v2 = <&bus_leftbus_opp_table>; 128*724ba675SRob Herring status = "disabled"; 129*724ba675SRob Herring }; 130*724ba675SRob Herring 131*724ba675SRob Herring bus_mcuisp: bus-mcuisp { 132*724ba675SRob Herring compatible = "samsung,exynos-bus"; 133*724ba675SRob Herring clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; 134*724ba675SRob Herring clock-names = "bus"; 135*724ba675SRob Herring operating-points-v2 = <&bus_mcuisp_opp_table>; 136*724ba675SRob Herring status = "disabled"; 137*724ba675SRob Herring 138*724ba675SRob Herring bus_mcuisp_opp_table: opp-table { 139*724ba675SRob Herring compatible = "operating-points-v2"; 140*724ba675SRob Herring 141*724ba675SRob Herring opp-50000000 { 142*724ba675SRob Herring opp-hz = /bits/ 64 <50000000>; 143*724ba675SRob Herring }; 144*724ba675SRob Herring opp-80000000 { 145*724ba675SRob Herring opp-hz = /bits/ 64 <80000000>; 146*724ba675SRob Herring }; 147*724ba675SRob Herring opp-100000000 { 148*724ba675SRob Herring opp-hz = /bits/ 64 <100000000>; 149*724ba675SRob Herring }; 150*724ba675SRob Herring opp-200000000 { 151*724ba675SRob Herring opp-hz = /bits/ 64 <200000000>; 152*724ba675SRob Herring }; 153*724ba675SRob Herring opp-400000000 { 154*724ba675SRob Herring opp-hz = /bits/ 64 <400000000>; 155*724ba675SRob Herring }; 156*724ba675SRob Herring }; 157*724ba675SRob Herring }; 158*724ba675SRob Herring 159*724ba675SRob Herring bus_mfc: bus-mfc { 160*724ba675SRob Herring compatible = "samsung,exynos-bus"; 161*724ba675SRob Herring clocks = <&cmu CLK_SCLK_MFC>; 162*724ba675SRob Herring clock-names = "bus"; 163*724ba675SRob Herring operating-points-v2 = <&bus_leftbus_opp_table>; 164*724ba675SRob Herring status = "disabled"; 165*724ba675SRob Herring }; 166*724ba675SRob Herring 167*724ba675SRob Herring bus_peril: bus-peril { 168*724ba675SRob Herring compatible = "samsung,exynos-bus"; 169*724ba675SRob Herring clocks = <&cmu CLK_DIV_ACLK_100>; 170*724ba675SRob Herring clock-names = "bus"; 171*724ba675SRob Herring operating-points-v2 = <&bus_peril_opp_table>; 172*724ba675SRob Herring status = "disabled"; 173*724ba675SRob Herring 174*724ba675SRob Herring bus_peril_opp_table: opp-table { 175*724ba675SRob Herring compatible = "operating-points-v2"; 176*724ba675SRob Herring 177*724ba675SRob Herring opp-50000000 { 178*724ba675SRob Herring opp-hz = /bits/ 64 <50000000>; 179*724ba675SRob Herring }; 180*724ba675SRob Herring opp-80000000 { 181*724ba675SRob Herring opp-hz = /bits/ 64 <80000000>; 182*724ba675SRob Herring }; 183*724ba675SRob Herring opp-100000000 { 184*724ba675SRob Herring opp-hz = /bits/ 64 <100000000>; 185*724ba675SRob Herring }; 186*724ba675SRob Herring }; 187*724ba675SRob Herring }; 188*724ba675SRob Herring 189*724ba675SRob Herring bus_rightbus: bus-rightbus { 190*724ba675SRob Herring compatible = "samsung,exynos-bus"; 191*724ba675SRob Herring clocks = <&cmu CLK_DIV_GDR>; 192*724ba675SRob Herring clock-names = "bus"; 193*724ba675SRob Herring operating-points-v2 = <&bus_leftbus_opp_table>; 194*724ba675SRob Herring status = "disabled"; 195*724ba675SRob Herring }; 196*724ba675SRob Herring 197*724ba675SRob Herring cpus { 198*724ba675SRob Herring #address-cells = <1>; 199*724ba675SRob Herring #size-cells = <0>; 200*724ba675SRob Herring 201*724ba675SRob Herring cpu-map { 202*724ba675SRob Herring cluster0 { 203*724ba675SRob Herring core0 { 204*724ba675SRob Herring cpu = <&cpu0>; 205*724ba675SRob Herring }; 206*724ba675SRob Herring core1 { 207*724ba675SRob Herring cpu = <&cpu1>; 208*724ba675SRob Herring }; 209*724ba675SRob Herring }; 210*724ba675SRob Herring }; 211*724ba675SRob Herring 212*724ba675SRob Herring cpu0: cpu@0 { 213*724ba675SRob Herring device_type = "cpu"; 214*724ba675SRob Herring compatible = "arm,cortex-a7"; 215*724ba675SRob Herring reg = <0>; 216*724ba675SRob Herring clock-frequency = <1000000000>; 217*724ba675SRob Herring clocks = <&cmu CLK_ARM_CLK>; 218*724ba675SRob Herring clock-names = "cpu"; 219*724ba675SRob Herring #cooling-cells = <2>; 220*724ba675SRob Herring 221*724ba675SRob Herring operating-points = < 222*724ba675SRob Herring 1000000 1150000 223*724ba675SRob Herring 900000 1112500 224*724ba675SRob Herring 800000 1075000 225*724ba675SRob Herring 700000 1037500 226*724ba675SRob Herring 600000 1000000 227*724ba675SRob Herring 500000 962500 228*724ba675SRob Herring 400000 925000 229*724ba675SRob Herring 300000 887500 230*724ba675SRob Herring 200000 850000 231*724ba675SRob Herring 100000 850000 232*724ba675SRob Herring >; 233*724ba675SRob Herring }; 234*724ba675SRob Herring 235*724ba675SRob Herring cpu1: cpu@1 { 236*724ba675SRob Herring device_type = "cpu"; 237*724ba675SRob Herring compatible = "arm,cortex-a7"; 238*724ba675SRob Herring reg = <1>; 239*724ba675SRob Herring clock-frequency = <1000000000>; 240*724ba675SRob Herring clocks = <&cmu CLK_ARM_CLK>; 241*724ba675SRob Herring clock-names = "cpu"; 242*724ba675SRob Herring #cooling-cells = <2>; 243*724ba675SRob Herring 244*724ba675SRob Herring operating-points = < 245*724ba675SRob Herring 1000000 1150000 246*724ba675SRob Herring 900000 1112500 247*724ba675SRob Herring 800000 1075000 248*724ba675SRob Herring 700000 1037500 249*724ba675SRob Herring 600000 1000000 250*724ba675SRob Herring 500000 962500 251*724ba675SRob Herring 400000 925000 252*724ba675SRob Herring 300000 887500 253*724ba675SRob Herring 200000 850000 254*724ba675SRob Herring 100000 850000 255*724ba675SRob Herring >; 256*724ba675SRob Herring }; 257*724ba675SRob Herring }; 258*724ba675SRob Herring 259*724ba675SRob Herring xusbxti: clock-0 { 260*724ba675SRob Herring compatible = "fixed-clock"; 261*724ba675SRob Herring clock-frequency = <0>; 262*724ba675SRob Herring #clock-cells = <0>; 263*724ba675SRob Herring clock-output-names = "xusbxti"; 264*724ba675SRob Herring }; 265*724ba675SRob Herring 266*724ba675SRob Herring xxti: clock-1 { 267*724ba675SRob Herring compatible = "fixed-clock"; 268*724ba675SRob Herring clock-frequency = <0>; 269*724ba675SRob Herring #clock-cells = <0>; 270*724ba675SRob Herring clock-output-names = "xxti"; 271*724ba675SRob Herring }; 272*724ba675SRob Herring 273*724ba675SRob Herring xtcxo: clock-2 { 274*724ba675SRob Herring compatible = "fixed-clock"; 275*724ba675SRob Herring clock-frequency = <0>; 276*724ba675SRob Herring #clock-cells = <0>; 277*724ba675SRob Herring clock-output-names = "xtcxo"; 278*724ba675SRob Herring }; 279*724ba675SRob Herring 280*724ba675SRob Herring bus_leftbus_opp_table: opp-table-0 { 281*724ba675SRob Herring compatible = "operating-points-v2"; 282*724ba675SRob Herring 283*724ba675SRob Herring opp-50000000 { 284*724ba675SRob Herring opp-hz = /bits/ 64 <50000000>; 285*724ba675SRob Herring opp-microvolt = <900000>; 286*724ba675SRob Herring }; 287*724ba675SRob Herring opp-80000000 { 288*724ba675SRob Herring opp-hz = /bits/ 64 <80000000>; 289*724ba675SRob Herring opp-microvolt = <900000>; 290*724ba675SRob Herring }; 291*724ba675SRob Herring opp-100000000 { 292*724ba675SRob Herring opp-hz = /bits/ 64 <100000000>; 293*724ba675SRob Herring opp-microvolt = <1000000>; 294*724ba675SRob Herring }; 295*724ba675SRob Herring opp-134000000 { 296*724ba675SRob Herring opp-hz = /bits/ 64 <134000000>; 297*724ba675SRob Herring opp-microvolt = <1000000>; 298*724ba675SRob Herring }; 299*724ba675SRob Herring opp-200000000 { 300*724ba675SRob Herring opp-hz = /bits/ 64 <200000000>; 301*724ba675SRob Herring opp-microvolt = <1000000>; 302*724ba675SRob Herring }; 303*724ba675SRob Herring }; 304*724ba675SRob Herring 305*724ba675SRob Herring pmu { 306*724ba675SRob Herring compatible = "arm,cortex-a7-pmu"; 307*724ba675SRob Herring interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 308*724ba675SRob Herring <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 309*724ba675SRob Herring }; 310*724ba675SRob Herring 311*724ba675SRob Herring soc: soc { 312*724ba675SRob Herring compatible = "simple-bus"; 313*724ba675SRob Herring #address-cells = <1>; 314*724ba675SRob Herring #size-cells = <1>; 315*724ba675SRob Herring ranges; 316*724ba675SRob Herring 317*724ba675SRob Herring sram@2020000 { 318*724ba675SRob Herring compatible = "mmio-sram"; 319*724ba675SRob Herring reg = <0x02020000 0x40000>; 320*724ba675SRob Herring #address-cells = <1>; 321*724ba675SRob Herring #size-cells = <1>; 322*724ba675SRob Herring ranges = <0 0x02020000 0x40000>; 323*724ba675SRob Herring 324*724ba675SRob Herring smp-sram@0 { 325*724ba675SRob Herring compatible = "samsung,exynos4210-sysram"; 326*724ba675SRob Herring reg = <0x0 0x1000>; 327*724ba675SRob Herring }; 328*724ba675SRob Herring 329*724ba675SRob Herring smp-sram@3f000 { 330*724ba675SRob Herring compatible = "samsung,exynos4210-sysram-ns"; 331*724ba675SRob Herring reg = <0x3f000 0x1000>; 332*724ba675SRob Herring }; 333*724ba675SRob Herring }; 334*724ba675SRob Herring 335*724ba675SRob Herring chipid@10000000 { 336*724ba675SRob Herring compatible = "samsung,exynos4210-chipid"; 337*724ba675SRob Herring reg = <0x10000000 0x100>; 338*724ba675SRob Herring }; 339*724ba675SRob Herring 340*724ba675SRob Herring sys_reg: syscon@10010000 { 341*724ba675SRob Herring compatible = "samsung,exynos3-sysreg", "syscon"; 342*724ba675SRob Herring reg = <0x10010000 0x400>; 343*724ba675SRob Herring }; 344*724ba675SRob Herring 345*724ba675SRob Herring pmu_system_controller: system-controller@10020000 { 346*724ba675SRob Herring compatible = "samsung,exynos3250-pmu", "simple-mfd", "syscon"; 347*724ba675SRob Herring reg = <0x10020000 0x4000>; 348*724ba675SRob Herring interrupt-controller; 349*724ba675SRob Herring #interrupt-cells = <3>; 350*724ba675SRob Herring interrupt-parent = <&gic>; 351*724ba675SRob Herring clock-names = "clkout8"; 352*724ba675SRob Herring clocks = <&cmu CLK_FIN_PLL>; 353*724ba675SRob Herring #clock-cells = <1>; 354*724ba675SRob Herring 355*724ba675SRob Herring mipi_phy: mipi-phy { 356*724ba675SRob Herring compatible = "samsung,s5pv210-mipi-video-phy"; 357*724ba675SRob Herring #phy-cells = <1>; 358*724ba675SRob Herring }; 359*724ba675SRob Herring }; 360*724ba675SRob Herring 361*724ba675SRob Herring pd_cam: power-domain@10023c00 { 362*724ba675SRob Herring compatible = "samsung,exynos4210-pd"; 363*724ba675SRob Herring reg = <0x10023c00 0x20>; 364*724ba675SRob Herring #power-domain-cells = <0>; 365*724ba675SRob Herring label = "CAM"; 366*724ba675SRob Herring }; 367*724ba675SRob Herring 368*724ba675SRob Herring pd_mfc: power-domain@10023c40 { 369*724ba675SRob Herring compatible = "samsung,exynos4210-pd"; 370*724ba675SRob Herring reg = <0x10023c40 0x20>; 371*724ba675SRob Herring #power-domain-cells = <0>; 372*724ba675SRob Herring label = "MFC"; 373*724ba675SRob Herring }; 374*724ba675SRob Herring 375*724ba675SRob Herring pd_g3d: power-domain@10023c60 { 376*724ba675SRob Herring compatible = "samsung,exynos4210-pd"; 377*724ba675SRob Herring reg = <0x10023c60 0x20>; 378*724ba675SRob Herring #power-domain-cells = <0>; 379*724ba675SRob Herring label = "G3D"; 380*724ba675SRob Herring }; 381*724ba675SRob Herring 382*724ba675SRob Herring pd_lcd0: power-domain@10023c80 { 383*724ba675SRob Herring compatible = "samsung,exynos4210-pd"; 384*724ba675SRob Herring reg = <0x10023c80 0x20>; 385*724ba675SRob Herring #power-domain-cells = <0>; 386*724ba675SRob Herring label = "LCD0"; 387*724ba675SRob Herring }; 388*724ba675SRob Herring 389*724ba675SRob Herring pd_isp: power-domain@10023ca0 { 390*724ba675SRob Herring compatible = "samsung,exynos4210-pd"; 391*724ba675SRob Herring reg = <0x10023ca0 0x20>; 392*724ba675SRob Herring #power-domain-cells = <0>; 393*724ba675SRob Herring label = "ISP"; 394*724ba675SRob Herring }; 395*724ba675SRob Herring 396*724ba675SRob Herring cmu: clock-controller@10030000 { 397*724ba675SRob Herring compatible = "samsung,exynos3250-cmu"; 398*724ba675SRob Herring reg = <0x10030000 0x20000>; 399*724ba675SRob Herring #clock-cells = <1>; 400*724ba675SRob Herring assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>, 401*724ba675SRob Herring <&cmu CLK_MOUT_ACLK_266_SUB>; 402*724ba675SRob Herring assigned-clock-parents = <&cmu CLK_FIN_PLL>, 403*724ba675SRob Herring <&cmu CLK_FIN_PLL>; 404*724ba675SRob Herring }; 405*724ba675SRob Herring 406*724ba675SRob Herring cmu_dmc: clock-controller@105c0000 { 407*724ba675SRob Herring compatible = "samsung,exynos3250-cmu-dmc"; 408*724ba675SRob Herring reg = <0x105c0000 0x2000>; 409*724ba675SRob Herring #clock-cells = <1>; 410*724ba675SRob Herring }; 411*724ba675SRob Herring 412*724ba675SRob Herring rtc: rtc@10070000 { 413*724ba675SRob Herring compatible = "samsung,s3c6410-rtc"; 414*724ba675SRob Herring reg = <0x10070000 0x100>; 415*724ba675SRob Herring interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 416*724ba675SRob Herring <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 417*724ba675SRob Herring interrupt-parent = <&pmu_system_controller>; 418*724ba675SRob Herring status = "disabled"; 419*724ba675SRob Herring }; 420*724ba675SRob Herring 421*724ba675SRob Herring tmu: tmu@100c0000 { 422*724ba675SRob Herring compatible = "samsung,exynos3250-tmu"; 423*724ba675SRob Herring reg = <0x100c0000 0x100>; 424*724ba675SRob Herring interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 425*724ba675SRob Herring clocks = <&cmu CLK_TMU_APBIF>; 426*724ba675SRob Herring clock-names = "tmu_apbif"; 427*724ba675SRob Herring #thermal-sensor-cells = <0>; 428*724ba675SRob Herring status = "disabled"; 429*724ba675SRob Herring }; 430*724ba675SRob Herring 431*724ba675SRob Herring gic: interrupt-controller@10481000 { 432*724ba675SRob Herring compatible = "arm,cortex-a15-gic"; 433*724ba675SRob Herring #interrupt-cells = <3>; 434*724ba675SRob Herring interrupt-controller; 435*724ba675SRob Herring reg = <0x10481000 0x1000>, 436*724ba675SRob Herring <0x10482000 0x2000>, 437*724ba675SRob Herring <0x10484000 0x2000>, 438*724ba675SRob Herring <0x10486000 0x2000>; 439*724ba675SRob Herring interrupts = <GIC_PPI 9 440*724ba675SRob Herring (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 441*724ba675SRob Herring }; 442*724ba675SRob Herring 443*724ba675SRob Herring timer@10050000 { 444*724ba675SRob Herring compatible = "samsung,exynos3250-mct", 445*724ba675SRob Herring "samsung,exynos4210-mct"; 446*724ba675SRob Herring reg = <0x10050000 0x800>; 447*724ba675SRob Herring interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 448*724ba675SRob Herring <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 449*724ba675SRob Herring <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 450*724ba675SRob Herring <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 451*724ba675SRob Herring <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 452*724ba675SRob Herring <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 453*724ba675SRob Herring <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, 454*724ba675SRob Herring <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 455*724ba675SRob Herring clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; 456*724ba675SRob Herring clock-names = "fin_pll", "mct"; 457*724ba675SRob Herring }; 458*724ba675SRob Herring 459*724ba675SRob Herring pinctrl_1: pinctrl@11000000 { 460*724ba675SRob Herring compatible = "samsung,exynos3250-pinctrl"; 461*724ba675SRob Herring reg = <0x11000000 0x1000>; 462*724ba675SRob Herring interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 463*724ba675SRob Herring 464*724ba675SRob Herring wakeup-interrupt-controller { 465*724ba675SRob Herring compatible = "samsung,exynos4210-wakeup-eint"; 466*724ba675SRob Herring interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 467*724ba675SRob Herring }; 468*724ba675SRob Herring }; 469*724ba675SRob Herring 470*724ba675SRob Herring pinctrl_0: pinctrl@11400000 { 471*724ba675SRob Herring compatible = "samsung,exynos3250-pinctrl"; 472*724ba675SRob Herring reg = <0x11400000 0x1000>; 473*724ba675SRob Herring interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 474*724ba675SRob Herring }; 475*724ba675SRob Herring 476*724ba675SRob Herring jpeg: codec@11830000 { 477*724ba675SRob Herring compatible = "samsung,exynos3250-jpeg"; 478*724ba675SRob Herring reg = <0x11830000 0x1000>; 479*724ba675SRob Herring interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 480*724ba675SRob Herring clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>; 481*724ba675SRob Herring clock-names = "jpeg", "sclk"; 482*724ba675SRob Herring power-domains = <&pd_cam>; 483*724ba675SRob Herring assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>; 484*724ba675SRob Herring assigned-clock-rates = <0>, <150000000>; 485*724ba675SRob Herring assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>; 486*724ba675SRob Herring iommus = <&sysmmu_jpeg>; 487*724ba675SRob Herring status = "disabled"; 488*724ba675SRob Herring }; 489*724ba675SRob Herring 490*724ba675SRob Herring sysmmu_jpeg: sysmmu@11a60000 { 491*724ba675SRob Herring compatible = "samsung,exynos-sysmmu"; 492*724ba675SRob Herring reg = <0x11a60000 0x1000>; 493*724ba675SRob Herring interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 494*724ba675SRob Herring clock-names = "sysmmu", "master"; 495*724ba675SRob Herring clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>; 496*724ba675SRob Herring power-domains = <&pd_cam>; 497*724ba675SRob Herring #iommu-cells = <0>; 498*724ba675SRob Herring }; 499*724ba675SRob Herring 500*724ba675SRob Herring fimd: fimd@11c00000 { 501*724ba675SRob Herring compatible = "samsung,exynos3250-fimd"; 502*724ba675SRob Herring reg = <0x11c00000 0x30000>; 503*724ba675SRob Herring interrupt-names = "fifo", "vsync", "lcd_sys"; 504*724ba675SRob Herring interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 505*724ba675SRob Herring <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 506*724ba675SRob Herring <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 507*724ba675SRob Herring clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; 508*724ba675SRob Herring clock-names = "sclk_fimd", "fimd"; 509*724ba675SRob Herring power-domains = <&pd_lcd0>; 510*724ba675SRob Herring iommus = <&sysmmu_fimd0>; 511*724ba675SRob Herring samsung,sysreg = <&sys_reg>; 512*724ba675SRob Herring status = "disabled"; 513*724ba675SRob Herring }; 514*724ba675SRob Herring 515*724ba675SRob Herring dsi_0: dsi@11c80000 { 516*724ba675SRob Herring compatible = "samsung,exynos3250-mipi-dsi"; 517*724ba675SRob Herring reg = <0x11c80000 0x10000>; 518*724ba675SRob Herring interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 519*724ba675SRob Herring samsung,phy-type = <0>; 520*724ba675SRob Herring power-domains = <&pd_lcd0>; 521*724ba675SRob Herring phys = <&mipi_phy 1>; 522*724ba675SRob Herring phy-names = "dsim"; 523*724ba675SRob Herring clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; 524*724ba675SRob Herring clock-names = "bus_clk", "pll_clk"; 525*724ba675SRob Herring #address-cells = <1>; 526*724ba675SRob Herring #size-cells = <0>; 527*724ba675SRob Herring status = "disabled"; 528*724ba675SRob Herring }; 529*724ba675SRob Herring 530*724ba675SRob Herring sysmmu_fimd0: sysmmu@11e20000 { 531*724ba675SRob Herring compatible = "samsung,exynos-sysmmu"; 532*724ba675SRob Herring reg = <0x11e20000 0x1000>; 533*724ba675SRob Herring interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 534*724ba675SRob Herring clock-names = "sysmmu", "master"; 535*724ba675SRob Herring clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; 536*724ba675SRob Herring power-domains = <&pd_lcd0>; 537*724ba675SRob Herring #iommu-cells = <0>; 538*724ba675SRob Herring }; 539*724ba675SRob Herring 540*724ba675SRob Herring hsotg: usb@12480000 { 541*724ba675SRob Herring compatible = "samsung,s3c6400-hsotg"; 542*724ba675SRob Herring reg = <0x12480000 0x20000>; 543*724ba675SRob Herring interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 544*724ba675SRob Herring clocks = <&cmu CLK_USBOTG>; 545*724ba675SRob Herring clock-names = "otg"; 546*724ba675SRob Herring phys = <&exynos_usbphy 0>; 547*724ba675SRob Herring phy-names = "usb2-phy"; 548*724ba675SRob Herring status = "disabled"; 549*724ba675SRob Herring }; 550*724ba675SRob Herring 551*724ba675SRob Herring mshc_0: mmc@12510000 { 552*724ba675SRob Herring compatible = "samsung,exynos5420-dw-mshc"; 553*724ba675SRob Herring reg = <0x12510000 0x1000>; 554*724ba675SRob Herring interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 555*724ba675SRob Herring clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; 556*724ba675SRob Herring clock-names = "biu", "ciu"; 557*724ba675SRob Herring fifo-depth = <0x80>; 558*724ba675SRob Herring #address-cells = <1>; 559*724ba675SRob Herring #size-cells = <0>; 560*724ba675SRob Herring status = "disabled"; 561*724ba675SRob Herring }; 562*724ba675SRob Herring 563*724ba675SRob Herring mshc_1: mmc@12520000 { 564*724ba675SRob Herring compatible = "samsung,exynos5420-dw-mshc"; 565*724ba675SRob Herring reg = <0x12520000 0x1000>; 566*724ba675SRob Herring interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 567*724ba675SRob Herring clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; 568*724ba675SRob Herring clock-names = "biu", "ciu"; 569*724ba675SRob Herring fifo-depth = <0x80>; 570*724ba675SRob Herring #address-cells = <1>; 571*724ba675SRob Herring #size-cells = <0>; 572*724ba675SRob Herring status = "disabled"; 573*724ba675SRob Herring }; 574*724ba675SRob Herring 575*724ba675SRob Herring mshc_2: mmc@12530000 { 576*724ba675SRob Herring compatible = "samsung,exynos5250-dw-mshc"; 577*724ba675SRob Herring reg = <0x12530000 0x1000>; 578*724ba675SRob Herring interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 579*724ba675SRob Herring clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; 580*724ba675SRob Herring clock-names = "biu", "ciu"; 581*724ba675SRob Herring fifo-depth = <0x80>; 582*724ba675SRob Herring #address-cells = <1>; 583*724ba675SRob Herring #size-cells = <0>; 584*724ba675SRob Herring status = "disabled"; 585*724ba675SRob Herring }; 586*724ba675SRob Herring 587*724ba675SRob Herring exynos_usbphy: usb-phy@125b0000 { 588*724ba675SRob Herring compatible = "samsung,exynos3250-usb2-phy"; 589*724ba675SRob Herring reg = <0x125b0000 0x100>; 590*724ba675SRob Herring samsung,pmureg-phandle = <&pmu_system_controller>; 591*724ba675SRob Herring clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>; 592*724ba675SRob Herring clock-names = "phy", "ref"; 593*724ba675SRob Herring #phy-cells = <1>; 594*724ba675SRob Herring status = "disabled"; 595*724ba675SRob Herring }; 596*724ba675SRob Herring 597*724ba675SRob Herring pdma0: dma-controller@12680000 { 598*724ba675SRob Herring compatible = "arm,pl330", "arm,primecell"; 599*724ba675SRob Herring reg = <0x12680000 0x1000>; 600*724ba675SRob Herring interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 601*724ba675SRob Herring clocks = <&cmu CLK_PDMA0>; 602*724ba675SRob Herring clock-names = "apb_pclk"; 603*724ba675SRob Herring #dma-cells = <1>; 604*724ba675SRob Herring }; 605*724ba675SRob Herring 606*724ba675SRob Herring pdma1: dma-controller@12690000 { 607*724ba675SRob Herring compatible = "arm,pl330", "arm,primecell"; 608*724ba675SRob Herring reg = <0x12690000 0x1000>; 609*724ba675SRob Herring interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 610*724ba675SRob Herring clocks = <&cmu CLK_PDMA1>; 611*724ba675SRob Herring clock-names = "apb_pclk"; 612*724ba675SRob Herring #dma-cells = <1>; 613*724ba675SRob Herring }; 614*724ba675SRob Herring 615*724ba675SRob Herring adc: adc@126c0000 { 616*724ba675SRob Herring compatible = "samsung,exynos3250-adc"; 617*724ba675SRob Herring reg = <0x126c0000 0x100>; 618*724ba675SRob Herring interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 619*724ba675SRob Herring clock-names = "adc", "sclk"; 620*724ba675SRob Herring clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; 621*724ba675SRob Herring #io-channel-cells = <1>; 622*724ba675SRob Herring samsung,syscon-phandle = <&pmu_system_controller>; 623*724ba675SRob Herring status = "disabled"; 624*724ba675SRob Herring }; 625*724ba675SRob Herring 626*724ba675SRob Herring gpu: gpu@13000000 { 627*724ba675SRob Herring compatible = "samsung,exynos4210-mali", "arm,mali-400"; 628*724ba675SRob Herring reg = <0x13000000 0x10000>; 629*724ba675SRob Herring interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 630*724ba675SRob Herring <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 631*724ba675SRob Herring <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 632*724ba675SRob Herring <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 633*724ba675SRob Herring <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 634*724ba675SRob Herring <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 635*724ba675SRob Herring <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 636*724ba675SRob Herring <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 637*724ba675SRob Herring <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 638*724ba675SRob Herring <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 639*724ba675SRob Herring <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 640*724ba675SRob Herring interrupt-names = "gp", 641*724ba675SRob Herring "gpmmu", 642*724ba675SRob Herring "pp0", 643*724ba675SRob Herring "ppmmu0", 644*724ba675SRob Herring "pp1", 645*724ba675SRob Herring "ppmmu1", 646*724ba675SRob Herring "pp2", 647*724ba675SRob Herring "ppmmu2", 648*724ba675SRob Herring "pp3", 649*724ba675SRob Herring "ppmmu3", 650*724ba675SRob Herring "pmu"; 651*724ba675SRob Herring clocks = <&cmu CLK_G3D>, 652*724ba675SRob Herring <&cmu CLK_SCLK_G3D>; 653*724ba675SRob Herring clock-names = "bus", "core"; 654*724ba675SRob Herring power-domains = <&pd_g3d>; 655*724ba675SRob Herring status = "disabled"; 656*724ba675SRob Herring /* TODO: operating points for DVFS, assigned clock as 134 MHz */ 657*724ba675SRob Herring }; 658*724ba675SRob Herring 659*724ba675SRob Herring mfc: codec@13400000 { 660*724ba675SRob Herring compatible = "samsung,exynos3250-mfc", "samsung,mfc-v7"; 661*724ba675SRob Herring reg = <0x13400000 0x10000>; 662*724ba675SRob Herring interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 663*724ba675SRob Herring clock-names = "mfc", "sclk_mfc"; 664*724ba675SRob Herring clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; 665*724ba675SRob Herring power-domains = <&pd_mfc>; 666*724ba675SRob Herring iommus = <&sysmmu_mfc>; 667*724ba675SRob Herring }; 668*724ba675SRob Herring 669*724ba675SRob Herring sysmmu_mfc: sysmmu@13620000 { 670*724ba675SRob Herring compatible = "samsung,exynos-sysmmu"; 671*724ba675SRob Herring reg = <0x13620000 0x1000>; 672*724ba675SRob Herring interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 673*724ba675SRob Herring clock-names = "sysmmu", "master"; 674*724ba675SRob Herring clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>; 675*724ba675SRob Herring power-domains = <&pd_mfc>; 676*724ba675SRob Herring #iommu-cells = <0>; 677*724ba675SRob Herring }; 678*724ba675SRob Herring 679*724ba675SRob Herring serial_0: serial@13800000 { 680*724ba675SRob Herring compatible = "samsung,exynos4210-uart"; 681*724ba675SRob Herring reg = <0x13800000 0x100>; 682*724ba675SRob Herring interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 683*724ba675SRob Herring clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; 684*724ba675SRob Herring clock-names = "uart", "clk_uart_baud0"; 685*724ba675SRob Herring pinctrl-names = "default"; 686*724ba675SRob Herring pinctrl-0 = <&uart0_data &uart0_fctl>; 687*724ba675SRob Herring status = "disabled"; 688*724ba675SRob Herring }; 689*724ba675SRob Herring 690*724ba675SRob Herring serial_1: serial@13810000 { 691*724ba675SRob Herring compatible = "samsung,exynos4210-uart"; 692*724ba675SRob Herring reg = <0x13810000 0x100>; 693*724ba675SRob Herring interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 694*724ba675SRob Herring clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; 695*724ba675SRob Herring clock-names = "uart", "clk_uart_baud0"; 696*724ba675SRob Herring pinctrl-names = "default"; 697*724ba675SRob Herring pinctrl-0 = <&uart1_data>; 698*724ba675SRob Herring status = "disabled"; 699*724ba675SRob Herring }; 700*724ba675SRob Herring 701*724ba675SRob Herring serial_2: serial@13820000 { 702*724ba675SRob Herring compatible = "samsung,exynos4210-uart"; 703*724ba675SRob Herring reg = <0x13820000 0x100>; 704*724ba675SRob Herring interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 705*724ba675SRob Herring clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; 706*724ba675SRob Herring clock-names = "uart", "clk_uart_baud0"; 707*724ba675SRob Herring pinctrl-names = "default"; 708*724ba675SRob Herring pinctrl-0 = <&uart2_data>; 709*724ba675SRob Herring status = "disabled"; 710*724ba675SRob Herring }; 711*724ba675SRob Herring 712*724ba675SRob Herring i2c_0: i2c@13860000 { 713*724ba675SRob Herring #address-cells = <1>; 714*724ba675SRob Herring #size-cells = <0>; 715*724ba675SRob Herring compatible = "samsung,s3c2440-i2c"; 716*724ba675SRob Herring reg = <0x13860000 0x100>; 717*724ba675SRob Herring interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 718*724ba675SRob Herring clocks = <&cmu CLK_I2C0>; 719*724ba675SRob Herring clock-names = "i2c"; 720*724ba675SRob Herring pinctrl-names = "default"; 721*724ba675SRob Herring pinctrl-0 = <&i2c0_bus>; 722*724ba675SRob Herring status = "disabled"; 723*724ba675SRob Herring }; 724*724ba675SRob Herring 725*724ba675SRob Herring i2c_1: i2c@13870000 { 726*724ba675SRob Herring #address-cells = <1>; 727*724ba675SRob Herring #size-cells = <0>; 728*724ba675SRob Herring compatible = "samsung,s3c2440-i2c"; 729*724ba675SRob Herring reg = <0x13870000 0x100>; 730*724ba675SRob Herring interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 731*724ba675SRob Herring clocks = <&cmu CLK_I2C1>; 732*724ba675SRob Herring clock-names = "i2c"; 733*724ba675SRob Herring pinctrl-names = "default"; 734*724ba675SRob Herring pinctrl-0 = <&i2c1_bus>; 735*724ba675SRob Herring status = "disabled"; 736*724ba675SRob Herring }; 737*724ba675SRob Herring 738*724ba675SRob Herring i2c_2: i2c@13880000 { 739*724ba675SRob Herring #address-cells = <1>; 740*724ba675SRob Herring #size-cells = <0>; 741*724ba675SRob Herring compatible = "samsung,s3c2440-i2c"; 742*724ba675SRob Herring reg = <0x13880000 0x100>; 743*724ba675SRob Herring interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 744*724ba675SRob Herring clocks = <&cmu CLK_I2C2>; 745*724ba675SRob Herring clock-names = "i2c"; 746*724ba675SRob Herring pinctrl-names = "default"; 747*724ba675SRob Herring pinctrl-0 = <&i2c2_bus>; 748*724ba675SRob Herring status = "disabled"; 749*724ba675SRob Herring }; 750*724ba675SRob Herring 751*724ba675SRob Herring i2c_3: i2c@13890000 { 752*724ba675SRob Herring #address-cells = <1>; 753*724ba675SRob Herring #size-cells = <0>; 754*724ba675SRob Herring compatible = "samsung,s3c2440-i2c"; 755*724ba675SRob Herring reg = <0x13890000 0x100>; 756*724ba675SRob Herring interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 757*724ba675SRob Herring clocks = <&cmu CLK_I2C3>; 758*724ba675SRob Herring clock-names = "i2c"; 759*724ba675SRob Herring pinctrl-names = "default"; 760*724ba675SRob Herring pinctrl-0 = <&i2c3_bus>; 761*724ba675SRob Herring status = "disabled"; 762*724ba675SRob Herring }; 763*724ba675SRob Herring 764*724ba675SRob Herring i2c_4: i2c@138a0000 { 765*724ba675SRob Herring #address-cells = <1>; 766*724ba675SRob Herring #size-cells = <0>; 767*724ba675SRob Herring compatible = "samsung,s3c2440-i2c"; 768*724ba675SRob Herring reg = <0x138a0000 0x100>; 769*724ba675SRob Herring interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 770*724ba675SRob Herring clocks = <&cmu CLK_I2C4>; 771*724ba675SRob Herring clock-names = "i2c"; 772*724ba675SRob Herring pinctrl-names = "default"; 773*724ba675SRob Herring pinctrl-0 = <&i2c4_bus>; 774*724ba675SRob Herring status = "disabled"; 775*724ba675SRob Herring }; 776*724ba675SRob Herring 777*724ba675SRob Herring i2c_5: i2c@138b0000 { 778*724ba675SRob Herring #address-cells = <1>; 779*724ba675SRob Herring #size-cells = <0>; 780*724ba675SRob Herring compatible = "samsung,s3c2440-i2c"; 781*724ba675SRob Herring reg = <0x138b0000 0x100>; 782*724ba675SRob Herring interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 783*724ba675SRob Herring clocks = <&cmu CLK_I2C5>; 784*724ba675SRob Herring clock-names = "i2c"; 785*724ba675SRob Herring pinctrl-names = "default"; 786*724ba675SRob Herring pinctrl-0 = <&i2c5_bus>; 787*724ba675SRob Herring status = "disabled"; 788*724ba675SRob Herring }; 789*724ba675SRob Herring 790*724ba675SRob Herring i2c_6: i2c@138c0000 { 791*724ba675SRob Herring #address-cells = <1>; 792*724ba675SRob Herring #size-cells = <0>; 793*724ba675SRob Herring compatible = "samsung,s3c2440-i2c"; 794*724ba675SRob Herring reg = <0x138c0000 0x100>; 795*724ba675SRob Herring interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 796*724ba675SRob Herring clocks = <&cmu CLK_I2C6>; 797*724ba675SRob Herring clock-names = "i2c"; 798*724ba675SRob Herring pinctrl-names = "default"; 799*724ba675SRob Herring pinctrl-0 = <&i2c6_bus>; 800*724ba675SRob Herring status = "disabled"; 801*724ba675SRob Herring }; 802*724ba675SRob Herring 803*724ba675SRob Herring i2c_7: i2c@138d0000 { 804*724ba675SRob Herring #address-cells = <1>; 805*724ba675SRob Herring #size-cells = <0>; 806*724ba675SRob Herring compatible = "samsung,s3c2440-i2c"; 807*724ba675SRob Herring reg = <0x138d0000 0x100>; 808*724ba675SRob Herring interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 809*724ba675SRob Herring clocks = <&cmu CLK_I2C7>; 810*724ba675SRob Herring clock-names = "i2c"; 811*724ba675SRob Herring pinctrl-names = "default"; 812*724ba675SRob Herring pinctrl-0 = <&i2c7_bus>; 813*724ba675SRob Herring status = "disabled"; 814*724ba675SRob Herring }; 815*724ba675SRob Herring 816*724ba675SRob Herring spi_0: spi@13920000 { 817*724ba675SRob Herring compatible = "samsung,exynos4210-spi"; 818*724ba675SRob Herring reg = <0x13920000 0x100>; 819*724ba675SRob Herring interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 820*724ba675SRob Herring dmas = <&pdma0 7>, <&pdma0 6>; 821*724ba675SRob Herring dma-names = "tx", "rx"; 822*724ba675SRob Herring #address-cells = <1>; 823*724ba675SRob Herring #size-cells = <0>; 824*724ba675SRob Herring clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; 825*724ba675SRob Herring clock-names = "spi", "spi_busclk0"; 826*724ba675SRob Herring samsung,spi-src-clk = <0>; 827*724ba675SRob Herring pinctrl-names = "default"; 828*724ba675SRob Herring pinctrl-0 = <&spi0_bus>; 829*724ba675SRob Herring status = "disabled"; 830*724ba675SRob Herring }; 831*724ba675SRob Herring 832*724ba675SRob Herring spi_1: spi@13930000 { 833*724ba675SRob Herring compatible = "samsung,exynos4210-spi"; 834*724ba675SRob Herring reg = <0x13930000 0x100>; 835*724ba675SRob Herring interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 836*724ba675SRob Herring dmas = <&pdma1 7>, <&pdma1 6>; 837*724ba675SRob Herring dma-names = "tx", "rx"; 838*724ba675SRob Herring #address-cells = <1>; 839*724ba675SRob Herring #size-cells = <0>; 840*724ba675SRob Herring clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; 841*724ba675SRob Herring clock-names = "spi", "spi_busclk0"; 842*724ba675SRob Herring samsung,spi-src-clk = <0>; 843*724ba675SRob Herring pinctrl-names = "default"; 844*724ba675SRob Herring pinctrl-0 = <&spi1_bus>; 845*724ba675SRob Herring status = "disabled"; 846*724ba675SRob Herring }; 847*724ba675SRob Herring 848*724ba675SRob Herring i2s2: i2s@13970000 { 849*724ba675SRob Herring compatible = "samsung,s3c6410-i2s"; 850*724ba675SRob Herring reg = <0x13970000 0x100>; 851*724ba675SRob Herring interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 852*724ba675SRob Herring clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>; 853*724ba675SRob Herring clock-names = "iis", "i2s_opclk0"; 854*724ba675SRob Herring dmas = <&pdma0 14>, <&pdma0 13>; 855*724ba675SRob Herring dma-names = "tx", "rx"; 856*724ba675SRob Herring pinctrl-0 = <&i2s2_bus>; 857*724ba675SRob Herring pinctrl-names = "default"; 858*724ba675SRob Herring status = "disabled"; 859*724ba675SRob Herring }; 860*724ba675SRob Herring 861*724ba675SRob Herring pwm: pwm@139d0000 { 862*724ba675SRob Herring compatible = "samsung,exynos4210-pwm"; 863*724ba675SRob Herring reg = <0x139d0000 0x1000>; 864*724ba675SRob Herring interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 865*724ba675SRob Herring <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 866*724ba675SRob Herring <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 867*724ba675SRob Herring <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 868*724ba675SRob Herring <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 869*724ba675SRob Herring #pwm-cells = <3>; 870*724ba675SRob Herring status = "disabled"; 871*724ba675SRob Herring }; 872*724ba675SRob Herring 873*724ba675SRob Herring ppmu_dmc0: ppmu@106a0000 { 874*724ba675SRob Herring compatible = "samsung,exynos-ppmu"; 875*724ba675SRob Herring reg = <0x106a0000 0x2000>; 876*724ba675SRob Herring status = "disabled"; 877*724ba675SRob Herring }; 878*724ba675SRob Herring 879*724ba675SRob Herring ppmu_dmc1: ppmu@106b0000 { 880*724ba675SRob Herring compatible = "samsung,exynos-ppmu"; 881*724ba675SRob Herring reg = <0x106b0000 0x2000>; 882*724ba675SRob Herring status = "disabled"; 883*724ba675SRob Herring }; 884*724ba675SRob Herring 885*724ba675SRob Herring ppmu_cpu: ppmu@106c0000 { 886*724ba675SRob Herring compatible = "samsung,exynos-ppmu"; 887*724ba675SRob Herring reg = <0x106c0000 0x2000>; 888*724ba675SRob Herring status = "disabled"; 889*724ba675SRob Herring }; 890*724ba675SRob Herring 891*724ba675SRob Herring ppmu_rightbus: ppmu@112a0000 { 892*724ba675SRob Herring compatible = "samsung,exynos-ppmu"; 893*724ba675SRob Herring reg = <0x112a0000 0x2000>; 894*724ba675SRob Herring clocks = <&cmu CLK_PPMURIGHT>; 895*724ba675SRob Herring clock-names = "ppmu"; 896*724ba675SRob Herring status = "disabled"; 897*724ba675SRob Herring }; 898*724ba675SRob Herring 899*724ba675SRob Herring ppmu_leftbus: ppmu@116a0000 { 900*724ba675SRob Herring compatible = "samsung,exynos-ppmu"; 901*724ba675SRob Herring reg = <0x116a0000 0x2000>; 902*724ba675SRob Herring clocks = <&cmu CLK_PPMULEFT>; 903*724ba675SRob Herring clock-names = "ppmu"; 904*724ba675SRob Herring status = "disabled"; 905*724ba675SRob Herring }; 906*724ba675SRob Herring 907*724ba675SRob Herring ppmu_camif: ppmu@11ac0000 { 908*724ba675SRob Herring compatible = "samsung,exynos-ppmu"; 909*724ba675SRob Herring reg = <0x11ac0000 0x2000>; 910*724ba675SRob Herring clocks = <&cmu CLK_PPMUCAMIF>; 911*724ba675SRob Herring clock-names = "ppmu"; 912*724ba675SRob Herring status = "disabled"; 913*724ba675SRob Herring }; 914*724ba675SRob Herring 915*724ba675SRob Herring ppmu_lcd0: ppmu@11e40000 { 916*724ba675SRob Herring compatible = "samsung,exynos-ppmu"; 917*724ba675SRob Herring reg = <0x11e40000 0x2000>; 918*724ba675SRob Herring clocks = <&cmu CLK_PPMULCD0>; 919*724ba675SRob Herring clock-names = "ppmu"; 920*724ba675SRob Herring status = "disabled"; 921*724ba675SRob Herring }; 922*724ba675SRob Herring 923*724ba675SRob Herring ppmu_fsys: ppmu@12630000 { 924*724ba675SRob Herring compatible = "samsung,exynos-ppmu"; 925*724ba675SRob Herring reg = <0x12630000 0x2000>; 926*724ba675SRob Herring clocks = <&cmu CLK_PPMUFILE>; 927*724ba675SRob Herring clock-names = "ppmu"; 928*724ba675SRob Herring status = "disabled"; 929*724ba675SRob Herring }; 930*724ba675SRob Herring 931*724ba675SRob Herring ppmu_g3d: ppmu@13220000 { 932*724ba675SRob Herring compatible = "samsung,exynos-ppmu"; 933*724ba675SRob Herring reg = <0x13220000 0x2000>; 934*724ba675SRob Herring clocks = <&cmu CLK_PPMUG3D>; 935*724ba675SRob Herring clock-names = "ppmu"; 936*724ba675SRob Herring status = "disabled"; 937*724ba675SRob Herring }; 938*724ba675SRob Herring 939*724ba675SRob Herring ppmu_mfc: ppmu@13660000 { 940*724ba675SRob Herring compatible = "samsung,exynos-ppmu"; 941*724ba675SRob Herring reg = <0x13660000 0x2000>; 942*724ba675SRob Herring clocks = <&cmu CLK_PPMUMFC_L>; 943*724ba675SRob Herring clock-names = "ppmu"; 944*724ba675SRob Herring status = "disabled"; 945*724ba675SRob Herring }; 946*724ba675SRob Herring }; 947*724ba675SRob Herring}; 948*724ba675SRob Herring 949*724ba675SRob Herring#include "exynos3250-pinctrl.dtsi" 950*724ba675SRob Herring#include "exynos-syscon-restart.dtsi" 951