1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4*724ba675SRob Herring * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. 5*724ba675SRob Herring */ 6*724ba675SRob Herring 7*724ba675SRob Herring/dts-v1/; 8*724ba675SRob Herring#include "rv1126.dtsi" 9*724ba675SRob Herring#include "rv1126-edgeble-neu2.dtsi" 10*724ba675SRob Herring 11*724ba675SRob Herring/ { 12*724ba675SRob Herring model = "Edgeble Neu2 IO Board"; 13*724ba675SRob Herring compatible = "edgeble,neural-compute-module-2-io", 14*724ba675SRob Herring "edgeble,neural-compute-module-2", "rockchip,rv1126"; 15*724ba675SRob Herring 16*724ba675SRob Herring aliases { 17*724ba675SRob Herring serial2 = &uart2; 18*724ba675SRob Herring }; 19*724ba675SRob Herring 20*724ba675SRob Herring chosen { 21*724ba675SRob Herring stdout-path = "serial2:1500000n8"; 22*724ba675SRob Herring }; 23*724ba675SRob Herring}; 24*724ba675SRob Herring 25*724ba675SRob Herring&gmac { 26*724ba675SRob Herring assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, 27*724ba675SRob Herring <&cru CLK_GMAC_ETHERNET_OUT>; 28*724ba675SRob Herring assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; 29*724ba675SRob Herring assigned-clock-rates = <125000000>, <0>, <25000000>; 30*724ba675SRob Herring clock_in_out = "input"; 31*724ba675SRob Herring phy-handle = <&phy>; 32*724ba675SRob Herring phy-mode = "rgmii"; 33*724ba675SRob Herring phy-supply = <&vcc_3v3>; 34*724ba675SRob Herring pinctrl-names = "default"; 35*724ba675SRob Herring pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>; 36*724ba675SRob Herring tx_delay = <0x2a>; 37*724ba675SRob Herring rx_delay = <0x1a>; 38*724ba675SRob Herring status = "okay"; 39*724ba675SRob Herring}; 40*724ba675SRob Herring 41*724ba675SRob Herring&mdio { 42*724ba675SRob Herring phy: ethernet-phy@0 { 43*724ba675SRob Herring compatible = "ethernet-phy-id001c.c916", 44*724ba675SRob Herring "ethernet-phy-ieee802.3-c22"; 45*724ba675SRob Herring reg = <0x0>; 46*724ba675SRob Herring pinctrl-names = "default"; 47*724ba675SRob Herring pinctrl-0 = <ð_phy_rst>; 48*724ba675SRob Herring reset-assert-us = <20000>; 49*724ba675SRob Herring reset-deassert-us = <100000>; 50*724ba675SRob Herring reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; 51*724ba675SRob Herring }; 52*724ba675SRob Herring}; 53*724ba675SRob Herring 54*724ba675SRob Herring&pinctrl { 55*724ba675SRob Herring ethernet { 56*724ba675SRob Herring eth_phy_rst: eth-phy-rst { 57*724ba675SRob Herring rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; 58*724ba675SRob Herring }; 59*724ba675SRob Herring }; 60*724ba675SRob Herring}; 61*724ba675SRob Herring 62*724ba675SRob Herring&sdmmc { 63*724ba675SRob Herring bus-width = <4>; 64*724ba675SRob Herring cap-mmc-highspeed; 65*724ba675SRob Herring cap-sd-highspeed; 66*724ba675SRob Herring card-detect-delay = <200>; 67*724ba675SRob Herring pinctrl-names = "default"; 68*724ba675SRob Herring pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>; 69*724ba675SRob Herring rockchip,default-sample-phase = <90>; 70*724ba675SRob Herring sd-uhs-sdr12; 71*724ba675SRob Herring sd-uhs-sdr25; 72*724ba675SRob Herring sd-uhs-sdr104; 73*724ba675SRob Herring vqmmc-supply = <&vccio_sd>; 74*724ba675SRob Herring status = "okay"; 75*724ba675SRob Herring}; 76*724ba675SRob Herring 77*724ba675SRob Herring&uart2 { 78*724ba675SRob Herring status = "okay"; 79*724ba675SRob Herring}; 80