1724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2724ba675SRob Herring 3724ba675SRob Herring#include <dt-bindings/gpio/gpio.h> 4724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 5724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 6724ba675SRob Herring#include <dt-bindings/pinctrl/rockchip.h> 7724ba675SRob Herring#include <dt-bindings/clock/rk3288-cru.h> 8724ba675SRob Herring#include <dt-bindings/power/rk3288-power.h> 9724ba675SRob Herring#include <dt-bindings/thermal/thermal.h> 10724ba675SRob Herring#include <dt-bindings/soc/rockchip,boot-mode.h> 11724ba675SRob Herring 12724ba675SRob Herring/ { 13724ba675SRob Herring #address-cells = <2>; 14724ba675SRob Herring #size-cells = <2>; 15724ba675SRob Herring 16724ba675SRob Herring compatible = "rockchip,rk3288"; 17724ba675SRob Herring 18724ba675SRob Herring interrupt-parent = <&gic>; 19724ba675SRob Herring 20724ba675SRob Herring aliases { 21724ba675SRob Herring ethernet0 = &gmac; 22724ba675SRob Herring i2c0 = &i2c0; 23724ba675SRob Herring i2c1 = &i2c1; 24724ba675SRob Herring i2c2 = &i2c2; 25724ba675SRob Herring i2c3 = &i2c3; 26724ba675SRob Herring i2c4 = &i2c4; 27724ba675SRob Herring i2c5 = &i2c5; 28724ba675SRob Herring mshc0 = &emmc; 29724ba675SRob Herring mshc1 = &sdmmc; 30724ba675SRob Herring mshc2 = &sdio0; 31724ba675SRob Herring mshc3 = &sdio1; 32724ba675SRob Herring serial0 = &uart0; 33724ba675SRob Herring serial1 = &uart1; 34724ba675SRob Herring serial2 = &uart2; 35724ba675SRob Herring serial3 = &uart3; 36724ba675SRob Herring serial4 = &uart4; 37724ba675SRob Herring spi0 = &spi0; 38724ba675SRob Herring spi1 = &spi1; 39724ba675SRob Herring spi2 = &spi2; 40724ba675SRob Herring }; 41724ba675SRob Herring 42724ba675SRob Herring arm-pmu { 43724ba675SRob Herring compatible = "arm,cortex-a12-pmu"; 44724ba675SRob Herring interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 45724ba675SRob Herring <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 46724ba675SRob Herring <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 47724ba675SRob Herring <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 48724ba675SRob Herring interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 49724ba675SRob Herring }; 50724ba675SRob Herring 51724ba675SRob Herring cpus { 52724ba675SRob Herring #address-cells = <1>; 53724ba675SRob Herring #size-cells = <0>; 54724ba675SRob Herring enable-method = "rockchip,rk3066-smp"; 55724ba675SRob Herring rockchip,pmu = <&pmu>; 56724ba675SRob Herring 57724ba675SRob Herring cpu0: cpu@500 { 58724ba675SRob Herring device_type = "cpu"; 59724ba675SRob Herring compatible = "arm,cortex-a12"; 60724ba675SRob Herring reg = <0x500>; 61724ba675SRob Herring resets = <&cru SRST_CORE0>; 62724ba675SRob Herring operating-points-v2 = <&cpu_opp_table>; 63724ba675SRob Herring #cooling-cells = <2>; /* min followed by max */ 64724ba675SRob Herring clock-latency = <40000>; 65724ba675SRob Herring clocks = <&cru ARMCLK>; 66724ba675SRob Herring dynamic-power-coefficient = <370>; 67724ba675SRob Herring }; 68724ba675SRob Herring cpu1: cpu@501 { 69724ba675SRob Herring device_type = "cpu"; 70724ba675SRob Herring compatible = "arm,cortex-a12"; 71724ba675SRob Herring reg = <0x501>; 72724ba675SRob Herring resets = <&cru SRST_CORE1>; 73724ba675SRob Herring operating-points-v2 = <&cpu_opp_table>; 74724ba675SRob Herring #cooling-cells = <2>; /* min followed by max */ 75724ba675SRob Herring clock-latency = <40000>; 76724ba675SRob Herring clocks = <&cru ARMCLK>; 77724ba675SRob Herring dynamic-power-coefficient = <370>; 78724ba675SRob Herring }; 79724ba675SRob Herring cpu2: cpu@502 { 80724ba675SRob Herring device_type = "cpu"; 81724ba675SRob Herring compatible = "arm,cortex-a12"; 82724ba675SRob Herring reg = <0x502>; 83724ba675SRob Herring resets = <&cru SRST_CORE2>; 84724ba675SRob Herring operating-points-v2 = <&cpu_opp_table>; 85724ba675SRob Herring #cooling-cells = <2>; /* min followed by max */ 86724ba675SRob Herring clock-latency = <40000>; 87724ba675SRob Herring clocks = <&cru ARMCLK>; 88724ba675SRob Herring dynamic-power-coefficient = <370>; 89724ba675SRob Herring }; 90724ba675SRob Herring cpu3: cpu@503 { 91724ba675SRob Herring device_type = "cpu"; 92724ba675SRob Herring compatible = "arm,cortex-a12"; 93724ba675SRob Herring reg = <0x503>; 94724ba675SRob Herring resets = <&cru SRST_CORE3>; 95724ba675SRob Herring operating-points-v2 = <&cpu_opp_table>; 96724ba675SRob Herring #cooling-cells = <2>; /* min followed by max */ 97724ba675SRob Herring clock-latency = <40000>; 98724ba675SRob Herring clocks = <&cru ARMCLK>; 99724ba675SRob Herring dynamic-power-coefficient = <370>; 100724ba675SRob Herring }; 101724ba675SRob Herring }; 102724ba675SRob Herring 103724ba675SRob Herring cpu_opp_table: opp-table-0 { 104724ba675SRob Herring compatible = "operating-points-v2"; 105724ba675SRob Herring opp-shared; 106724ba675SRob Herring 107724ba675SRob Herring opp-126000000 { 108724ba675SRob Herring opp-hz = /bits/ 64 <126000000>; 109724ba675SRob Herring opp-microvolt = <900000>; 110724ba675SRob Herring }; 111724ba675SRob Herring opp-216000000 { 112724ba675SRob Herring opp-hz = /bits/ 64 <216000000>; 113724ba675SRob Herring opp-microvolt = <900000>; 114724ba675SRob Herring }; 115724ba675SRob Herring opp-312000000 { 116724ba675SRob Herring opp-hz = /bits/ 64 <312000000>; 117724ba675SRob Herring opp-microvolt = <900000>; 118724ba675SRob Herring }; 119724ba675SRob Herring opp-408000000 { 120724ba675SRob Herring opp-hz = /bits/ 64 <408000000>; 121724ba675SRob Herring opp-microvolt = <900000>; 122724ba675SRob Herring }; 123724ba675SRob Herring opp-600000000 { 124724ba675SRob Herring opp-hz = /bits/ 64 <600000000>; 125724ba675SRob Herring opp-microvolt = <900000>; 126724ba675SRob Herring }; 127724ba675SRob Herring opp-696000000 { 128724ba675SRob Herring opp-hz = /bits/ 64 <696000000>; 129724ba675SRob Herring opp-microvolt = <950000>; 130724ba675SRob Herring }; 131724ba675SRob Herring opp-816000000 { 132724ba675SRob Herring opp-hz = /bits/ 64 <816000000>; 133724ba675SRob Herring opp-microvolt = <1000000>; 134724ba675SRob Herring }; 135724ba675SRob Herring opp-1008000000 { 136724ba675SRob Herring opp-hz = /bits/ 64 <1008000000>; 137724ba675SRob Herring opp-microvolt = <1050000>; 138724ba675SRob Herring }; 139724ba675SRob Herring opp-1200000000 { 140724ba675SRob Herring opp-hz = /bits/ 64 <1200000000>; 141724ba675SRob Herring opp-microvolt = <1100000>; 142724ba675SRob Herring }; 143724ba675SRob Herring opp-1416000000 { 144724ba675SRob Herring opp-hz = /bits/ 64 <1416000000>; 145724ba675SRob Herring opp-microvolt = <1200000>; 146724ba675SRob Herring }; 147724ba675SRob Herring opp-1512000000 { 148724ba675SRob Herring opp-hz = /bits/ 64 <1512000000>; 149724ba675SRob Herring opp-microvolt = <1300000>; 150724ba675SRob Herring }; 151724ba675SRob Herring opp-1608000000 { 152724ba675SRob Herring opp-hz = /bits/ 64 <1608000000>; 153724ba675SRob Herring opp-microvolt = <1350000>; 154724ba675SRob Herring }; 155724ba675SRob Herring }; 156724ba675SRob Herring 157724ba675SRob Herring reserved-memory { 158724ba675SRob Herring #address-cells = <2>; 159724ba675SRob Herring #size-cells = <2>; 160724ba675SRob Herring ranges; 161724ba675SRob Herring 162724ba675SRob Herring /* 163724ba675SRob Herring * The rk3288 cannot use the memory area above 0xfe000000 164724ba675SRob Herring * for dma operations for some reason. While there is 165724ba675SRob Herring * probably a better solution available somewhere, we 166724ba675SRob Herring * haven't found it yet and while devices with 2GB of ram 167724ba675SRob Herring * are not affected, this issue prevents 4GB from booting. 168724ba675SRob Herring * So to make these devices at least bootable, block 169724ba675SRob Herring * this area for the time being until the real solution 170724ba675SRob Herring * is found. 171724ba675SRob Herring */ 172724ba675SRob Herring dma-unusable@fe000000 { 173724ba675SRob Herring reg = <0x0 0xfe000000 0x0 0x1000000>; 174724ba675SRob Herring }; 175724ba675SRob Herring }; 176724ba675SRob Herring 177724ba675SRob Herring xin24m: oscillator { 178724ba675SRob Herring compatible = "fixed-clock"; 179724ba675SRob Herring clock-frequency = <24000000>; 180724ba675SRob Herring clock-output-names = "xin24m"; 181724ba675SRob Herring #clock-cells = <0>; 182724ba675SRob Herring }; 183724ba675SRob Herring 184724ba675SRob Herring timer { 185724ba675SRob Herring compatible = "arm,armv7-timer"; 186724ba675SRob Herring arm,cpu-registers-not-fw-configured; 187724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 188724ba675SRob Herring <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 189724ba675SRob Herring <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 190724ba675SRob Herring <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 191724ba675SRob Herring clock-frequency = <24000000>; 192724ba675SRob Herring arm,no-tick-in-suspend; 193724ba675SRob Herring }; 194724ba675SRob Herring 195724ba675SRob Herring timer: timer@ff810000 { 196724ba675SRob Herring compatible = "rockchip,rk3288-timer"; 197724ba675SRob Herring reg = <0x0 0xff810000 0x0 0x20>; 198724ba675SRob Herring interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 199724ba675SRob Herring clocks = <&cru PCLK_TIMER>, <&xin24m>; 200724ba675SRob Herring clock-names = "pclk", "timer"; 201724ba675SRob Herring }; 202724ba675SRob Herring 203724ba675SRob Herring display-subsystem { 204724ba675SRob Herring compatible = "rockchip,display-subsystem"; 205724ba675SRob Herring ports = <&vopl_out>, <&vopb_out>; 206724ba675SRob Herring }; 207724ba675SRob Herring 208724ba675SRob Herring sdmmc: mmc@ff0c0000 { 209724ba675SRob Herring compatible = "rockchip,rk3288-dw-mshc"; 210724ba675SRob Herring max-frequency = <150000000>; 211724ba675SRob Herring clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 212724ba675SRob Herring <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 213724ba675SRob Herring clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 214724ba675SRob Herring fifo-depth = <0x100>; 215724ba675SRob Herring interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 216724ba675SRob Herring reg = <0x0 0xff0c0000 0x0 0x4000>; 217724ba675SRob Herring resets = <&cru SRST_MMC0>; 218724ba675SRob Herring reset-names = "reset"; 219724ba675SRob Herring status = "disabled"; 220724ba675SRob Herring }; 221724ba675SRob Herring 222724ba675SRob Herring sdio0: mmc@ff0d0000 { 223724ba675SRob Herring compatible = "rockchip,rk3288-dw-mshc"; 224724ba675SRob Herring max-frequency = <150000000>; 225724ba675SRob Herring clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 226724ba675SRob Herring <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 227724ba675SRob Herring clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 228724ba675SRob Herring fifo-depth = <0x100>; 229724ba675SRob Herring interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 230724ba675SRob Herring reg = <0x0 0xff0d0000 0x0 0x4000>; 231724ba675SRob Herring resets = <&cru SRST_SDIO0>; 232724ba675SRob Herring reset-names = "reset"; 233724ba675SRob Herring status = "disabled"; 234724ba675SRob Herring }; 235724ba675SRob Herring 236724ba675SRob Herring sdio1: mmc@ff0e0000 { 237724ba675SRob Herring compatible = "rockchip,rk3288-dw-mshc"; 238724ba675SRob Herring max-frequency = <150000000>; 239724ba675SRob Herring clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, 240724ba675SRob Herring <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; 241724ba675SRob Herring clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 242724ba675SRob Herring fifo-depth = <0x100>; 243724ba675SRob Herring interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 244724ba675SRob Herring reg = <0x0 0xff0e0000 0x0 0x4000>; 245724ba675SRob Herring resets = <&cru SRST_SDIO1>; 246724ba675SRob Herring reset-names = "reset"; 247724ba675SRob Herring status = "disabled"; 248724ba675SRob Herring }; 249724ba675SRob Herring 250724ba675SRob Herring emmc: mmc@ff0f0000 { 251724ba675SRob Herring compatible = "rockchip,rk3288-dw-mshc"; 252724ba675SRob Herring max-frequency = <150000000>; 253724ba675SRob Herring clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 254724ba675SRob Herring <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 255724ba675SRob Herring clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 256724ba675SRob Herring fifo-depth = <0x100>; 257724ba675SRob Herring interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 258724ba675SRob Herring reg = <0x0 0xff0f0000 0x0 0x4000>; 259724ba675SRob Herring resets = <&cru SRST_EMMC>; 260724ba675SRob Herring reset-names = "reset"; 261724ba675SRob Herring status = "disabled"; 262724ba675SRob Herring }; 263724ba675SRob Herring 264724ba675SRob Herring saradc: saradc@ff100000 { 265724ba675SRob Herring compatible = "rockchip,saradc"; 266724ba675SRob Herring reg = <0x0 0xff100000 0x0 0x100>; 267724ba675SRob Herring interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 268724ba675SRob Herring #io-channel-cells = <1>; 269724ba675SRob Herring clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 270724ba675SRob Herring clock-names = "saradc", "apb_pclk"; 271724ba675SRob Herring resets = <&cru SRST_SARADC>; 272724ba675SRob Herring reset-names = "saradc-apb"; 273724ba675SRob Herring status = "disabled"; 274724ba675SRob Herring }; 275724ba675SRob Herring 276724ba675SRob Herring spi0: spi@ff110000 { 277724ba675SRob Herring compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 278724ba675SRob Herring clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 279724ba675SRob Herring clock-names = "spiclk", "apb_pclk"; 280724ba675SRob Herring dmas = <&dmac_peri 11>, <&dmac_peri 12>; 281724ba675SRob Herring dma-names = "tx", "rx"; 282724ba675SRob Herring interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 283724ba675SRob Herring pinctrl-names = "default"; 284724ba675SRob Herring pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 285724ba675SRob Herring reg = <0x0 0xff110000 0x0 0x1000>; 286724ba675SRob Herring #address-cells = <1>; 287724ba675SRob Herring #size-cells = <0>; 288724ba675SRob Herring status = "disabled"; 289724ba675SRob Herring }; 290724ba675SRob Herring 291724ba675SRob Herring spi1: spi@ff120000 { 292724ba675SRob Herring compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 293724ba675SRob Herring clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 294724ba675SRob Herring clock-names = "spiclk", "apb_pclk"; 295724ba675SRob Herring dmas = <&dmac_peri 13>, <&dmac_peri 14>; 296724ba675SRob Herring dma-names = "tx", "rx"; 297724ba675SRob Herring interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 298724ba675SRob Herring pinctrl-names = "default"; 299724ba675SRob Herring pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 300724ba675SRob Herring reg = <0x0 0xff120000 0x0 0x1000>; 301724ba675SRob Herring #address-cells = <1>; 302724ba675SRob Herring #size-cells = <0>; 303724ba675SRob Herring status = "disabled"; 304724ba675SRob Herring }; 305724ba675SRob Herring 306724ba675SRob Herring spi2: spi@ff130000 { 307724ba675SRob Herring compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 308724ba675SRob Herring clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 309724ba675SRob Herring clock-names = "spiclk", "apb_pclk"; 310724ba675SRob Herring dmas = <&dmac_peri 15>, <&dmac_peri 16>; 311724ba675SRob Herring dma-names = "tx", "rx"; 312724ba675SRob Herring interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 313724ba675SRob Herring pinctrl-names = "default"; 314724ba675SRob Herring pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 315724ba675SRob Herring reg = <0x0 0xff130000 0x0 0x1000>; 316724ba675SRob Herring #address-cells = <1>; 317724ba675SRob Herring #size-cells = <0>; 318724ba675SRob Herring status = "disabled"; 319724ba675SRob Herring }; 320724ba675SRob Herring 321724ba675SRob Herring i2c1: i2c@ff140000 { 322724ba675SRob Herring compatible = "rockchip,rk3288-i2c"; 323724ba675SRob Herring reg = <0x0 0xff140000 0x0 0x1000>; 324724ba675SRob Herring interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 325724ba675SRob Herring #address-cells = <1>; 326724ba675SRob Herring #size-cells = <0>; 327724ba675SRob Herring clock-names = "i2c"; 328724ba675SRob Herring clocks = <&cru PCLK_I2C1>; 329724ba675SRob Herring pinctrl-names = "default"; 330724ba675SRob Herring pinctrl-0 = <&i2c1_xfer>; 331724ba675SRob Herring status = "disabled"; 332724ba675SRob Herring }; 333724ba675SRob Herring 334724ba675SRob Herring i2c3: i2c@ff150000 { 335724ba675SRob Herring compatible = "rockchip,rk3288-i2c"; 336724ba675SRob Herring reg = <0x0 0xff150000 0x0 0x1000>; 337724ba675SRob Herring interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 338724ba675SRob Herring #address-cells = <1>; 339724ba675SRob Herring #size-cells = <0>; 340724ba675SRob Herring clock-names = "i2c"; 341724ba675SRob Herring clocks = <&cru PCLK_I2C3>; 342724ba675SRob Herring pinctrl-names = "default"; 343724ba675SRob Herring pinctrl-0 = <&i2c3_xfer>; 344724ba675SRob Herring status = "disabled"; 345724ba675SRob Herring }; 346724ba675SRob Herring 347724ba675SRob Herring i2c4: i2c@ff160000 { 348724ba675SRob Herring compatible = "rockchip,rk3288-i2c"; 349724ba675SRob Herring reg = <0x0 0xff160000 0x0 0x1000>; 350724ba675SRob Herring interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 351724ba675SRob Herring #address-cells = <1>; 352724ba675SRob Herring #size-cells = <0>; 353724ba675SRob Herring clock-names = "i2c"; 354724ba675SRob Herring clocks = <&cru PCLK_I2C4>; 355724ba675SRob Herring pinctrl-names = "default"; 356724ba675SRob Herring pinctrl-0 = <&i2c4_xfer>; 357724ba675SRob Herring status = "disabled"; 358724ba675SRob Herring }; 359724ba675SRob Herring 360724ba675SRob Herring i2c5: i2c@ff170000 { 361724ba675SRob Herring compatible = "rockchip,rk3288-i2c"; 362724ba675SRob Herring reg = <0x0 0xff170000 0x0 0x1000>; 363724ba675SRob Herring interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 364724ba675SRob Herring #address-cells = <1>; 365724ba675SRob Herring #size-cells = <0>; 366724ba675SRob Herring clock-names = "i2c"; 367724ba675SRob Herring clocks = <&cru PCLK_I2C5>; 368724ba675SRob Herring pinctrl-names = "default"; 369724ba675SRob Herring pinctrl-0 = <&i2c5_xfer>; 370724ba675SRob Herring status = "disabled"; 371724ba675SRob Herring }; 372724ba675SRob Herring 373724ba675SRob Herring uart0: serial@ff180000 { 374724ba675SRob Herring compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 375724ba675SRob Herring reg = <0x0 0xff180000 0x0 0x100>; 376724ba675SRob Herring interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 377724ba675SRob Herring reg-shift = <2>; 378724ba675SRob Herring reg-io-width = <4>; 379724ba675SRob Herring clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 380724ba675SRob Herring clock-names = "baudclk", "apb_pclk"; 381724ba675SRob Herring dmas = <&dmac_peri 1>, <&dmac_peri 2>; 382724ba675SRob Herring dma-names = "tx", "rx"; 383724ba675SRob Herring pinctrl-names = "default"; 384724ba675SRob Herring pinctrl-0 = <&uart0_xfer>; 385724ba675SRob Herring status = "disabled"; 386724ba675SRob Herring }; 387724ba675SRob Herring 388724ba675SRob Herring uart1: serial@ff190000 { 389724ba675SRob Herring compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 390724ba675SRob Herring reg = <0x0 0xff190000 0x0 0x100>; 391724ba675SRob Herring interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 392724ba675SRob Herring reg-shift = <2>; 393724ba675SRob Herring reg-io-width = <4>; 394724ba675SRob Herring clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 395724ba675SRob Herring clock-names = "baudclk", "apb_pclk"; 396724ba675SRob Herring dmas = <&dmac_peri 3>, <&dmac_peri 4>; 397724ba675SRob Herring dma-names = "tx", "rx"; 398724ba675SRob Herring pinctrl-names = "default"; 399724ba675SRob Herring pinctrl-0 = <&uart1_xfer>; 400724ba675SRob Herring status = "disabled"; 401724ba675SRob Herring }; 402724ba675SRob Herring 403724ba675SRob Herring uart2: serial@ff690000 { 404724ba675SRob Herring compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 405724ba675SRob Herring reg = <0x0 0xff690000 0x0 0x100>; 406724ba675SRob Herring interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 407724ba675SRob Herring reg-shift = <2>; 408724ba675SRob Herring reg-io-width = <4>; 409724ba675SRob Herring clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 410724ba675SRob Herring clock-names = "baudclk", "apb_pclk"; 411724ba675SRob Herring pinctrl-names = "default"; 412724ba675SRob Herring pinctrl-0 = <&uart2_xfer>; 413724ba675SRob Herring status = "disabled"; 414724ba675SRob Herring }; 415724ba675SRob Herring 416724ba675SRob Herring uart3: serial@ff1b0000 { 417724ba675SRob Herring compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 418724ba675SRob Herring reg = <0x0 0xff1b0000 0x0 0x100>; 419724ba675SRob Herring interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 420724ba675SRob Herring reg-shift = <2>; 421724ba675SRob Herring reg-io-width = <4>; 422724ba675SRob Herring clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 423724ba675SRob Herring clock-names = "baudclk", "apb_pclk"; 424724ba675SRob Herring dmas = <&dmac_peri 7>, <&dmac_peri 8>; 425724ba675SRob Herring dma-names = "tx", "rx"; 426724ba675SRob Herring pinctrl-names = "default"; 427724ba675SRob Herring pinctrl-0 = <&uart3_xfer>; 428724ba675SRob Herring status = "disabled"; 429724ba675SRob Herring }; 430724ba675SRob Herring 431724ba675SRob Herring uart4: serial@ff1c0000 { 432724ba675SRob Herring compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 433724ba675SRob Herring reg = <0x0 0xff1c0000 0x0 0x100>; 434724ba675SRob Herring interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 435724ba675SRob Herring reg-shift = <2>; 436724ba675SRob Herring reg-io-width = <4>; 437724ba675SRob Herring clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 438724ba675SRob Herring clock-names = "baudclk", "apb_pclk"; 439724ba675SRob Herring dmas = <&dmac_peri 9>, <&dmac_peri 10>; 440724ba675SRob Herring dma-names = "tx", "rx"; 441724ba675SRob Herring pinctrl-names = "default"; 442724ba675SRob Herring pinctrl-0 = <&uart4_xfer>; 443724ba675SRob Herring status = "disabled"; 444724ba675SRob Herring }; 445724ba675SRob Herring 446724ba675SRob Herring dmac_peri: dma-controller@ff250000 { 447724ba675SRob Herring compatible = "arm,pl330", "arm,primecell"; 448724ba675SRob Herring reg = <0x0 0xff250000 0x0 0x4000>; 449724ba675SRob Herring interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 450724ba675SRob Herring <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 451724ba675SRob Herring #dma-cells = <1>; 452724ba675SRob Herring arm,pl330-broken-no-flushp; 453724ba675SRob Herring arm,pl330-periph-burst; 454724ba675SRob Herring clocks = <&cru ACLK_DMAC2>; 455724ba675SRob Herring clock-names = "apb_pclk"; 456724ba675SRob Herring }; 457724ba675SRob Herring 458724ba675SRob Herring thermal-zones { 459724ba675SRob Herring reserve_thermal: reserve-thermal { 460724ba675SRob Herring polling-delay-passive = <1000>; /* milliseconds */ 461724ba675SRob Herring polling-delay = <5000>; /* milliseconds */ 462724ba675SRob Herring 463724ba675SRob Herring thermal-sensors = <&tsadc 0>; 464724ba675SRob Herring }; 465724ba675SRob Herring 466724ba675SRob Herring cpu_thermal: cpu-thermal { 467724ba675SRob Herring polling-delay-passive = <100>; /* milliseconds */ 468724ba675SRob Herring polling-delay = <5000>; /* milliseconds */ 469724ba675SRob Herring 470724ba675SRob Herring thermal-sensors = <&tsadc 1>; 471724ba675SRob Herring 472724ba675SRob Herring trips { 473724ba675SRob Herring cpu_alert0: cpu_alert0 { 474724ba675SRob Herring temperature = <70000>; /* millicelsius */ 475724ba675SRob Herring hysteresis = <2000>; /* millicelsius */ 476724ba675SRob Herring type = "passive"; 477724ba675SRob Herring }; 478724ba675SRob Herring cpu_alert1: cpu_alert1 { 479724ba675SRob Herring temperature = <75000>; /* millicelsius */ 480724ba675SRob Herring hysteresis = <2000>; /* millicelsius */ 481724ba675SRob Herring type = "passive"; 482724ba675SRob Herring }; 483724ba675SRob Herring cpu_crit: cpu_crit { 484724ba675SRob Herring temperature = <90000>; /* millicelsius */ 485724ba675SRob Herring hysteresis = <2000>; /* millicelsius */ 486724ba675SRob Herring type = "critical"; 487724ba675SRob Herring }; 488724ba675SRob Herring }; 489724ba675SRob Herring 490724ba675SRob Herring cooling-maps { 491724ba675SRob Herring map0 { 492724ba675SRob Herring trip = <&cpu_alert0>; 493724ba675SRob Herring cooling-device = 494724ba675SRob Herring <&cpu0 THERMAL_NO_LIMIT 6>, 495724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT 6>, 496724ba675SRob Herring <&cpu2 THERMAL_NO_LIMIT 6>, 497724ba675SRob Herring <&cpu3 THERMAL_NO_LIMIT 6>; 498724ba675SRob Herring }; 499724ba675SRob Herring map1 { 500724ba675SRob Herring trip = <&cpu_alert1>; 501724ba675SRob Herring cooling-device = 502724ba675SRob Herring <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 503724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 504724ba675SRob Herring <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 505724ba675SRob Herring <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 506724ba675SRob Herring }; 507724ba675SRob Herring }; 508724ba675SRob Herring }; 509724ba675SRob Herring 510724ba675SRob Herring gpu_thermal: gpu-thermal { 511724ba675SRob Herring polling-delay-passive = <100>; /* milliseconds */ 512724ba675SRob Herring polling-delay = <5000>; /* milliseconds */ 513724ba675SRob Herring 514724ba675SRob Herring thermal-sensors = <&tsadc 2>; 515724ba675SRob Herring 516724ba675SRob Herring trips { 517724ba675SRob Herring gpu_alert0: gpu_alert0 { 518724ba675SRob Herring temperature = <70000>; /* millicelsius */ 519724ba675SRob Herring hysteresis = <2000>; /* millicelsius */ 520724ba675SRob Herring type = "passive"; 521724ba675SRob Herring }; 522724ba675SRob Herring gpu_crit: gpu_crit { 523724ba675SRob Herring temperature = <90000>; /* millicelsius */ 524724ba675SRob Herring hysteresis = <2000>; /* millicelsius */ 525724ba675SRob Herring type = "critical"; 526724ba675SRob Herring }; 527724ba675SRob Herring }; 528724ba675SRob Herring 529724ba675SRob Herring cooling-maps { 530724ba675SRob Herring map0 { 531724ba675SRob Herring trip = <&gpu_alert0>; 532724ba675SRob Herring cooling-device = 533724ba675SRob Herring <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 534724ba675SRob Herring }; 535724ba675SRob Herring }; 536724ba675SRob Herring }; 537724ba675SRob Herring }; 538724ba675SRob Herring 539724ba675SRob Herring tsadc: tsadc@ff280000 { 540724ba675SRob Herring compatible = "rockchip,rk3288-tsadc"; 541724ba675SRob Herring reg = <0x0 0xff280000 0x0 0x100>; 542724ba675SRob Herring interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 543724ba675SRob Herring clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 544724ba675SRob Herring clock-names = "tsadc", "apb_pclk"; 545724ba675SRob Herring resets = <&cru SRST_TSADC>; 546724ba675SRob Herring reset-names = "tsadc-apb"; 547724ba675SRob Herring pinctrl-names = "init", "default", "sleep"; 548724ba675SRob Herring pinctrl-0 = <&otp_pin>; 549724ba675SRob Herring pinctrl-1 = <&otp_out>; 550724ba675SRob Herring pinctrl-2 = <&otp_pin>; 551724ba675SRob Herring #thermal-sensor-cells = <1>; 552724ba675SRob Herring rockchip,grf = <&grf>; 553724ba675SRob Herring rockchip,hw-tshut-temp = <95000>; 554724ba675SRob Herring status = "disabled"; 555724ba675SRob Herring }; 556724ba675SRob Herring 557724ba675SRob Herring gmac: ethernet@ff290000 { 558724ba675SRob Herring compatible = "rockchip,rk3288-gmac"; 559724ba675SRob Herring reg = <0x0 0xff290000 0x0 0x10000>; 560724ba675SRob Herring interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 561724ba675SRob Herring <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 562724ba675SRob Herring interrupt-names = "macirq", "eth_wake_irq"; 563724ba675SRob Herring rockchip,grf = <&grf>; 564724ba675SRob Herring clocks = <&cru SCLK_MAC>, 565724ba675SRob Herring <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 566724ba675SRob Herring <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 567724ba675SRob Herring <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 568724ba675SRob Herring clock-names = "stmmaceth", 569724ba675SRob Herring "mac_clk_rx", "mac_clk_tx", 570724ba675SRob Herring "clk_mac_ref", "clk_mac_refout", 571724ba675SRob Herring "aclk_mac", "pclk_mac"; 572724ba675SRob Herring resets = <&cru SRST_MAC>; 573724ba675SRob Herring reset-names = "stmmaceth"; 574724ba675SRob Herring status = "disabled"; 575724ba675SRob Herring }; 576724ba675SRob Herring 577724ba675SRob Herring usb_host0_ehci: usb@ff500000 { 578724ba675SRob Herring compatible = "generic-ehci"; 579724ba675SRob Herring reg = <0x0 0xff500000 0x0 0x100>; 580724ba675SRob Herring interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 581724ba675SRob Herring clocks = <&cru HCLK_USBHOST0>; 582724ba675SRob Herring phys = <&usbphy1>; 583724ba675SRob Herring phy-names = "usb"; 584724ba675SRob Herring status = "disabled"; 585724ba675SRob Herring }; 586724ba675SRob Herring 587724ba675SRob Herring /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */ 588724ba675SRob Herring usb_host0_ohci: usb@ff520000 { 589724ba675SRob Herring compatible = "generic-ohci"; 590724ba675SRob Herring reg = <0x0 0xff520000 0x0 0x100>; 591724ba675SRob Herring interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 592724ba675SRob Herring clocks = <&cru HCLK_USBHOST0>; 593724ba675SRob Herring phys = <&usbphy1>; 594724ba675SRob Herring phy-names = "usb"; 595724ba675SRob Herring status = "disabled"; 596724ba675SRob Herring }; 597724ba675SRob Herring 598724ba675SRob Herring usb_host1: usb@ff540000 { 599724ba675SRob Herring compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 600724ba675SRob Herring "snps,dwc2"; 601724ba675SRob Herring reg = <0x0 0xff540000 0x0 0x40000>; 602724ba675SRob Herring interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 603724ba675SRob Herring clocks = <&cru HCLK_USBHOST1>; 604724ba675SRob Herring clock-names = "otg"; 605724ba675SRob Herring dr_mode = "host"; 606724ba675SRob Herring phys = <&usbphy2>; 607724ba675SRob Herring phy-names = "usb2-phy"; 608724ba675SRob Herring snps,reset-phy-on-wake; 609724ba675SRob Herring status = "disabled"; 610724ba675SRob Herring }; 611724ba675SRob Herring 612724ba675SRob Herring usb_otg: usb@ff580000 { 613724ba675SRob Herring compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 614724ba675SRob Herring "snps,dwc2"; 615724ba675SRob Herring reg = <0x0 0xff580000 0x0 0x40000>; 616724ba675SRob Herring interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 617724ba675SRob Herring clocks = <&cru HCLK_OTG0>; 618724ba675SRob Herring clock-names = "otg"; 619724ba675SRob Herring dr_mode = "otg"; 620724ba675SRob Herring g-np-tx-fifo-size = <16>; 621724ba675SRob Herring g-rx-fifo-size = <275>; 622724ba675SRob Herring g-tx-fifo-size = <256 128 128 64 64 32>; 623724ba675SRob Herring phys = <&usbphy0>; 624724ba675SRob Herring phy-names = "usb2-phy"; 625724ba675SRob Herring status = "disabled"; 626724ba675SRob Herring }; 627724ba675SRob Herring 628724ba675SRob Herring usb_hsic: usb@ff5c0000 { 629724ba675SRob Herring compatible = "generic-ehci"; 630724ba675SRob Herring reg = <0x0 0xff5c0000 0x0 0x100>; 631724ba675SRob Herring interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 632724ba675SRob Herring clocks = <&cru HCLK_HSIC>; 633724ba675SRob Herring status = "disabled"; 634724ba675SRob Herring }; 635724ba675SRob Herring 636724ba675SRob Herring dmac_bus_ns: dma-controller@ff600000 { 637724ba675SRob Herring compatible = "arm,pl330", "arm,primecell"; 638724ba675SRob Herring reg = <0x0 0xff600000 0x0 0x4000>; 639724ba675SRob Herring interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 640724ba675SRob Herring <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 641724ba675SRob Herring #dma-cells = <1>; 642724ba675SRob Herring arm,pl330-broken-no-flushp; 643724ba675SRob Herring arm,pl330-periph-burst; 644724ba675SRob Herring clocks = <&cru ACLK_DMAC1>; 645724ba675SRob Herring clock-names = "apb_pclk"; 646724ba675SRob Herring status = "disabled"; 647724ba675SRob Herring }; 648724ba675SRob Herring 649724ba675SRob Herring i2c0: i2c@ff650000 { 650724ba675SRob Herring compatible = "rockchip,rk3288-i2c"; 651724ba675SRob Herring reg = <0x0 0xff650000 0x0 0x1000>; 652724ba675SRob Herring interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 653724ba675SRob Herring #address-cells = <1>; 654724ba675SRob Herring #size-cells = <0>; 655724ba675SRob Herring clock-names = "i2c"; 656724ba675SRob Herring clocks = <&cru PCLK_I2C0>; 657724ba675SRob Herring pinctrl-names = "default"; 658724ba675SRob Herring pinctrl-0 = <&i2c0_xfer>; 659724ba675SRob Herring status = "disabled"; 660724ba675SRob Herring }; 661724ba675SRob Herring 662724ba675SRob Herring i2c2: i2c@ff660000 { 663724ba675SRob Herring compatible = "rockchip,rk3288-i2c"; 664724ba675SRob Herring reg = <0x0 0xff660000 0x0 0x1000>; 665724ba675SRob Herring interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 666724ba675SRob Herring #address-cells = <1>; 667724ba675SRob Herring #size-cells = <0>; 668724ba675SRob Herring clock-names = "i2c"; 669724ba675SRob Herring clocks = <&cru PCLK_I2C2>; 670724ba675SRob Herring pinctrl-names = "default"; 671724ba675SRob Herring pinctrl-0 = <&i2c2_xfer>; 672724ba675SRob Herring status = "disabled"; 673724ba675SRob Herring }; 674724ba675SRob Herring 675724ba675SRob Herring pwm0: pwm@ff680000 { 676724ba675SRob Herring compatible = "rockchip,rk3288-pwm"; 677724ba675SRob Herring reg = <0x0 0xff680000 0x0 0x10>; 678724ba675SRob Herring #pwm-cells = <3>; 679724ba675SRob Herring pinctrl-names = "default"; 680724ba675SRob Herring pinctrl-0 = <&pwm0_pin>; 681724ba675SRob Herring clocks = <&cru PCLK_RKPWM>; 682724ba675SRob Herring status = "disabled"; 683724ba675SRob Herring }; 684724ba675SRob Herring 685724ba675SRob Herring pwm1: pwm@ff680010 { 686724ba675SRob Herring compatible = "rockchip,rk3288-pwm"; 687724ba675SRob Herring reg = <0x0 0xff680010 0x0 0x10>; 688724ba675SRob Herring #pwm-cells = <3>; 689724ba675SRob Herring pinctrl-names = "default"; 690724ba675SRob Herring pinctrl-0 = <&pwm1_pin>; 691724ba675SRob Herring clocks = <&cru PCLK_RKPWM>; 692724ba675SRob Herring status = "disabled"; 693724ba675SRob Herring }; 694724ba675SRob Herring 695724ba675SRob Herring pwm2: pwm@ff680020 { 696724ba675SRob Herring compatible = "rockchip,rk3288-pwm"; 697724ba675SRob Herring reg = <0x0 0xff680020 0x0 0x10>; 698724ba675SRob Herring #pwm-cells = <3>; 699724ba675SRob Herring pinctrl-names = "default"; 700724ba675SRob Herring pinctrl-0 = <&pwm2_pin>; 701724ba675SRob Herring clocks = <&cru PCLK_RKPWM>; 702724ba675SRob Herring status = "disabled"; 703724ba675SRob Herring }; 704724ba675SRob Herring 705724ba675SRob Herring pwm3: pwm@ff680030 { 706724ba675SRob Herring compatible = "rockchip,rk3288-pwm"; 707724ba675SRob Herring reg = <0x0 0xff680030 0x0 0x10>; 708724ba675SRob Herring #pwm-cells = <3>; 709724ba675SRob Herring pinctrl-names = "default"; 710724ba675SRob Herring pinctrl-0 = <&pwm3_pin>; 711724ba675SRob Herring clocks = <&cru PCLK_RKPWM>; 712724ba675SRob Herring status = "disabled"; 713724ba675SRob Herring }; 714724ba675SRob Herring 715724ba675SRob Herring bus_intmem: sram@ff700000 { 716724ba675SRob Herring compatible = "mmio-sram"; 717724ba675SRob Herring reg = <0x0 0xff700000 0x0 0x18000>; 718724ba675SRob Herring #address-cells = <1>; 719724ba675SRob Herring #size-cells = <1>; 720724ba675SRob Herring ranges = <0 0x0 0xff700000 0x18000>; 721724ba675SRob Herring smp-sram@0 { 722724ba675SRob Herring compatible = "rockchip,rk3066-smp-sram"; 723724ba675SRob Herring reg = <0x00 0x10>; 724724ba675SRob Herring }; 725724ba675SRob Herring }; 726724ba675SRob Herring 727724ba675SRob Herring pmu_sram: sram@ff720000 { 728724ba675SRob Herring compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 729724ba675SRob Herring reg = <0x0 0xff720000 0x0 0x1000>; 730724ba675SRob Herring }; 731724ba675SRob Herring 732724ba675SRob Herring pmu: power-management@ff730000 { 733724ba675SRob Herring compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; 734724ba675SRob Herring reg = <0x0 0xff730000 0x0 0x100>; 735724ba675SRob Herring 736724ba675SRob Herring power: power-controller { 737724ba675SRob Herring compatible = "rockchip,rk3288-power-controller"; 738724ba675SRob Herring #power-domain-cells = <1>; 739724ba675SRob Herring #address-cells = <1>; 740724ba675SRob Herring #size-cells = <0>; 741724ba675SRob Herring 742724ba675SRob Herring assigned-clocks = <&cru SCLK_EDP_24M>; 743724ba675SRob Herring assigned-clock-parents = <&xin24m>; 744724ba675SRob Herring 745724ba675SRob Herring /* 746724ba675SRob Herring * Note: Although SCLK_* are the working clocks 747724ba675SRob Herring * of device without including on the NOC, needed for 748724ba675SRob Herring * synchronous reset. 749724ba675SRob Herring * 750724ba675SRob Herring * The clocks on the which NOC: 751724ba675SRob Herring * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. 752724ba675SRob Herring * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. 753724ba675SRob Herring * ACLK_RGA is on ACLK_RGA_NIU. 754724ba675SRob Herring * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. 755724ba675SRob Herring * 756724ba675SRob Herring * Which clock are device clocks: 757724ba675SRob Herring * clocks devices 758724ba675SRob Herring * *_IEP IEP:Image Enhancement Processor 759724ba675SRob Herring * *_ISP ISP:Image Signal Processing 760724ba675SRob Herring * *_VIP VIP:Video Input Processor 761724ba675SRob Herring * *_VOP* VOP:Visual Output Processor 762724ba675SRob Herring * *_RGA RGA 763724ba675SRob Herring * *_EDP* EDP 764724ba675SRob Herring * *_LVDS_* LVDS 765724ba675SRob Herring * *_HDMI HDMI 766724ba675SRob Herring * *_MIPI_* MIPI 767724ba675SRob Herring */ 768724ba675SRob Herring power-domain@RK3288_PD_VIO { 769724ba675SRob Herring reg = <RK3288_PD_VIO>; 770724ba675SRob Herring clocks = <&cru ACLK_IEP>, 771724ba675SRob Herring <&cru ACLK_ISP>, 772724ba675SRob Herring <&cru ACLK_RGA>, 773724ba675SRob Herring <&cru ACLK_VIP>, 774724ba675SRob Herring <&cru ACLK_VOP0>, 775724ba675SRob Herring <&cru ACLK_VOP1>, 776724ba675SRob Herring <&cru DCLK_VOP0>, 777724ba675SRob Herring <&cru DCLK_VOP1>, 778724ba675SRob Herring <&cru HCLK_IEP>, 779724ba675SRob Herring <&cru HCLK_ISP>, 780724ba675SRob Herring <&cru HCLK_RGA>, 781724ba675SRob Herring <&cru HCLK_VIP>, 782724ba675SRob Herring <&cru HCLK_VOP0>, 783724ba675SRob Herring <&cru HCLK_VOP1>, 784724ba675SRob Herring <&cru PCLK_EDP_CTRL>, 785724ba675SRob Herring <&cru PCLK_HDMI_CTRL>, 786724ba675SRob Herring <&cru PCLK_LVDS_PHY>, 787724ba675SRob Herring <&cru PCLK_MIPI_CSI>, 788724ba675SRob Herring <&cru PCLK_MIPI_DSI0>, 789724ba675SRob Herring <&cru PCLK_MIPI_DSI1>, 790724ba675SRob Herring <&cru SCLK_EDP_24M>, 791724ba675SRob Herring <&cru SCLK_EDP>, 792724ba675SRob Herring <&cru SCLK_ISP_JPE>, 793724ba675SRob Herring <&cru SCLK_ISP>, 794724ba675SRob Herring <&cru SCLK_RGA>; 795724ba675SRob Herring pm_qos = <&qos_vio0_iep>, 796724ba675SRob Herring <&qos_vio1_vop>, 797724ba675SRob Herring <&qos_vio1_isp_w0>, 798724ba675SRob Herring <&qos_vio1_isp_w1>, 799724ba675SRob Herring <&qos_vio0_vop>, 800724ba675SRob Herring <&qos_vio0_vip>, 801724ba675SRob Herring <&qos_vio2_rga_r>, 802724ba675SRob Herring <&qos_vio2_rga_w>, 803724ba675SRob Herring <&qos_vio1_isp_r>; 804724ba675SRob Herring #power-domain-cells = <0>; 805724ba675SRob Herring }; 806724ba675SRob Herring 807724ba675SRob Herring /* 808724ba675SRob Herring * Note: The following 3 are HEVC(H.265) clocks, 809724ba675SRob Herring * and on the ACLK_HEVC_NIU (NOC). 810724ba675SRob Herring */ 811724ba675SRob Herring power-domain@RK3288_PD_HEVC { 812724ba675SRob Herring reg = <RK3288_PD_HEVC>; 813724ba675SRob Herring clocks = <&cru ACLK_HEVC>, 814724ba675SRob Herring <&cru SCLK_HEVC_CABAC>, 815724ba675SRob Herring <&cru SCLK_HEVC_CORE>; 816724ba675SRob Herring pm_qos = <&qos_hevc_r>, 817724ba675SRob Herring <&qos_hevc_w>; 818724ba675SRob Herring #power-domain-cells = <0>; 819724ba675SRob Herring }; 820724ba675SRob Herring 821724ba675SRob Herring /* 822724ba675SRob Herring * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC 823724ba675SRob Herring * (video endecoder & decoder) clocks that on the 824724ba675SRob Herring * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). 825724ba675SRob Herring */ 826724ba675SRob Herring power-domain@RK3288_PD_VIDEO { 827724ba675SRob Herring reg = <RK3288_PD_VIDEO>; 828724ba675SRob Herring clocks = <&cru ACLK_VCODEC>, 829724ba675SRob Herring <&cru HCLK_VCODEC>; 830724ba675SRob Herring pm_qos = <&qos_video>; 831724ba675SRob Herring #power-domain-cells = <0>; 832724ba675SRob Herring }; 833724ba675SRob Herring 834724ba675SRob Herring /* 835724ba675SRob Herring * Note: ACLK_GPU is the GPU clock, 836724ba675SRob Herring * and on the ACLK_GPU_NIU (NOC). 837724ba675SRob Herring */ 838724ba675SRob Herring power-domain@RK3288_PD_GPU { 839724ba675SRob Herring reg = <RK3288_PD_GPU>; 840724ba675SRob Herring clocks = <&cru ACLK_GPU>; 841724ba675SRob Herring pm_qos = <&qos_gpu_r>, 842724ba675SRob Herring <&qos_gpu_w>; 843724ba675SRob Herring #power-domain-cells = <0>; 844724ba675SRob Herring }; 845724ba675SRob Herring }; 846724ba675SRob Herring 847724ba675SRob Herring reboot-mode { 848724ba675SRob Herring compatible = "syscon-reboot-mode"; 849724ba675SRob Herring offset = <0x94>; 850724ba675SRob Herring mode-normal = <BOOT_NORMAL>; 851724ba675SRob Herring mode-recovery = <BOOT_RECOVERY>; 852724ba675SRob Herring mode-bootloader = <BOOT_FASTBOOT>; 853724ba675SRob Herring mode-loader = <BOOT_BL_DOWNLOAD>; 854724ba675SRob Herring }; 855724ba675SRob Herring }; 856724ba675SRob Herring 857724ba675SRob Herring sgrf: syscon@ff740000 { 858724ba675SRob Herring compatible = "rockchip,rk3288-sgrf", "syscon"; 859724ba675SRob Herring reg = <0x0 0xff740000 0x0 0x1000>; 860724ba675SRob Herring }; 861724ba675SRob Herring 862724ba675SRob Herring cru: clock-controller@ff760000 { 863724ba675SRob Herring compatible = "rockchip,rk3288-cru"; 864724ba675SRob Herring reg = <0x0 0xff760000 0x0 0x1000>; 865724ba675SRob Herring clocks = <&xin24m>; 866724ba675SRob Herring clock-names = "xin24m"; 867724ba675SRob Herring rockchip,grf = <&grf>; 868724ba675SRob Herring #clock-cells = <1>; 869724ba675SRob Herring #reset-cells = <1>; 870724ba675SRob Herring assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, 871724ba675SRob Herring <&cru PLL_NPLL>, <&cru ACLK_CPU>, 872724ba675SRob Herring <&cru HCLK_CPU>, <&cru PCLK_CPU>, 873724ba675SRob Herring <&cru ACLK_PERI>, <&cru HCLK_PERI>, 874724ba675SRob Herring <&cru PCLK_PERI>; 875724ba675SRob Herring assigned-clock-rates = <594000000>, <400000000>, 876724ba675SRob Herring <500000000>, <300000000>, 877724ba675SRob Herring <150000000>, <75000000>, 878724ba675SRob Herring <300000000>, <150000000>, 879724ba675SRob Herring <75000000>; 880724ba675SRob Herring }; 881724ba675SRob Herring 882724ba675SRob Herring grf: syscon@ff770000 { 883724ba675SRob Herring compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; 884724ba675SRob Herring reg = <0x0 0xff770000 0x0 0x1000>; 885724ba675SRob Herring 886724ba675SRob Herring edp_phy: edp-phy { 887724ba675SRob Herring compatible = "rockchip,rk3288-dp-phy"; 888724ba675SRob Herring clocks = <&cru SCLK_EDP_24M>; 889724ba675SRob Herring clock-names = "24m"; 890724ba675SRob Herring #phy-cells = <0>; 891724ba675SRob Herring status = "disabled"; 892724ba675SRob Herring }; 893724ba675SRob Herring 894724ba675SRob Herring io_domains: io-domains { 895724ba675SRob Herring compatible = "rockchip,rk3288-io-voltage-domain"; 896724ba675SRob Herring status = "disabled"; 897724ba675SRob Herring }; 898724ba675SRob Herring 899724ba675SRob Herring usbphy: usbphy { 900724ba675SRob Herring compatible = "rockchip,rk3288-usb-phy"; 901724ba675SRob Herring #address-cells = <1>; 902724ba675SRob Herring #size-cells = <0>; 903724ba675SRob Herring status = "disabled"; 904724ba675SRob Herring 905724ba675SRob Herring usbphy0: usb-phy@320 { 906724ba675SRob Herring #phy-cells = <0>; 907724ba675SRob Herring reg = <0x320>; 908724ba675SRob Herring clocks = <&cru SCLK_OTGPHY0>; 909724ba675SRob Herring clock-names = "phyclk"; 910724ba675SRob Herring #clock-cells = <0>; 911724ba675SRob Herring resets = <&cru SRST_USBOTG_PHY>; 912724ba675SRob Herring reset-names = "phy-reset"; 913724ba675SRob Herring }; 914724ba675SRob Herring 915724ba675SRob Herring usbphy1: usb-phy@334 { 916724ba675SRob Herring #phy-cells = <0>; 917724ba675SRob Herring reg = <0x334>; 918724ba675SRob Herring clocks = <&cru SCLK_OTGPHY1>; 919724ba675SRob Herring clock-names = "phyclk"; 920724ba675SRob Herring #clock-cells = <0>; 921724ba675SRob Herring resets = <&cru SRST_USBHOST0_PHY>; 922724ba675SRob Herring reset-names = "phy-reset"; 923724ba675SRob Herring }; 924724ba675SRob Herring 925724ba675SRob Herring usbphy2: usb-phy@348 { 926724ba675SRob Herring #phy-cells = <0>; 927724ba675SRob Herring reg = <0x348>; 928724ba675SRob Herring clocks = <&cru SCLK_OTGPHY2>; 929724ba675SRob Herring clock-names = "phyclk"; 930724ba675SRob Herring #clock-cells = <0>; 931724ba675SRob Herring resets = <&cru SRST_USBHOST1_PHY>; 932724ba675SRob Herring reset-names = "phy-reset"; 933724ba675SRob Herring }; 934724ba675SRob Herring }; 935724ba675SRob Herring }; 936724ba675SRob Herring 937724ba675SRob Herring wdt: watchdog@ff800000 { 938724ba675SRob Herring compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; 939724ba675SRob Herring reg = <0x0 0xff800000 0x0 0x100>; 940724ba675SRob Herring clocks = <&cru PCLK_WDT>; 941724ba675SRob Herring interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 942724ba675SRob Herring status = "disabled"; 943724ba675SRob Herring }; 944724ba675SRob Herring 945724ba675SRob Herring spdif: sound@ff8b0000 { 946724ba675SRob Herring compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; 947724ba675SRob Herring reg = <0x0 0xff8b0000 0x0 0x10000>; 948724ba675SRob Herring #sound-dai-cells = <0>; 949724ba675SRob Herring clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>; 950724ba675SRob Herring clock-names = "mclk", "hclk"; 951724ba675SRob Herring dmas = <&dmac_bus_s 3>; 952724ba675SRob Herring dma-names = "tx"; 953724ba675SRob Herring interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 954724ba675SRob Herring pinctrl-names = "default"; 955724ba675SRob Herring pinctrl-0 = <&spdif_tx>; 956724ba675SRob Herring rockchip,grf = <&grf>; 957724ba675SRob Herring status = "disabled"; 958724ba675SRob Herring }; 959724ba675SRob Herring 960724ba675SRob Herring i2s: i2s@ff890000 { 961724ba675SRob Herring compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; 962724ba675SRob Herring reg = <0x0 0xff890000 0x0 0x10000>; 963724ba675SRob Herring #sound-dai-cells = <0>; 964724ba675SRob Herring interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 965724ba675SRob Herring clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; 966724ba675SRob Herring clock-names = "i2s_clk", "i2s_hclk"; 967724ba675SRob Herring dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; 968724ba675SRob Herring dma-names = "tx", "rx"; 969724ba675SRob Herring pinctrl-names = "default"; 970724ba675SRob Herring pinctrl-0 = <&i2s0_bus>; 971724ba675SRob Herring rockchip,playback-channels = <8>; 972724ba675SRob Herring rockchip,capture-channels = <2>; 973724ba675SRob Herring status = "disabled"; 974724ba675SRob Herring }; 975724ba675SRob Herring 976724ba675SRob Herring crypto: crypto@ff8a0000 { 977724ba675SRob Herring compatible = "rockchip,rk3288-crypto"; 978724ba675SRob Herring reg = <0x0 0xff8a0000 0x0 0x4000>; 979724ba675SRob Herring interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 980724ba675SRob Herring clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, 981724ba675SRob Herring <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; 982724ba675SRob Herring clock-names = "aclk", "hclk", "sclk", "apb_pclk"; 983724ba675SRob Herring resets = <&cru SRST_CRYPTO>; 984724ba675SRob Herring reset-names = "crypto-rst"; 985724ba675SRob Herring }; 986724ba675SRob Herring 987724ba675SRob Herring iep_mmu: iommu@ff900800 { 988724ba675SRob Herring compatible = "rockchip,iommu"; 989724ba675SRob Herring reg = <0x0 0xff900800 0x0 0x40>; 990724ba675SRob Herring interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 991724ba675SRob Herring clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 992724ba675SRob Herring clock-names = "aclk", "iface"; 993724ba675SRob Herring #iommu-cells = <0>; 994724ba675SRob Herring status = "disabled"; 995724ba675SRob Herring }; 996724ba675SRob Herring 997724ba675SRob Herring isp_mmu: iommu@ff914000 { 998724ba675SRob Herring compatible = "rockchip,iommu"; 999724ba675SRob Herring reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1000724ba675SRob Herring interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1001724ba675SRob Herring clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1002724ba675SRob Herring clock-names = "aclk", "iface"; 1003724ba675SRob Herring #iommu-cells = <0>; 1004724ba675SRob Herring rockchip,disable-mmu-reset; 1005724ba675SRob Herring status = "disabled"; 1006724ba675SRob Herring }; 1007724ba675SRob Herring 1008724ba675SRob Herring rga: rga@ff920000 { 1009724ba675SRob Herring compatible = "rockchip,rk3288-rga"; 1010724ba675SRob Herring reg = <0x0 0xff920000 0x0 0x180>; 1011724ba675SRob Herring interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1012724ba675SRob Herring clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; 1013724ba675SRob Herring clock-names = "aclk", "hclk", "sclk"; 1014724ba675SRob Herring power-domains = <&power RK3288_PD_VIO>; 1015724ba675SRob Herring resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; 1016724ba675SRob Herring reset-names = "core", "axi", "ahb"; 1017724ba675SRob Herring }; 1018724ba675SRob Herring 1019724ba675SRob Herring vopb: vop@ff930000 { 1020724ba675SRob Herring compatible = "rockchip,rk3288-vop"; 1021724ba675SRob Herring reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; 1022724ba675SRob Herring interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1023724ba675SRob Herring clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1024724ba675SRob Herring clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1025724ba675SRob Herring power-domains = <&power RK3288_PD_VIO>; 1026724ba675SRob Herring resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 1027724ba675SRob Herring reset-names = "axi", "ahb", "dclk"; 1028724ba675SRob Herring iommus = <&vopb_mmu>; 1029724ba675SRob Herring status = "disabled"; 1030724ba675SRob Herring 1031724ba675SRob Herring vopb_out: port { 1032724ba675SRob Herring #address-cells = <1>; 1033724ba675SRob Herring #size-cells = <0>; 1034724ba675SRob Herring 1035724ba675SRob Herring vopb_out_hdmi: endpoint@0 { 1036724ba675SRob Herring reg = <0>; 1037724ba675SRob Herring remote-endpoint = <&hdmi_in_vopb>; 1038724ba675SRob Herring }; 1039724ba675SRob Herring 1040724ba675SRob Herring vopb_out_edp: endpoint@1 { 1041724ba675SRob Herring reg = <1>; 1042724ba675SRob Herring remote-endpoint = <&edp_in_vopb>; 1043724ba675SRob Herring }; 1044724ba675SRob Herring 1045724ba675SRob Herring vopb_out_mipi: endpoint@2 { 1046724ba675SRob Herring reg = <2>; 1047724ba675SRob Herring remote-endpoint = <&mipi_in_vopb>; 1048724ba675SRob Herring }; 1049724ba675SRob Herring 1050724ba675SRob Herring vopb_out_lvds: endpoint@3 { 1051724ba675SRob Herring reg = <3>; 1052724ba675SRob Herring remote-endpoint = <&lvds_in_vopb>; 1053724ba675SRob Herring }; 1054724ba675SRob Herring }; 1055724ba675SRob Herring }; 1056724ba675SRob Herring 1057724ba675SRob Herring vopb_mmu: iommu@ff930300 { 1058724ba675SRob Herring compatible = "rockchip,iommu"; 1059724ba675SRob Herring reg = <0x0 0xff930300 0x0 0x100>; 1060724ba675SRob Herring interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1061724ba675SRob Herring clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1062724ba675SRob Herring clock-names = "aclk", "iface"; 1063724ba675SRob Herring power-domains = <&power RK3288_PD_VIO>; 1064724ba675SRob Herring #iommu-cells = <0>; 1065724ba675SRob Herring status = "disabled"; 1066724ba675SRob Herring }; 1067724ba675SRob Herring 1068724ba675SRob Herring vopl: vop@ff940000 { 1069724ba675SRob Herring compatible = "rockchip,rk3288-vop"; 1070724ba675SRob Herring reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>; 1071724ba675SRob Herring interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1072724ba675SRob Herring clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1073724ba675SRob Herring clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1074724ba675SRob Herring power-domains = <&power RK3288_PD_VIO>; 1075724ba675SRob Herring resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 1076724ba675SRob Herring reset-names = "axi", "ahb", "dclk"; 1077724ba675SRob Herring iommus = <&vopl_mmu>; 1078724ba675SRob Herring status = "disabled"; 1079724ba675SRob Herring 1080724ba675SRob Herring vopl_out: port { 1081724ba675SRob Herring #address-cells = <1>; 1082724ba675SRob Herring #size-cells = <0>; 1083724ba675SRob Herring 1084724ba675SRob Herring vopl_out_hdmi: endpoint@0 { 1085724ba675SRob Herring reg = <0>; 1086724ba675SRob Herring remote-endpoint = <&hdmi_in_vopl>; 1087724ba675SRob Herring }; 1088724ba675SRob Herring 1089724ba675SRob Herring vopl_out_edp: endpoint@1 { 1090724ba675SRob Herring reg = <1>; 1091724ba675SRob Herring remote-endpoint = <&edp_in_vopl>; 1092724ba675SRob Herring }; 1093724ba675SRob Herring 1094724ba675SRob Herring vopl_out_mipi: endpoint@2 { 1095724ba675SRob Herring reg = <2>; 1096724ba675SRob Herring remote-endpoint = <&mipi_in_vopl>; 1097724ba675SRob Herring }; 1098724ba675SRob Herring 1099724ba675SRob Herring vopl_out_lvds: endpoint@3 { 1100724ba675SRob Herring reg = <3>; 1101724ba675SRob Herring remote-endpoint = <&lvds_in_vopl>; 1102724ba675SRob Herring }; 1103724ba675SRob Herring }; 1104724ba675SRob Herring }; 1105724ba675SRob Herring 1106724ba675SRob Herring vopl_mmu: iommu@ff940300 { 1107724ba675SRob Herring compatible = "rockchip,iommu"; 1108724ba675SRob Herring reg = <0x0 0xff940300 0x0 0x100>; 1109724ba675SRob Herring interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1110724ba675SRob Herring clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1111724ba675SRob Herring clock-names = "aclk", "iface"; 1112724ba675SRob Herring power-domains = <&power RK3288_PD_VIO>; 1113724ba675SRob Herring #iommu-cells = <0>; 1114724ba675SRob Herring status = "disabled"; 1115724ba675SRob Herring }; 1116724ba675SRob Herring 1117724ba675SRob Herring mipi_dsi: dsi@ff960000 { 1118724ba675SRob Herring compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; 1119724ba675SRob Herring reg = <0x0 0xff960000 0x0 0x4000>; 1120724ba675SRob Herring interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1121724ba675SRob Herring clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; 1122724ba675SRob Herring clock-names = "ref", "pclk"; 1123724ba675SRob Herring power-domains = <&power RK3288_PD_VIO>; 1124724ba675SRob Herring rockchip,grf = <&grf>; 1125724ba675SRob Herring status = "disabled"; 1126724ba675SRob Herring 1127724ba675SRob Herring ports { 1128724ba675SRob Herring #address-cells = <1>; 1129724ba675SRob Herring #size-cells = <0>; 1130724ba675SRob Herring 1131724ba675SRob Herring mipi_in: port@0 { 1132724ba675SRob Herring reg = <0>; 1133724ba675SRob Herring #address-cells = <1>; 1134724ba675SRob Herring #size-cells = <0>; 1135724ba675SRob Herring 1136724ba675SRob Herring mipi_in_vopb: endpoint@0 { 1137724ba675SRob Herring reg = <0>; 1138724ba675SRob Herring remote-endpoint = <&vopb_out_mipi>; 1139724ba675SRob Herring }; 1140724ba675SRob Herring 1141724ba675SRob Herring mipi_in_vopl: endpoint@1 { 1142724ba675SRob Herring reg = <1>; 1143724ba675SRob Herring remote-endpoint = <&vopl_out_mipi>; 1144724ba675SRob Herring }; 1145724ba675SRob Herring }; 1146724ba675SRob Herring 1147724ba675SRob Herring mipi_out: port@1 { 1148724ba675SRob Herring reg = <1>; 1149724ba675SRob Herring }; 1150724ba675SRob Herring }; 1151724ba675SRob Herring }; 1152724ba675SRob Herring 1153724ba675SRob Herring lvds: lvds@ff96c000 { 1154724ba675SRob Herring compatible = "rockchip,rk3288-lvds"; 1155724ba675SRob Herring reg = <0x0 0xff96c000 0x0 0x4000>; 1156724ba675SRob Herring clocks = <&cru PCLK_LVDS_PHY>; 1157724ba675SRob Herring clock-names = "pclk_lvds"; 1158724ba675SRob Herring pinctrl-names = "lcdc"; 1159724ba675SRob Herring pinctrl-0 = <&lcdc_ctl>; 1160724ba675SRob Herring power-domains = <&power RK3288_PD_VIO>; 1161724ba675SRob Herring rockchip,grf = <&grf>; 1162724ba675SRob Herring status = "disabled"; 1163724ba675SRob Herring 1164724ba675SRob Herring ports { 1165724ba675SRob Herring #address-cells = <1>; 1166724ba675SRob Herring #size-cells = <0>; 1167724ba675SRob Herring 1168724ba675SRob Herring lvds_in: port@0 { 1169724ba675SRob Herring reg = <0>; 1170724ba675SRob Herring #address-cells = <1>; 1171724ba675SRob Herring #size-cells = <0>; 1172724ba675SRob Herring 1173724ba675SRob Herring lvds_in_vopb: endpoint@0 { 1174724ba675SRob Herring reg = <0>; 1175724ba675SRob Herring remote-endpoint = <&vopb_out_lvds>; 1176724ba675SRob Herring }; 1177724ba675SRob Herring 1178724ba675SRob Herring lvds_in_vopl: endpoint@1 { 1179724ba675SRob Herring reg = <1>; 1180724ba675SRob Herring remote-endpoint = <&vopl_out_lvds>; 1181724ba675SRob Herring }; 1182724ba675SRob Herring }; 1183724ba675SRob Herring 1184724ba675SRob Herring lvds_out: port@1 { 1185724ba675SRob Herring reg = <1>; 1186724ba675SRob Herring }; 1187724ba675SRob Herring }; 1188724ba675SRob Herring }; 1189724ba675SRob Herring 1190724ba675SRob Herring edp: dp@ff970000 { 1191724ba675SRob Herring compatible = "rockchip,rk3288-dp"; 1192724ba675SRob Herring reg = <0x0 0xff970000 0x0 0x4000>; 1193724ba675SRob Herring interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1194724ba675SRob Herring clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; 1195724ba675SRob Herring clock-names = "dp", "pclk"; 1196724ba675SRob Herring phys = <&edp_phy>; 1197724ba675SRob Herring phy-names = "dp"; 1198724ba675SRob Herring power-domains = <&power RK3288_PD_VIO>; 1199724ba675SRob Herring resets = <&cru SRST_EDP>; 1200724ba675SRob Herring reset-names = "dp"; 1201724ba675SRob Herring rockchip,grf = <&grf>; 1202724ba675SRob Herring status = "disabled"; 1203724ba675SRob Herring 1204724ba675SRob Herring ports { 1205724ba675SRob Herring #address-cells = <1>; 1206724ba675SRob Herring #size-cells = <0>; 1207724ba675SRob Herring 1208724ba675SRob Herring edp_in: port@0 { 1209724ba675SRob Herring reg = <0>; 1210724ba675SRob Herring #address-cells = <1>; 1211724ba675SRob Herring #size-cells = <0>; 1212724ba675SRob Herring 1213724ba675SRob Herring edp_in_vopb: endpoint@0 { 1214724ba675SRob Herring reg = <0>; 1215724ba675SRob Herring remote-endpoint = <&vopb_out_edp>; 1216724ba675SRob Herring }; 1217724ba675SRob Herring 1218724ba675SRob Herring edp_in_vopl: endpoint@1 { 1219724ba675SRob Herring reg = <1>; 1220724ba675SRob Herring remote-endpoint = <&vopl_out_edp>; 1221724ba675SRob Herring }; 1222724ba675SRob Herring }; 1223724ba675SRob Herring 1224724ba675SRob Herring edp_out: port@1 { 1225724ba675SRob Herring reg = <1>; 1226724ba675SRob Herring }; 1227724ba675SRob Herring }; 1228724ba675SRob Herring }; 1229724ba675SRob Herring 1230724ba675SRob Herring hdmi: hdmi@ff980000 { 1231724ba675SRob Herring compatible = "rockchip,rk3288-dw-hdmi"; 1232724ba675SRob Herring reg = <0x0 0xff980000 0x0 0x20000>; 1233724ba675SRob Herring reg-io-width = <4>; 1234724ba675SRob Herring interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1235724ba675SRob Herring clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; 1236724ba675SRob Herring clock-names = "iahb", "isfr", "cec"; 1237724ba675SRob Herring power-domains = <&power RK3288_PD_VIO>; 1238c795042eSJohan Jonker rockchip,grf = <&grf>; 1239c795042eSJohan Jonker #sound-dai-cells = <0>; 1240724ba675SRob Herring status = "disabled"; 1241724ba675SRob Herring 1242724ba675SRob Herring ports { 1243724ba675SRob Herring #address-cells = <1>; 1244724ba675SRob Herring #size-cells = <0>; 1245c795042eSJohan Jonker 1246c795042eSJohan Jonker hdmi_in: port@0 { 1247c795042eSJohan Jonker reg = <0>; 1248c795042eSJohan Jonker #address-cells = <1>; 1249c795042eSJohan Jonker #size-cells = <0>; 1250c795042eSJohan Jonker 1251724ba675SRob Herring hdmi_in_vopb: endpoint@0 { 1252724ba675SRob Herring reg = <0>; 1253724ba675SRob Herring remote-endpoint = <&vopb_out_hdmi>; 1254724ba675SRob Herring }; 1255c795042eSJohan Jonker 1256724ba675SRob Herring hdmi_in_vopl: endpoint@1 { 1257724ba675SRob Herring reg = <1>; 1258724ba675SRob Herring remote-endpoint = <&vopl_out_hdmi>; 1259724ba675SRob Herring }; 1260724ba675SRob Herring }; 1261c795042eSJohan Jonker 1262c795042eSJohan Jonker hdmi_out: port@1 { 1263c795042eSJohan Jonker reg = <1>; 1264c795042eSJohan Jonker }; 1265724ba675SRob Herring }; 1266724ba675SRob Herring }; 1267724ba675SRob Herring 1268724ba675SRob Herring vpu: video-codec@ff9a0000 { 1269724ba675SRob Herring compatible = "rockchip,rk3288-vpu"; 1270724ba675SRob Herring reg = <0x0 0xff9a0000 0x0 0x800>; 1271724ba675SRob Herring interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1272724ba675SRob Herring <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1273724ba675SRob Herring interrupt-names = "vepu", "vdpu"; 1274724ba675SRob Herring clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1275724ba675SRob Herring clock-names = "aclk", "hclk"; 1276724ba675SRob Herring iommus = <&vpu_mmu>; 1277724ba675SRob Herring power-domains = <&power RK3288_PD_VIDEO>; 1278724ba675SRob Herring }; 1279724ba675SRob Herring 1280724ba675SRob Herring vpu_mmu: iommu@ff9a0800 { 1281724ba675SRob Herring compatible = "rockchip,iommu"; 1282724ba675SRob Herring reg = <0x0 0xff9a0800 0x0 0x100>; 1283724ba675SRob Herring interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1284724ba675SRob Herring clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1285724ba675SRob Herring clock-names = "aclk", "iface"; 1286724ba675SRob Herring #iommu-cells = <0>; 1287724ba675SRob Herring power-domains = <&power RK3288_PD_VIDEO>; 1288724ba675SRob Herring }; 1289724ba675SRob Herring 1290724ba675SRob Herring hevc_mmu: iommu@ff9c0440 { 1291724ba675SRob Herring compatible = "rockchip,iommu"; 1292724ba675SRob Herring reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; 1293724ba675SRob Herring interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1294724ba675SRob Herring clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; 1295724ba675SRob Herring clock-names = "aclk", "iface"; 1296724ba675SRob Herring #iommu-cells = <0>; 1297724ba675SRob Herring status = "disabled"; 1298724ba675SRob Herring }; 1299724ba675SRob Herring 1300724ba675SRob Herring gpu: gpu@ffa30000 { 1301724ba675SRob Herring compatible = "rockchip,rk3288-mali", "arm,mali-t760"; 1302724ba675SRob Herring reg = <0x0 0xffa30000 0x0 0x10000>; 1303724ba675SRob Herring interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1304724ba675SRob Herring <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1305724ba675SRob Herring <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1306724ba675SRob Herring interrupt-names = "job", "mmu", "gpu"; 1307724ba675SRob Herring clocks = <&cru ACLK_GPU>; 1308724ba675SRob Herring operating-points-v2 = <&gpu_opp_table>; 1309724ba675SRob Herring #cooling-cells = <2>; /* min followed by max */ 1310724ba675SRob Herring power-domains = <&power RK3288_PD_GPU>; 1311724ba675SRob Herring status = "disabled"; 1312724ba675SRob Herring }; 1313724ba675SRob Herring 1314724ba675SRob Herring gpu_opp_table: opp-table-1 { 1315724ba675SRob Herring compatible = "operating-points-v2"; 1316724ba675SRob Herring 1317724ba675SRob Herring opp-100000000 { 1318724ba675SRob Herring opp-hz = /bits/ 64 <100000000>; 1319724ba675SRob Herring opp-microvolt = <950000>; 1320724ba675SRob Herring }; 1321724ba675SRob Herring opp-200000000 { 1322724ba675SRob Herring opp-hz = /bits/ 64 <200000000>; 1323724ba675SRob Herring opp-microvolt = <950000>; 1324724ba675SRob Herring }; 1325724ba675SRob Herring opp-300000000 { 1326724ba675SRob Herring opp-hz = /bits/ 64 <300000000>; 1327724ba675SRob Herring opp-microvolt = <1000000>; 1328724ba675SRob Herring }; 1329724ba675SRob Herring opp-400000000 { 1330724ba675SRob Herring opp-hz = /bits/ 64 <400000000>; 1331724ba675SRob Herring opp-microvolt = <1100000>; 1332724ba675SRob Herring }; 1333724ba675SRob Herring opp-600000000 { 1334724ba675SRob Herring opp-hz = /bits/ 64 <600000000>; 1335724ba675SRob Herring opp-microvolt = <1250000>; 1336724ba675SRob Herring }; 1337724ba675SRob Herring }; 1338724ba675SRob Herring 1339724ba675SRob Herring qos_gpu_r: qos@ffaa0000 { 1340724ba675SRob Herring compatible = "rockchip,rk3288-qos", "syscon"; 1341724ba675SRob Herring reg = <0x0 0xffaa0000 0x0 0x20>; 1342724ba675SRob Herring }; 1343724ba675SRob Herring 1344724ba675SRob Herring qos_gpu_w: qos@ffaa0080 { 1345724ba675SRob Herring compatible = "rockchip,rk3288-qos", "syscon"; 1346724ba675SRob Herring reg = <0x0 0xffaa0080 0x0 0x20>; 1347724ba675SRob Herring }; 1348724ba675SRob Herring 1349724ba675SRob Herring qos_vio1_vop: qos@ffad0000 { 1350724ba675SRob Herring compatible = "rockchip,rk3288-qos", "syscon"; 1351724ba675SRob Herring reg = <0x0 0xffad0000 0x0 0x20>; 1352724ba675SRob Herring }; 1353724ba675SRob Herring 1354724ba675SRob Herring qos_vio1_isp_w0: qos@ffad0100 { 1355724ba675SRob Herring compatible = "rockchip,rk3288-qos", "syscon"; 1356724ba675SRob Herring reg = <0x0 0xffad0100 0x0 0x20>; 1357724ba675SRob Herring }; 1358724ba675SRob Herring 1359724ba675SRob Herring qos_vio1_isp_w1: qos@ffad0180 { 1360724ba675SRob Herring compatible = "rockchip,rk3288-qos", "syscon"; 1361724ba675SRob Herring reg = <0x0 0xffad0180 0x0 0x20>; 1362724ba675SRob Herring }; 1363724ba675SRob Herring 1364724ba675SRob Herring qos_vio0_vop: qos@ffad0400 { 1365724ba675SRob Herring compatible = "rockchip,rk3288-qos", "syscon"; 1366724ba675SRob Herring reg = <0x0 0xffad0400 0x0 0x20>; 1367724ba675SRob Herring }; 1368724ba675SRob Herring 1369724ba675SRob Herring qos_vio0_vip: qos@ffad0480 { 1370724ba675SRob Herring compatible = "rockchip,rk3288-qos", "syscon"; 1371724ba675SRob Herring reg = <0x0 0xffad0480 0x0 0x20>; 1372724ba675SRob Herring }; 1373724ba675SRob Herring 1374724ba675SRob Herring qos_vio0_iep: qos@ffad0500 { 1375724ba675SRob Herring compatible = "rockchip,rk3288-qos", "syscon"; 1376724ba675SRob Herring reg = <0x0 0xffad0500 0x0 0x20>; 1377724ba675SRob Herring }; 1378724ba675SRob Herring 1379724ba675SRob Herring qos_vio2_rga_r: qos@ffad0800 { 1380724ba675SRob Herring compatible = "rockchip,rk3288-qos", "syscon"; 1381724ba675SRob Herring reg = <0x0 0xffad0800 0x0 0x20>; 1382724ba675SRob Herring }; 1383724ba675SRob Herring 1384724ba675SRob Herring qos_vio2_rga_w: qos@ffad0880 { 1385724ba675SRob Herring compatible = "rockchip,rk3288-qos", "syscon"; 1386724ba675SRob Herring reg = <0x0 0xffad0880 0x0 0x20>; 1387724ba675SRob Herring }; 1388724ba675SRob Herring 1389724ba675SRob Herring qos_vio1_isp_r: qos@ffad0900 { 1390724ba675SRob Herring compatible = "rockchip,rk3288-qos", "syscon"; 1391724ba675SRob Herring reg = <0x0 0xffad0900 0x0 0x20>; 1392724ba675SRob Herring }; 1393724ba675SRob Herring 1394724ba675SRob Herring qos_video: qos@ffae0000 { 1395724ba675SRob Herring compatible = "rockchip,rk3288-qos", "syscon"; 1396724ba675SRob Herring reg = <0x0 0xffae0000 0x0 0x20>; 1397724ba675SRob Herring }; 1398724ba675SRob Herring 1399724ba675SRob Herring qos_hevc_r: qos@ffaf0000 { 1400724ba675SRob Herring compatible = "rockchip,rk3288-qos", "syscon"; 1401724ba675SRob Herring reg = <0x0 0xffaf0000 0x0 0x20>; 1402724ba675SRob Herring }; 1403724ba675SRob Herring 1404724ba675SRob Herring qos_hevc_w: qos@ffaf0080 { 1405724ba675SRob Herring compatible = "rockchip,rk3288-qos", "syscon"; 1406724ba675SRob Herring reg = <0x0 0xffaf0080 0x0 0x20>; 1407724ba675SRob Herring }; 1408724ba675SRob Herring 1409724ba675SRob Herring dmac_bus_s: dma-controller@ffb20000 { 1410724ba675SRob Herring compatible = "arm,pl330", "arm,primecell"; 1411724ba675SRob Herring reg = <0x0 0xffb20000 0x0 0x4000>; 1412724ba675SRob Herring interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1413724ba675SRob Herring <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1414724ba675SRob Herring #dma-cells = <1>; 1415724ba675SRob Herring arm,pl330-broken-no-flushp; 1416724ba675SRob Herring arm,pl330-periph-burst; 1417724ba675SRob Herring clocks = <&cru ACLK_DMAC1>; 1418724ba675SRob Herring clock-names = "apb_pclk"; 1419724ba675SRob Herring }; 1420724ba675SRob Herring 1421724ba675SRob Herring efuse: efuse@ffb40000 { 1422724ba675SRob Herring compatible = "rockchip,rk3288-efuse"; 1423724ba675SRob Herring reg = <0x0 0xffb40000 0x0 0x20>; 1424724ba675SRob Herring #address-cells = <1>; 1425724ba675SRob Herring #size-cells = <1>; 1426724ba675SRob Herring clocks = <&cru PCLK_EFUSE256>; 1427724ba675SRob Herring clock-names = "pclk_efuse"; 1428724ba675SRob Herring 1429724ba675SRob Herring cpu_id: cpu-id@7 { 1430724ba675SRob Herring reg = <0x07 0x10>; 1431724ba675SRob Herring }; 1432724ba675SRob Herring cpu_leakage: cpu_leakage@17 { 1433724ba675SRob Herring reg = <0x17 0x1>; 1434724ba675SRob Herring }; 1435724ba675SRob Herring }; 1436724ba675SRob Herring 1437724ba675SRob Herring gic: interrupt-controller@ffc01000 { 1438724ba675SRob Herring compatible = "arm,gic-400"; 1439724ba675SRob Herring interrupt-controller; 1440724ba675SRob Herring #interrupt-cells = <3>; 1441724ba675SRob Herring #address-cells = <0>; 1442724ba675SRob Herring 1443724ba675SRob Herring reg = <0x0 0xffc01000 0x0 0x1000>, 1444724ba675SRob Herring <0x0 0xffc02000 0x0 0x2000>, 1445724ba675SRob Herring <0x0 0xffc04000 0x0 0x2000>, 1446724ba675SRob Herring <0x0 0xffc06000 0x0 0x2000>; 1447724ba675SRob Herring interrupts = <GIC_PPI 9 0xf04>; 1448724ba675SRob Herring }; 1449724ba675SRob Herring 1450724ba675SRob Herring pinctrl: pinctrl { 1451724ba675SRob Herring compatible = "rockchip,rk3288-pinctrl"; 1452724ba675SRob Herring rockchip,grf = <&grf>; 1453724ba675SRob Herring rockchip,pmu = <&pmu>; 1454724ba675SRob Herring #address-cells = <2>; 1455724ba675SRob Herring #size-cells = <2>; 1456724ba675SRob Herring ranges; 1457724ba675SRob Herring 1458724ba675SRob Herring gpio0: gpio@ff750000 { 1459724ba675SRob Herring compatible = "rockchip,gpio-bank"; 1460724ba675SRob Herring reg = <0x0 0xff750000 0x0 0x100>; 1461724ba675SRob Herring interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1462724ba675SRob Herring clocks = <&cru PCLK_GPIO0>; 1463724ba675SRob Herring 1464724ba675SRob Herring gpio-controller; 1465724ba675SRob Herring #gpio-cells = <2>; 1466724ba675SRob Herring 1467724ba675SRob Herring interrupt-controller; 1468724ba675SRob Herring #interrupt-cells = <2>; 1469724ba675SRob Herring }; 1470724ba675SRob Herring 1471724ba675SRob Herring gpio1: gpio@ff780000 { 1472724ba675SRob Herring compatible = "rockchip,gpio-bank"; 1473724ba675SRob Herring reg = <0x0 0xff780000 0x0 0x100>; 1474724ba675SRob Herring interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1475724ba675SRob Herring clocks = <&cru PCLK_GPIO1>; 1476724ba675SRob Herring 1477724ba675SRob Herring gpio-controller; 1478724ba675SRob Herring #gpio-cells = <2>; 1479724ba675SRob Herring 1480724ba675SRob Herring interrupt-controller; 1481724ba675SRob Herring #interrupt-cells = <2>; 1482724ba675SRob Herring }; 1483724ba675SRob Herring 1484724ba675SRob Herring gpio2: gpio@ff790000 { 1485724ba675SRob Herring compatible = "rockchip,gpio-bank"; 1486724ba675SRob Herring reg = <0x0 0xff790000 0x0 0x100>; 1487724ba675SRob Herring interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1488724ba675SRob Herring clocks = <&cru PCLK_GPIO2>; 1489724ba675SRob Herring 1490724ba675SRob Herring gpio-controller; 1491724ba675SRob Herring #gpio-cells = <2>; 1492724ba675SRob Herring 1493724ba675SRob Herring interrupt-controller; 1494724ba675SRob Herring #interrupt-cells = <2>; 1495724ba675SRob Herring }; 1496724ba675SRob Herring 1497724ba675SRob Herring gpio3: gpio@ff7a0000 { 1498724ba675SRob Herring compatible = "rockchip,gpio-bank"; 1499724ba675SRob Herring reg = <0x0 0xff7a0000 0x0 0x100>; 1500724ba675SRob Herring interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1501724ba675SRob Herring clocks = <&cru PCLK_GPIO3>; 1502724ba675SRob Herring 1503724ba675SRob Herring gpio-controller; 1504724ba675SRob Herring #gpio-cells = <2>; 1505724ba675SRob Herring 1506724ba675SRob Herring interrupt-controller; 1507724ba675SRob Herring #interrupt-cells = <2>; 1508724ba675SRob Herring }; 1509724ba675SRob Herring 1510724ba675SRob Herring gpio4: gpio@ff7b0000 { 1511724ba675SRob Herring compatible = "rockchip,gpio-bank"; 1512724ba675SRob Herring reg = <0x0 0xff7b0000 0x0 0x100>; 1513724ba675SRob Herring interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1514724ba675SRob Herring clocks = <&cru PCLK_GPIO4>; 1515724ba675SRob Herring 1516724ba675SRob Herring gpio-controller; 1517724ba675SRob Herring #gpio-cells = <2>; 1518724ba675SRob Herring 1519724ba675SRob Herring interrupt-controller; 1520724ba675SRob Herring #interrupt-cells = <2>; 1521724ba675SRob Herring }; 1522724ba675SRob Herring 1523724ba675SRob Herring gpio5: gpio@ff7c0000 { 1524724ba675SRob Herring compatible = "rockchip,gpio-bank"; 1525724ba675SRob Herring reg = <0x0 0xff7c0000 0x0 0x100>; 1526724ba675SRob Herring interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1527724ba675SRob Herring clocks = <&cru PCLK_GPIO5>; 1528724ba675SRob Herring 1529724ba675SRob Herring gpio-controller; 1530724ba675SRob Herring #gpio-cells = <2>; 1531724ba675SRob Herring 1532724ba675SRob Herring interrupt-controller; 1533724ba675SRob Herring #interrupt-cells = <2>; 1534724ba675SRob Herring }; 1535724ba675SRob Herring 1536724ba675SRob Herring gpio6: gpio@ff7d0000 { 1537724ba675SRob Herring compatible = "rockchip,gpio-bank"; 1538724ba675SRob Herring reg = <0x0 0xff7d0000 0x0 0x100>; 1539724ba675SRob Herring interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1540724ba675SRob Herring clocks = <&cru PCLK_GPIO6>; 1541724ba675SRob Herring 1542724ba675SRob Herring gpio-controller; 1543724ba675SRob Herring #gpio-cells = <2>; 1544724ba675SRob Herring 1545724ba675SRob Herring interrupt-controller; 1546724ba675SRob Herring #interrupt-cells = <2>; 1547724ba675SRob Herring }; 1548724ba675SRob Herring 1549724ba675SRob Herring gpio7: gpio@ff7e0000 { 1550724ba675SRob Herring compatible = "rockchip,gpio-bank"; 1551724ba675SRob Herring reg = <0x0 0xff7e0000 0x0 0x100>; 1552724ba675SRob Herring interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1553724ba675SRob Herring clocks = <&cru PCLK_GPIO7>; 1554724ba675SRob Herring 1555724ba675SRob Herring gpio-controller; 1556724ba675SRob Herring #gpio-cells = <2>; 1557724ba675SRob Herring 1558724ba675SRob Herring interrupt-controller; 1559724ba675SRob Herring #interrupt-cells = <2>; 1560724ba675SRob Herring }; 1561724ba675SRob Herring 1562724ba675SRob Herring gpio8: gpio@ff7f0000 { 1563724ba675SRob Herring compatible = "rockchip,gpio-bank"; 1564724ba675SRob Herring reg = <0x0 0xff7f0000 0x0 0x100>; 1565724ba675SRob Herring interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1566724ba675SRob Herring clocks = <&cru PCLK_GPIO8>; 1567724ba675SRob Herring 1568724ba675SRob Herring gpio-controller; 1569724ba675SRob Herring #gpio-cells = <2>; 1570724ba675SRob Herring 1571724ba675SRob Herring interrupt-controller; 1572724ba675SRob Herring #interrupt-cells = <2>; 1573724ba675SRob Herring }; 1574724ba675SRob Herring 1575724ba675SRob Herring hdmi { 1576724ba675SRob Herring hdmi_cec_c0: hdmi-cec-c0 { 1577724ba675SRob Herring rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>; 1578724ba675SRob Herring }; 1579724ba675SRob Herring 1580724ba675SRob Herring hdmi_cec_c7: hdmi-cec-c7 { 1581724ba675SRob Herring rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>; 1582724ba675SRob Herring }; 1583724ba675SRob Herring 1584724ba675SRob Herring hdmi_ddc: hdmi-ddc { 1585724ba675SRob Herring rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>, 1586724ba675SRob Herring <7 RK_PC4 2 &pcfg_pull_none>; 1587724ba675SRob Herring }; 1588724ba675SRob Herring 1589724ba675SRob Herring hdmi_ddc_unwedge: hdmi-ddc-unwedge { 1590724ba675SRob Herring rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>, 1591724ba675SRob Herring <7 RK_PC4 2 &pcfg_pull_none>; 1592724ba675SRob Herring }; 1593724ba675SRob Herring }; 1594724ba675SRob Herring 1595724ba675SRob Herring pcfg_output_low: pcfg-output-low { 1596724ba675SRob Herring output-low; 1597724ba675SRob Herring }; 1598724ba675SRob Herring 1599724ba675SRob Herring pcfg_pull_up: pcfg-pull-up { 1600724ba675SRob Herring bias-pull-up; 1601724ba675SRob Herring }; 1602724ba675SRob Herring 1603724ba675SRob Herring pcfg_pull_down: pcfg-pull-down { 1604724ba675SRob Herring bias-pull-down; 1605724ba675SRob Herring }; 1606724ba675SRob Herring 1607724ba675SRob Herring pcfg_pull_none: pcfg-pull-none { 1608724ba675SRob Herring bias-disable; 1609724ba675SRob Herring }; 1610724ba675SRob Herring 1611724ba675SRob Herring pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1612724ba675SRob Herring bias-disable; 1613724ba675SRob Herring drive-strength = <12>; 1614724ba675SRob Herring }; 1615724ba675SRob Herring 1616724ba675SRob Herring suspend { 1617724ba675SRob Herring global_pwroff: global-pwroff { 1618724ba675SRob Herring rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>; 1619724ba675SRob Herring }; 1620724ba675SRob Herring 1621724ba675SRob Herring ddrio_pwroff: ddrio-pwroff { 1622724ba675SRob Herring rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 1623724ba675SRob Herring }; 1624724ba675SRob Herring 1625724ba675SRob Herring ddr0_retention: ddr0-retention { 1626724ba675SRob Herring rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>; 1627724ba675SRob Herring }; 1628724ba675SRob Herring 1629724ba675SRob Herring ddr1_retention: ddr1-retention { 1630724ba675SRob Herring rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; 1631724ba675SRob Herring }; 1632724ba675SRob Herring }; 1633724ba675SRob Herring 1634724ba675SRob Herring edp { 1635724ba675SRob Herring edp_hpd: edp-hpd { 1636724ba675SRob Herring rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>; 1637724ba675SRob Herring }; 1638724ba675SRob Herring }; 1639724ba675SRob Herring 1640724ba675SRob Herring i2c0 { 1641724ba675SRob Herring i2c0_xfer: i2c0-xfer { 1642724ba675SRob Herring rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>, 1643724ba675SRob Herring <0 RK_PC0 1 &pcfg_pull_none>; 1644724ba675SRob Herring }; 1645724ba675SRob Herring }; 1646724ba675SRob Herring 1647724ba675SRob Herring i2c1 { 1648724ba675SRob Herring i2c1_xfer: i2c1-xfer { 1649724ba675SRob Herring rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>, 1650724ba675SRob Herring <8 RK_PA5 1 &pcfg_pull_none>; 1651724ba675SRob Herring }; 1652724ba675SRob Herring }; 1653724ba675SRob Herring 1654724ba675SRob Herring i2c2 { 1655724ba675SRob Herring i2c2_xfer: i2c2-xfer { 1656724ba675SRob Herring rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>, 1657724ba675SRob Herring <6 RK_PB2 1 &pcfg_pull_none>; 1658724ba675SRob Herring }; 1659724ba675SRob Herring }; 1660724ba675SRob Herring 1661724ba675SRob Herring i2c3 { 1662724ba675SRob Herring i2c3_xfer: i2c3-xfer { 1663724ba675SRob Herring rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>, 1664724ba675SRob Herring <2 RK_PC1 1 &pcfg_pull_none>; 1665724ba675SRob Herring }; 1666724ba675SRob Herring }; 1667724ba675SRob Herring 1668724ba675SRob Herring i2c4 { 1669724ba675SRob Herring i2c4_xfer: i2c4-xfer { 1670724ba675SRob Herring rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>, 1671724ba675SRob Herring <7 RK_PC2 1 &pcfg_pull_none>; 1672724ba675SRob Herring }; 1673724ba675SRob Herring }; 1674724ba675SRob Herring 1675724ba675SRob Herring i2c5 { 1676724ba675SRob Herring i2c5_xfer: i2c5-xfer { 1677724ba675SRob Herring rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>, 1678724ba675SRob Herring <7 RK_PC4 1 &pcfg_pull_none>; 1679724ba675SRob Herring }; 1680724ba675SRob Herring }; 1681724ba675SRob Herring 1682724ba675SRob Herring i2s0 { 1683724ba675SRob Herring i2s0_bus: i2s0-bus { 1684724ba675SRob Herring rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>, 1685724ba675SRob Herring <6 RK_PA1 1 &pcfg_pull_none>, 1686724ba675SRob Herring <6 RK_PA2 1 &pcfg_pull_none>, 1687724ba675SRob Herring <6 RK_PA3 1 &pcfg_pull_none>, 1688724ba675SRob Herring <6 RK_PA4 1 &pcfg_pull_none>, 1689724ba675SRob Herring <6 RK_PB0 1 &pcfg_pull_none>; 1690724ba675SRob Herring }; 1691724ba675SRob Herring }; 1692724ba675SRob Herring 1693724ba675SRob Herring lcdc { 1694724ba675SRob Herring lcdc_ctl: lcdc-ctl { 1695724ba675SRob Herring rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 1696724ba675SRob Herring <1 RK_PD1 1 &pcfg_pull_none>, 1697724ba675SRob Herring <1 RK_PD2 1 &pcfg_pull_none>, 1698724ba675SRob Herring <1 RK_PD3 1 &pcfg_pull_none>; 1699724ba675SRob Herring }; 1700724ba675SRob Herring }; 1701724ba675SRob Herring 1702724ba675SRob Herring sdmmc { 1703724ba675SRob Herring sdmmc_clk: sdmmc-clk { 1704724ba675SRob Herring rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>; 1705724ba675SRob Herring }; 1706724ba675SRob Herring 1707724ba675SRob Herring sdmmc_cmd: sdmmc-cmd { 1708724ba675SRob Herring rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>; 1709724ba675SRob Herring }; 1710724ba675SRob Herring 1711724ba675SRob Herring sdmmc_cd: sdmmc-cd { 1712724ba675SRob Herring rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>; 1713724ba675SRob Herring }; 1714724ba675SRob Herring 1715724ba675SRob Herring sdmmc_bus1: sdmmc-bus1 { 1716724ba675SRob Herring rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>; 1717724ba675SRob Herring }; 1718724ba675SRob Herring 1719724ba675SRob Herring sdmmc_bus4: sdmmc-bus4 { 1720724ba675SRob Herring rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>, 1721724ba675SRob Herring <6 RK_PC1 1 &pcfg_pull_up>, 1722724ba675SRob Herring <6 RK_PC2 1 &pcfg_pull_up>, 1723724ba675SRob Herring <6 RK_PC3 1 &pcfg_pull_up>; 1724724ba675SRob Herring }; 1725724ba675SRob Herring }; 1726724ba675SRob Herring 1727724ba675SRob Herring sdio0 { 1728724ba675SRob Herring sdio0_bus1: sdio0-bus1 { 1729724ba675SRob Herring rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>; 1730724ba675SRob Herring }; 1731724ba675SRob Herring 1732724ba675SRob Herring sdio0_bus4: sdio0-bus4 { 1733724ba675SRob Herring rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>, 1734724ba675SRob Herring <4 RK_PC5 1 &pcfg_pull_up>, 1735724ba675SRob Herring <4 RK_PC6 1 &pcfg_pull_up>, 1736724ba675SRob Herring <4 RK_PC7 1 &pcfg_pull_up>; 1737724ba675SRob Herring }; 1738724ba675SRob Herring 1739724ba675SRob Herring sdio0_cmd: sdio0-cmd { 1740724ba675SRob Herring rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>; 1741724ba675SRob Herring }; 1742724ba675SRob Herring 1743724ba675SRob Herring sdio0_clk: sdio0-clk { 1744724ba675SRob Herring rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>; 1745724ba675SRob Herring }; 1746724ba675SRob Herring 1747724ba675SRob Herring sdio0_cd: sdio0-cd { 1748724ba675SRob Herring rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>; 1749724ba675SRob Herring }; 1750724ba675SRob Herring 1751724ba675SRob Herring sdio0_wp: sdio0-wp { 1752724ba675SRob Herring rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>; 1753724ba675SRob Herring }; 1754724ba675SRob Herring 1755724ba675SRob Herring sdio0_pwr: sdio0-pwr { 1756724ba675SRob Herring rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>; 1757724ba675SRob Herring }; 1758724ba675SRob Herring 1759724ba675SRob Herring sdio0_bkpwr: sdio0-bkpwr { 1760724ba675SRob Herring rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>; 1761724ba675SRob Herring }; 1762724ba675SRob Herring 1763724ba675SRob Herring sdio0_int: sdio0-int { 1764724ba675SRob Herring rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>; 1765724ba675SRob Herring }; 1766724ba675SRob Herring }; 1767724ba675SRob Herring 1768724ba675SRob Herring sdio1 { 1769724ba675SRob Herring sdio1_bus1: sdio1-bus1 { 1770724ba675SRob Herring rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>; 1771724ba675SRob Herring }; 1772724ba675SRob Herring 1773724ba675SRob Herring sdio1_bus4: sdio1-bus4 { 1774724ba675SRob Herring rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>, 1775724ba675SRob Herring <3 RK_PD1 4 &pcfg_pull_up>, 1776724ba675SRob Herring <3 RK_PD2 4 &pcfg_pull_up>, 1777724ba675SRob Herring <3 RK_PD3 4 &pcfg_pull_up>; 1778724ba675SRob Herring }; 1779724ba675SRob Herring 1780724ba675SRob Herring sdio1_cd: sdio1-cd { 1781724ba675SRob Herring rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>; 1782724ba675SRob Herring }; 1783724ba675SRob Herring 1784724ba675SRob Herring sdio1_wp: sdio1-wp { 1785724ba675SRob Herring rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>; 1786724ba675SRob Herring }; 1787724ba675SRob Herring 1788724ba675SRob Herring sdio1_bkpwr: sdio1-bkpwr { 1789724ba675SRob Herring rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>; 1790724ba675SRob Herring }; 1791724ba675SRob Herring 1792724ba675SRob Herring sdio1_int: sdio1-int { 1793724ba675SRob Herring rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>; 1794724ba675SRob Herring }; 1795724ba675SRob Herring 1796724ba675SRob Herring sdio1_cmd: sdio1-cmd { 1797724ba675SRob Herring rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>; 1798724ba675SRob Herring }; 1799724ba675SRob Herring 1800724ba675SRob Herring sdio1_clk: sdio1-clk { 1801724ba675SRob Herring rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>; 1802724ba675SRob Herring }; 1803724ba675SRob Herring 1804724ba675SRob Herring sdio1_pwr: sdio1-pwr { 1805724ba675SRob Herring rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>; 1806724ba675SRob Herring }; 1807724ba675SRob Herring }; 1808724ba675SRob Herring 1809724ba675SRob Herring emmc { 1810724ba675SRob Herring emmc_clk: emmc-clk { 1811724ba675SRob Herring rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>; 1812724ba675SRob Herring }; 1813724ba675SRob Herring 1814724ba675SRob Herring emmc_cmd: emmc-cmd { 1815724ba675SRob Herring rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>; 1816724ba675SRob Herring }; 1817724ba675SRob Herring 1818724ba675SRob Herring emmc_pwr: emmc-pwr { 1819724ba675SRob Herring rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>; 1820724ba675SRob Herring }; 1821724ba675SRob Herring 1822724ba675SRob Herring emmc_bus1: emmc-bus1 { 1823724ba675SRob Herring rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>; 1824724ba675SRob Herring }; 1825724ba675SRob Herring 1826724ba675SRob Herring emmc_bus4: emmc-bus4 { 1827724ba675SRob Herring rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, 1828724ba675SRob Herring <3 RK_PA1 2 &pcfg_pull_up>, 1829724ba675SRob Herring <3 RK_PA2 2 &pcfg_pull_up>, 1830724ba675SRob Herring <3 RK_PA3 2 &pcfg_pull_up>; 1831724ba675SRob Herring }; 1832724ba675SRob Herring 1833724ba675SRob Herring emmc_bus8: emmc-bus8 { 1834724ba675SRob Herring rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, 1835724ba675SRob Herring <3 RK_PA1 2 &pcfg_pull_up>, 1836724ba675SRob Herring <3 RK_PA2 2 &pcfg_pull_up>, 1837724ba675SRob Herring <3 RK_PA3 2 &pcfg_pull_up>, 1838724ba675SRob Herring <3 RK_PA4 2 &pcfg_pull_up>, 1839724ba675SRob Herring <3 RK_PA5 2 &pcfg_pull_up>, 1840724ba675SRob Herring <3 RK_PA6 2 &pcfg_pull_up>, 1841724ba675SRob Herring <3 RK_PA7 2 &pcfg_pull_up>; 1842724ba675SRob Herring }; 1843724ba675SRob Herring }; 1844724ba675SRob Herring 1845724ba675SRob Herring spi0 { 1846724ba675SRob Herring spi0_clk: spi0-clk { 1847724ba675SRob Herring rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>; 1848724ba675SRob Herring }; 1849724ba675SRob Herring spi0_cs0: spi0-cs0 { 1850724ba675SRob Herring rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>; 1851724ba675SRob Herring }; 1852724ba675SRob Herring spi0_tx: spi0-tx { 1853724ba675SRob Herring rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>; 1854724ba675SRob Herring }; 1855724ba675SRob Herring spi0_rx: spi0-rx { 1856724ba675SRob Herring rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>; 1857724ba675SRob Herring }; 1858724ba675SRob Herring spi0_cs1: spi0-cs1 { 1859724ba675SRob Herring rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>; 1860724ba675SRob Herring }; 1861724ba675SRob Herring }; 1862724ba675SRob Herring spi1 { 1863724ba675SRob Herring spi1_clk: spi1-clk { 1864724ba675SRob Herring rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>; 1865724ba675SRob Herring }; 1866724ba675SRob Herring spi1_cs0: spi1-cs0 { 1867724ba675SRob Herring rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>; 1868724ba675SRob Herring }; 1869724ba675SRob Herring spi1_rx: spi1-rx { 1870724ba675SRob Herring rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>; 1871724ba675SRob Herring }; 1872724ba675SRob Herring spi1_tx: spi1-tx { 1873724ba675SRob Herring rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>; 1874724ba675SRob Herring }; 1875724ba675SRob Herring }; 1876724ba675SRob Herring 1877724ba675SRob Herring spi2 { 1878724ba675SRob Herring spi2_cs1: spi2-cs1 { 1879724ba675SRob Herring rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>; 1880724ba675SRob Herring }; 1881724ba675SRob Herring spi2_clk: spi2-clk { 1882724ba675SRob Herring rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>; 1883724ba675SRob Herring }; 1884724ba675SRob Herring spi2_cs0: spi2-cs0 { 1885724ba675SRob Herring rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>; 1886724ba675SRob Herring }; 1887724ba675SRob Herring spi2_rx: spi2-rx { 1888724ba675SRob Herring rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>; 1889724ba675SRob Herring }; 1890724ba675SRob Herring spi2_tx: spi2-tx { 1891724ba675SRob Herring rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>; 1892724ba675SRob Herring }; 1893724ba675SRob Herring }; 1894724ba675SRob Herring 1895724ba675SRob Herring uart0 { 1896724ba675SRob Herring uart0_xfer: uart0-xfer { 1897724ba675SRob Herring rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>, 1898724ba675SRob Herring <4 RK_PC1 1 &pcfg_pull_none>; 1899724ba675SRob Herring }; 1900724ba675SRob Herring 1901724ba675SRob Herring uart0_cts: uart0-cts { 1902724ba675SRob Herring rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>; 1903724ba675SRob Herring }; 1904724ba675SRob Herring 1905724ba675SRob Herring uart0_rts: uart0-rts { 1906724ba675SRob Herring rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>; 1907724ba675SRob Herring }; 1908724ba675SRob Herring }; 1909724ba675SRob Herring 1910724ba675SRob Herring uart1 { 1911724ba675SRob Herring uart1_xfer: uart1-xfer { 1912724ba675SRob Herring rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>, 1913724ba675SRob Herring <5 RK_PB1 1 &pcfg_pull_none>; 1914724ba675SRob Herring }; 1915724ba675SRob Herring 1916724ba675SRob Herring uart1_cts: uart1-cts { 1917724ba675SRob Herring rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>; 1918724ba675SRob Herring }; 1919724ba675SRob Herring 1920724ba675SRob Herring uart1_rts: uart1-rts { 1921724ba675SRob Herring rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>; 1922724ba675SRob Herring }; 1923724ba675SRob Herring }; 1924724ba675SRob Herring 1925724ba675SRob Herring uart2 { 1926724ba675SRob Herring uart2_xfer: uart2-xfer { 1927724ba675SRob Herring rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>, 1928724ba675SRob Herring <7 RK_PC7 1 &pcfg_pull_none>; 1929724ba675SRob Herring }; 1930724ba675SRob Herring /* no rts / cts for uart2 */ 1931724ba675SRob Herring }; 1932724ba675SRob Herring 1933724ba675SRob Herring uart3 { 1934724ba675SRob Herring uart3_xfer: uart3-xfer { 1935724ba675SRob Herring rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>, 1936724ba675SRob Herring <7 RK_PB0 1 &pcfg_pull_none>; 1937724ba675SRob Herring }; 1938724ba675SRob Herring 1939724ba675SRob Herring uart3_cts: uart3-cts { 1940724ba675SRob Herring rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>; 1941724ba675SRob Herring }; 1942724ba675SRob Herring 1943724ba675SRob Herring uart3_rts: uart3-rts { 1944724ba675SRob Herring rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>; 1945724ba675SRob Herring }; 1946724ba675SRob Herring }; 1947724ba675SRob Herring 1948724ba675SRob Herring uart4 { 1949724ba675SRob Herring uart4_xfer: uart4-xfer { 1950724ba675SRob Herring rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>, 1951724ba675SRob Herring <5 RK_PB6 3 &pcfg_pull_none>; 1952724ba675SRob Herring }; 1953724ba675SRob Herring 1954724ba675SRob Herring uart4_cts: uart4-cts { 1955724ba675SRob Herring rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>; 1956724ba675SRob Herring }; 1957724ba675SRob Herring 1958724ba675SRob Herring uart4_rts: uart4-rts { 1959724ba675SRob Herring rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>; 1960724ba675SRob Herring }; 1961724ba675SRob Herring }; 1962724ba675SRob Herring 1963724ba675SRob Herring tsadc { 1964724ba675SRob Herring otp_pin: otp-pin { 1965724ba675SRob Herring rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1966724ba675SRob Herring }; 1967724ba675SRob Herring 1968724ba675SRob Herring otp_out: otp-out { 1969724ba675SRob Herring rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>; 1970724ba675SRob Herring }; 1971724ba675SRob Herring }; 1972724ba675SRob Herring 1973724ba675SRob Herring pwm0 { 1974724ba675SRob Herring pwm0_pin: pwm0-pin { 1975724ba675SRob Herring rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>; 1976724ba675SRob Herring }; 1977724ba675SRob Herring }; 1978724ba675SRob Herring 1979724ba675SRob Herring pwm1 { 1980724ba675SRob Herring pwm1_pin: pwm1-pin { 1981724ba675SRob Herring rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>; 1982724ba675SRob Herring }; 1983724ba675SRob Herring }; 1984724ba675SRob Herring 1985724ba675SRob Herring pwm2 { 1986724ba675SRob Herring pwm2_pin: pwm2-pin { 1987724ba675SRob Herring rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>; 1988724ba675SRob Herring }; 1989724ba675SRob Herring }; 1990724ba675SRob Herring 1991724ba675SRob Herring pwm3 { 1992724ba675SRob Herring pwm3_pin: pwm3-pin { 1993724ba675SRob Herring rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>; 1994724ba675SRob Herring }; 1995724ba675SRob Herring }; 1996724ba675SRob Herring 1997724ba675SRob Herring gmac { 1998724ba675SRob Herring rgmii_pins: rgmii-pins { 1999724ba675SRob Herring rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, 2000724ba675SRob Herring <3 RK_PD7 3 &pcfg_pull_none>, 2001724ba675SRob Herring <3 RK_PD2 3 &pcfg_pull_none>, 2002724ba675SRob Herring <3 RK_PD3 3 &pcfg_pull_none>, 2003724ba675SRob Herring <3 RK_PD4 3 &pcfg_pull_none_12ma>, 2004724ba675SRob Herring <3 RK_PD5 3 &pcfg_pull_none_12ma>, 2005724ba675SRob Herring <3 RK_PD0 3 &pcfg_pull_none_12ma>, 2006724ba675SRob Herring <3 RK_PD1 3 &pcfg_pull_none_12ma>, 2007724ba675SRob Herring <4 RK_PA0 3 &pcfg_pull_none>, 2008724ba675SRob Herring <4 RK_PA5 3 &pcfg_pull_none>, 2009724ba675SRob Herring <4 RK_PA6 3 &pcfg_pull_none>, 2010724ba675SRob Herring <4 RK_PB1 3 &pcfg_pull_none_12ma>, 2011724ba675SRob Herring <4 RK_PA4 3 &pcfg_pull_none_12ma>, 2012724ba675SRob Herring <4 RK_PA1 3 &pcfg_pull_none>, 2013724ba675SRob Herring <4 RK_PA3 3 &pcfg_pull_none>; 2014724ba675SRob Herring }; 2015724ba675SRob Herring 2016724ba675SRob Herring rmii_pins: rmii-pins { 2017724ba675SRob Herring rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, 2018724ba675SRob Herring <3 RK_PD7 3 &pcfg_pull_none>, 2019724ba675SRob Herring <3 RK_PD4 3 &pcfg_pull_none>, 2020724ba675SRob Herring <3 RK_PD5 3 &pcfg_pull_none>, 2021724ba675SRob Herring <4 RK_PA0 3 &pcfg_pull_none>, 2022724ba675SRob Herring <4 RK_PA5 3 &pcfg_pull_none>, 2023724ba675SRob Herring <4 RK_PA4 3 &pcfg_pull_none>, 2024724ba675SRob Herring <4 RK_PA1 3 &pcfg_pull_none>, 2025724ba675SRob Herring <4 RK_PA2 3 &pcfg_pull_none>, 2026724ba675SRob Herring <4 RK_PA3 3 &pcfg_pull_none>; 2027724ba675SRob Herring }; 2028724ba675SRob Herring }; 2029724ba675SRob Herring 2030724ba675SRob Herring spdif { 2031724ba675SRob Herring spdif_tx: spdif-tx { 2032724ba675SRob Herring rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>; 2033724ba675SRob Herring }; 2034724ba675SRob Herring }; 2035724ba675SRob Herring }; 2036724ba675SRob Herring}; 2037