1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (c) 2013 MundoReader S.L. 4*724ba675SRob Herring * Author: Heiko Stuebner <heiko@sntech.de> 5*724ba675SRob Herring */ 6*724ba675SRob Herring 7*724ba675SRob Herring#include <dt-bindings/gpio/gpio.h> 8*724ba675SRob Herring#include <dt-bindings/pinctrl/rockchip.h> 9*724ba675SRob Herring#include <dt-bindings/clock/rk3188-cru.h> 10*724ba675SRob Herring#include <dt-bindings/power/rk3188-power.h> 11*724ba675SRob Herring#include "rk3xxx.dtsi" 12*724ba675SRob Herring 13*724ba675SRob Herring/ { 14*724ba675SRob Herring compatible = "rockchip,rk3188"; 15*724ba675SRob Herring 16*724ba675SRob Herring cpus { 17*724ba675SRob Herring #address-cells = <1>; 18*724ba675SRob Herring #size-cells = <0>; 19*724ba675SRob Herring enable-method = "rockchip,rk3066-smp"; 20*724ba675SRob Herring 21*724ba675SRob Herring cpu0: cpu@0 { 22*724ba675SRob Herring device_type = "cpu"; 23*724ba675SRob Herring compatible = "arm,cortex-a9"; 24*724ba675SRob Herring next-level-cache = <&L2>; 25*724ba675SRob Herring reg = <0x0>; 26*724ba675SRob Herring clock-latency = <40000>; 27*724ba675SRob Herring clocks = <&cru ARMCLK>; 28*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 29*724ba675SRob Herring resets = <&cru SRST_CORE0>; 30*724ba675SRob Herring }; 31*724ba675SRob Herring cpu1: cpu@1 { 32*724ba675SRob Herring device_type = "cpu"; 33*724ba675SRob Herring compatible = "arm,cortex-a9"; 34*724ba675SRob Herring next-level-cache = <&L2>; 35*724ba675SRob Herring reg = <0x1>; 36*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 37*724ba675SRob Herring resets = <&cru SRST_CORE1>; 38*724ba675SRob Herring }; 39*724ba675SRob Herring cpu2: cpu@2 { 40*724ba675SRob Herring device_type = "cpu"; 41*724ba675SRob Herring compatible = "arm,cortex-a9"; 42*724ba675SRob Herring next-level-cache = <&L2>; 43*724ba675SRob Herring reg = <0x2>; 44*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 45*724ba675SRob Herring resets = <&cru SRST_CORE2>; 46*724ba675SRob Herring }; 47*724ba675SRob Herring cpu3: cpu@3 { 48*724ba675SRob Herring device_type = "cpu"; 49*724ba675SRob Herring compatible = "arm,cortex-a9"; 50*724ba675SRob Herring next-level-cache = <&L2>; 51*724ba675SRob Herring reg = <0x3>; 52*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 53*724ba675SRob Herring resets = <&cru SRST_CORE3>; 54*724ba675SRob Herring }; 55*724ba675SRob Herring }; 56*724ba675SRob Herring 57*724ba675SRob Herring cpu0_opp_table: opp-table-0 { 58*724ba675SRob Herring compatible = "operating-points-v2"; 59*724ba675SRob Herring opp-shared; 60*724ba675SRob Herring 61*724ba675SRob Herring opp-312000000 { 62*724ba675SRob Herring opp-hz = /bits/ 64 <312000000>; 63*724ba675SRob Herring opp-microvolt = <875000>; 64*724ba675SRob Herring clock-latency-ns = <40000>; 65*724ba675SRob Herring }; 66*724ba675SRob Herring opp-504000000 { 67*724ba675SRob Herring opp-hz = /bits/ 64 <504000000>; 68*724ba675SRob Herring opp-microvolt = <925000>; 69*724ba675SRob Herring }; 70*724ba675SRob Herring opp-600000000 { 71*724ba675SRob Herring opp-hz = /bits/ 64 <600000000>; 72*724ba675SRob Herring opp-microvolt = <950000>; 73*724ba675SRob Herring opp-suspend; 74*724ba675SRob Herring }; 75*724ba675SRob Herring opp-816000000 { 76*724ba675SRob Herring opp-hz = /bits/ 64 <816000000>; 77*724ba675SRob Herring opp-microvolt = <975000>; 78*724ba675SRob Herring }; 79*724ba675SRob Herring opp-1008000000 { 80*724ba675SRob Herring opp-hz = /bits/ 64 <1008000000>; 81*724ba675SRob Herring opp-microvolt = <1075000>; 82*724ba675SRob Herring }; 83*724ba675SRob Herring opp-1200000000 { 84*724ba675SRob Herring opp-hz = /bits/ 64 <1200000000>; 85*724ba675SRob Herring opp-microvolt = <1150000>; 86*724ba675SRob Herring }; 87*724ba675SRob Herring opp-1416000000 { 88*724ba675SRob Herring opp-hz = /bits/ 64 <1416000000>; 89*724ba675SRob Herring opp-microvolt = <1250000>; 90*724ba675SRob Herring }; 91*724ba675SRob Herring opp-1608000000 { 92*724ba675SRob Herring opp-hz = /bits/ 64 <1608000000>; 93*724ba675SRob Herring opp-microvolt = <1350000>; 94*724ba675SRob Herring }; 95*724ba675SRob Herring }; 96*724ba675SRob Herring 97*724ba675SRob Herring display-subsystem { 98*724ba675SRob Herring compatible = "rockchip,display-subsystem"; 99*724ba675SRob Herring ports = <&vop0_out>, <&vop1_out>; 100*724ba675SRob Herring }; 101*724ba675SRob Herring 102*724ba675SRob Herring sram: sram@10080000 { 103*724ba675SRob Herring compatible = "mmio-sram"; 104*724ba675SRob Herring reg = <0x10080000 0x8000>; 105*724ba675SRob Herring #address-cells = <1>; 106*724ba675SRob Herring #size-cells = <1>; 107*724ba675SRob Herring ranges = <0 0x10080000 0x8000>; 108*724ba675SRob Herring 109*724ba675SRob Herring smp-sram@0 { 110*724ba675SRob Herring compatible = "rockchip,rk3066-smp-sram"; 111*724ba675SRob Herring reg = <0x0 0x50>; 112*724ba675SRob Herring }; 113*724ba675SRob Herring }; 114*724ba675SRob Herring 115*724ba675SRob Herring vop0: vop@1010c000 { 116*724ba675SRob Herring compatible = "rockchip,rk3188-vop"; 117*724ba675SRob Herring reg = <0x1010c000 0x1000>; 118*724ba675SRob Herring interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 119*724ba675SRob Herring clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>; 120*724ba675SRob Herring clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 121*724ba675SRob Herring power-domains = <&power RK3188_PD_VIO>; 122*724ba675SRob Herring resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 123*724ba675SRob Herring reset-names = "axi", "ahb", "dclk"; 124*724ba675SRob Herring status = "disabled"; 125*724ba675SRob Herring 126*724ba675SRob Herring vop0_out: port { 127*724ba675SRob Herring #address-cells = <1>; 128*724ba675SRob Herring #size-cells = <0>; 129*724ba675SRob Herring }; 130*724ba675SRob Herring }; 131*724ba675SRob Herring 132*724ba675SRob Herring vop1: vop@1010e000 { 133*724ba675SRob Herring compatible = "rockchip,rk3188-vop"; 134*724ba675SRob Herring reg = <0x1010e000 0x1000>; 135*724ba675SRob Herring interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 136*724ba675SRob Herring clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>; 137*724ba675SRob Herring clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 138*724ba675SRob Herring power-domains = <&power RK3188_PD_VIO>; 139*724ba675SRob Herring resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 140*724ba675SRob Herring reset-names = "axi", "ahb", "dclk"; 141*724ba675SRob Herring status = "disabled"; 142*724ba675SRob Herring 143*724ba675SRob Herring vop1_out: port { 144*724ba675SRob Herring #address-cells = <1>; 145*724ba675SRob Herring #size-cells = <0>; 146*724ba675SRob Herring }; 147*724ba675SRob Herring }; 148*724ba675SRob Herring 149*724ba675SRob Herring timer3: timer@2000e000 { 150*724ba675SRob Herring compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; 151*724ba675SRob Herring reg = <0x2000e000 0x20>; 152*724ba675SRob Herring interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 153*724ba675SRob Herring clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>; 154*724ba675SRob Herring clock-names = "pclk", "timer"; 155*724ba675SRob Herring }; 156*724ba675SRob Herring 157*724ba675SRob Herring timer6: timer@200380a0 { 158*724ba675SRob Herring compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; 159*724ba675SRob Herring reg = <0x200380a0 0x20>; 160*724ba675SRob Herring interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 161*724ba675SRob Herring clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>; 162*724ba675SRob Herring clock-names = "pclk", "timer"; 163*724ba675SRob Herring }; 164*724ba675SRob Herring 165*724ba675SRob Herring i2s0: i2s@1011a000 { 166*724ba675SRob Herring compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; 167*724ba675SRob Herring reg = <0x1011a000 0x2000>; 168*724ba675SRob Herring interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 169*724ba675SRob Herring pinctrl-names = "default"; 170*724ba675SRob Herring pinctrl-0 = <&i2s0_bus>; 171*724ba675SRob Herring clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; 172*724ba675SRob Herring clock-names = "i2s_clk", "i2s_hclk"; 173*724ba675SRob Herring dmas = <&dmac1_s 6>, <&dmac1_s 7>; 174*724ba675SRob Herring dma-names = "tx", "rx"; 175*724ba675SRob Herring rockchip,playback-channels = <2>; 176*724ba675SRob Herring rockchip,capture-channels = <2>; 177*724ba675SRob Herring #sound-dai-cells = <0>; 178*724ba675SRob Herring status = "disabled"; 179*724ba675SRob Herring }; 180*724ba675SRob Herring 181*724ba675SRob Herring spdif: sound@1011e000 { 182*724ba675SRob Herring compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; 183*724ba675SRob Herring reg = <0x1011e000 0x2000>; 184*724ba675SRob Herring #sound-dai-cells = <0>; 185*724ba675SRob Herring clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; 186*724ba675SRob Herring clock-names = "mclk", "hclk"; 187*724ba675SRob Herring dmas = <&dmac1_s 8>; 188*724ba675SRob Herring dma-names = "tx"; 189*724ba675SRob Herring interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 190*724ba675SRob Herring pinctrl-names = "default"; 191*724ba675SRob Herring pinctrl-0 = <&spdif_tx>; 192*724ba675SRob Herring status = "disabled"; 193*724ba675SRob Herring }; 194*724ba675SRob Herring 195*724ba675SRob Herring cru: clock-controller@20000000 { 196*724ba675SRob Herring compatible = "rockchip,rk3188-cru"; 197*724ba675SRob Herring reg = <0x20000000 0x1000>; 198*724ba675SRob Herring clocks = <&xin24m>; 199*724ba675SRob Herring clock-names = "xin24m"; 200*724ba675SRob Herring rockchip,grf = <&grf>; 201*724ba675SRob Herring #clock-cells = <1>; 202*724ba675SRob Herring #reset-cells = <1>; 203*724ba675SRob Herring }; 204*724ba675SRob Herring 205*724ba675SRob Herring efuse: efuse@20010000 { 206*724ba675SRob Herring compatible = "rockchip,rk3188-efuse"; 207*724ba675SRob Herring reg = <0x20010000 0x4000>; 208*724ba675SRob Herring #address-cells = <1>; 209*724ba675SRob Herring #size-cells = <1>; 210*724ba675SRob Herring clocks = <&cru PCLK_EFUSE>; 211*724ba675SRob Herring clock-names = "pclk_efuse"; 212*724ba675SRob Herring 213*724ba675SRob Herring cpu_leakage: cpu_leakage@17 { 214*724ba675SRob Herring reg = <0x17 0x1>; 215*724ba675SRob Herring }; 216*724ba675SRob Herring }; 217*724ba675SRob Herring 218*724ba675SRob Herring pinctrl: pinctrl { 219*724ba675SRob Herring compatible = "rockchip,rk3188-pinctrl"; 220*724ba675SRob Herring rockchip,grf = <&grf>; 221*724ba675SRob Herring rockchip,pmu = <&pmu>; 222*724ba675SRob Herring 223*724ba675SRob Herring #address-cells = <1>; 224*724ba675SRob Herring #size-cells = <1>; 225*724ba675SRob Herring ranges; 226*724ba675SRob Herring 227*724ba675SRob Herring gpio0: gpio@2000a000 { 228*724ba675SRob Herring compatible = "rockchip,rk3188-gpio-bank0"; 229*724ba675SRob Herring reg = <0x2000a000 0x100>; 230*724ba675SRob Herring interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 231*724ba675SRob Herring clocks = <&cru PCLK_GPIO0>; 232*724ba675SRob Herring 233*724ba675SRob Herring gpio-controller; 234*724ba675SRob Herring #gpio-cells = <2>; 235*724ba675SRob Herring 236*724ba675SRob Herring interrupt-controller; 237*724ba675SRob Herring #interrupt-cells = <2>; 238*724ba675SRob Herring }; 239*724ba675SRob Herring 240*724ba675SRob Herring gpio1: gpio@2003c000 { 241*724ba675SRob Herring compatible = "rockchip,gpio-bank"; 242*724ba675SRob Herring reg = <0x2003c000 0x100>; 243*724ba675SRob Herring interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 244*724ba675SRob Herring clocks = <&cru PCLK_GPIO1>; 245*724ba675SRob Herring 246*724ba675SRob Herring gpio-controller; 247*724ba675SRob Herring #gpio-cells = <2>; 248*724ba675SRob Herring 249*724ba675SRob Herring interrupt-controller; 250*724ba675SRob Herring #interrupt-cells = <2>; 251*724ba675SRob Herring }; 252*724ba675SRob Herring 253*724ba675SRob Herring gpio2: gpio@2003e000 { 254*724ba675SRob Herring compatible = "rockchip,gpio-bank"; 255*724ba675SRob Herring reg = <0x2003e000 0x100>; 256*724ba675SRob Herring interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 257*724ba675SRob Herring clocks = <&cru PCLK_GPIO2>; 258*724ba675SRob Herring 259*724ba675SRob Herring gpio-controller; 260*724ba675SRob Herring #gpio-cells = <2>; 261*724ba675SRob Herring 262*724ba675SRob Herring interrupt-controller; 263*724ba675SRob Herring #interrupt-cells = <2>; 264*724ba675SRob Herring }; 265*724ba675SRob Herring 266*724ba675SRob Herring gpio3: gpio@20080000 { 267*724ba675SRob Herring compatible = "rockchip,gpio-bank"; 268*724ba675SRob Herring reg = <0x20080000 0x100>; 269*724ba675SRob Herring interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 270*724ba675SRob Herring clocks = <&cru PCLK_GPIO3>; 271*724ba675SRob Herring 272*724ba675SRob Herring gpio-controller; 273*724ba675SRob Herring #gpio-cells = <2>; 274*724ba675SRob Herring 275*724ba675SRob Herring interrupt-controller; 276*724ba675SRob Herring #interrupt-cells = <2>; 277*724ba675SRob Herring }; 278*724ba675SRob Herring 279*724ba675SRob Herring pcfg_pull_up: pcfg-pull-up { 280*724ba675SRob Herring bias-pull-up; 281*724ba675SRob Herring }; 282*724ba675SRob Herring 283*724ba675SRob Herring pcfg_pull_down: pcfg-pull-down { 284*724ba675SRob Herring bias-pull-down; 285*724ba675SRob Herring }; 286*724ba675SRob Herring 287*724ba675SRob Herring pcfg_pull_none: pcfg-pull-none { 288*724ba675SRob Herring bias-disable; 289*724ba675SRob Herring }; 290*724ba675SRob Herring 291*724ba675SRob Herring emmc { 292*724ba675SRob Herring emmc_clk: emmc-clk { 293*724ba675SRob Herring rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; 294*724ba675SRob Herring }; 295*724ba675SRob Herring 296*724ba675SRob Herring emmc_cmd: emmc-cmd { 297*724ba675SRob Herring rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>; 298*724ba675SRob Herring }; 299*724ba675SRob Herring 300*724ba675SRob Herring emmc_rst: emmc-rst { 301*724ba675SRob Herring rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>; 302*724ba675SRob Herring }; 303*724ba675SRob Herring 304*724ba675SRob Herring /* 305*724ba675SRob Herring * The data pins are shared between nandc and emmc and 306*724ba675SRob Herring * not accessible through pinctrl. Also they should've 307*724ba675SRob Herring * been already set correctly by firmware, as 308*724ba675SRob Herring * flash/emmc is the boot-device. 309*724ba675SRob Herring */ 310*724ba675SRob Herring }; 311*724ba675SRob Herring 312*724ba675SRob Herring emac { 313*724ba675SRob Herring emac_xfer: emac-xfer { 314*724ba675SRob Herring rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */ 315*724ba675SRob Herring <3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */ 316*724ba675SRob Herring <3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */ 317*724ba675SRob Herring <3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */ 318*724ba675SRob Herring <3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */ 319*724ba675SRob Herring <3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */ 320*724ba675SRob Herring <3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */ 321*724ba675SRob Herring <3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */ 322*724ba675SRob Herring }; 323*724ba675SRob Herring 324*724ba675SRob Herring emac_mdio: emac-mdio { 325*724ba675SRob Herring rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, 326*724ba675SRob Herring <3 RK_PD1 2 &pcfg_pull_none>; 327*724ba675SRob Herring }; 328*724ba675SRob Herring }; 329*724ba675SRob Herring 330*724ba675SRob Herring i2c0 { 331*724ba675SRob Herring i2c0_xfer: i2c0-xfer { 332*724ba675SRob Herring rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 333*724ba675SRob Herring <1 RK_PD1 1 &pcfg_pull_none>; 334*724ba675SRob Herring }; 335*724ba675SRob Herring }; 336*724ba675SRob Herring 337*724ba675SRob Herring i2c1 { 338*724ba675SRob Herring i2c1_xfer: i2c1-xfer { 339*724ba675SRob Herring rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>, 340*724ba675SRob Herring <1 RK_PD3 1 &pcfg_pull_none>; 341*724ba675SRob Herring }; 342*724ba675SRob Herring }; 343*724ba675SRob Herring 344*724ba675SRob Herring i2c2 { 345*724ba675SRob Herring i2c2_xfer: i2c2-xfer { 346*724ba675SRob Herring rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>, 347*724ba675SRob Herring <1 RK_PD5 1 &pcfg_pull_none>; 348*724ba675SRob Herring }; 349*724ba675SRob Herring }; 350*724ba675SRob Herring 351*724ba675SRob Herring i2c3 { 352*724ba675SRob Herring i2c3_xfer: i2c3-xfer { 353*724ba675SRob Herring rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>, 354*724ba675SRob Herring <3 RK_PB7 2 &pcfg_pull_none>; 355*724ba675SRob Herring }; 356*724ba675SRob Herring }; 357*724ba675SRob Herring 358*724ba675SRob Herring i2c4 { 359*724ba675SRob Herring i2c4_xfer: i2c4-xfer { 360*724ba675SRob Herring rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>, 361*724ba675SRob Herring <1 RK_PD7 1 &pcfg_pull_none>; 362*724ba675SRob Herring }; 363*724ba675SRob Herring }; 364*724ba675SRob Herring 365*724ba675SRob Herring lcdc1 { 366*724ba675SRob Herring lcdc1_dclk: lcdc1-dclk { 367*724ba675SRob Herring rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>; 368*724ba675SRob Herring }; 369*724ba675SRob Herring 370*724ba675SRob Herring lcdc1_den: lcdc1-den { 371*724ba675SRob Herring rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>; 372*724ba675SRob Herring }; 373*724ba675SRob Herring 374*724ba675SRob Herring lcdc1_hsync: lcdc1-hsync { 375*724ba675SRob Herring rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; 376*724ba675SRob Herring }; 377*724ba675SRob Herring 378*724ba675SRob Herring lcdc1_vsync: lcdc1-vsync { 379*724ba675SRob Herring rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; 380*724ba675SRob Herring }; 381*724ba675SRob Herring 382*724ba675SRob Herring lcdc1_rgb24: lcdc1-rgb24 { 383*724ba675SRob Herring rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, 384*724ba675SRob Herring <2 RK_PA1 1 &pcfg_pull_none>, 385*724ba675SRob Herring <2 RK_PA2 1 &pcfg_pull_none>, 386*724ba675SRob Herring <2 RK_PA3 1 &pcfg_pull_none>, 387*724ba675SRob Herring <2 RK_PA4 1 &pcfg_pull_none>, 388*724ba675SRob Herring <2 RK_PA5 1 &pcfg_pull_none>, 389*724ba675SRob Herring <2 RK_PA6 1 &pcfg_pull_none>, 390*724ba675SRob Herring <2 RK_PA7 1 &pcfg_pull_none>, 391*724ba675SRob Herring <2 RK_PB0 1 &pcfg_pull_none>, 392*724ba675SRob Herring <2 RK_PB1 1 &pcfg_pull_none>, 393*724ba675SRob Herring <2 RK_PB2 1 &pcfg_pull_none>, 394*724ba675SRob Herring <2 RK_PB3 1 &pcfg_pull_none>, 395*724ba675SRob Herring <2 RK_PB4 1 &pcfg_pull_none>, 396*724ba675SRob Herring <2 RK_PB5 1 &pcfg_pull_none>, 397*724ba675SRob Herring <2 RK_PB6 1 &pcfg_pull_none>, 398*724ba675SRob Herring <2 RK_PB7 1 &pcfg_pull_none>, 399*724ba675SRob Herring <2 RK_PC0 1 &pcfg_pull_none>, 400*724ba675SRob Herring <2 RK_PC1 1 &pcfg_pull_none>, 401*724ba675SRob Herring <2 RK_PC2 1 &pcfg_pull_none>, 402*724ba675SRob Herring <2 RK_PC3 1 &pcfg_pull_none>, 403*724ba675SRob Herring <2 RK_PC4 1 &pcfg_pull_none>, 404*724ba675SRob Herring <2 RK_PC5 1 &pcfg_pull_none>, 405*724ba675SRob Herring <2 RK_PC6 1 &pcfg_pull_none>, 406*724ba675SRob Herring <2 RK_PC7 1 &pcfg_pull_none>; 407*724ba675SRob Herring }; 408*724ba675SRob Herring }; 409*724ba675SRob Herring 410*724ba675SRob Herring pwm0 { 411*724ba675SRob Herring pwm0_out: pwm0-out { 412*724ba675SRob Herring rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 413*724ba675SRob Herring }; 414*724ba675SRob Herring }; 415*724ba675SRob Herring 416*724ba675SRob Herring pwm1 { 417*724ba675SRob Herring pwm1_out: pwm1-out { 418*724ba675SRob Herring rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>; 419*724ba675SRob Herring }; 420*724ba675SRob Herring }; 421*724ba675SRob Herring 422*724ba675SRob Herring pwm2 { 423*724ba675SRob Herring pwm2_out: pwm2-out { 424*724ba675SRob Herring rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>; 425*724ba675SRob Herring }; 426*724ba675SRob Herring }; 427*724ba675SRob Herring 428*724ba675SRob Herring pwm3 { 429*724ba675SRob Herring pwm3_out: pwm3-out { 430*724ba675SRob Herring rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>; 431*724ba675SRob Herring }; 432*724ba675SRob Herring }; 433*724ba675SRob Herring 434*724ba675SRob Herring spi0 { 435*724ba675SRob Herring spi0_clk: spi0-clk { 436*724ba675SRob Herring rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>; 437*724ba675SRob Herring }; 438*724ba675SRob Herring spi0_cs0: spi0-cs0 { 439*724ba675SRob Herring rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>; 440*724ba675SRob Herring }; 441*724ba675SRob Herring spi0_tx: spi0-tx { 442*724ba675SRob Herring rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>; 443*724ba675SRob Herring }; 444*724ba675SRob Herring spi0_rx: spi0-rx { 445*724ba675SRob Herring rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>; 446*724ba675SRob Herring }; 447*724ba675SRob Herring spi0_cs1: spi0-cs1 { 448*724ba675SRob Herring rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>; 449*724ba675SRob Herring }; 450*724ba675SRob Herring }; 451*724ba675SRob Herring 452*724ba675SRob Herring spi1 { 453*724ba675SRob Herring spi1_clk: spi1-clk { 454*724ba675SRob Herring rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>; 455*724ba675SRob Herring }; 456*724ba675SRob Herring spi1_cs0: spi1-cs0 { 457*724ba675SRob Herring rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>; 458*724ba675SRob Herring }; 459*724ba675SRob Herring spi1_rx: spi1-rx { 460*724ba675SRob Herring rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>; 461*724ba675SRob Herring }; 462*724ba675SRob Herring spi1_tx: spi1-tx { 463*724ba675SRob Herring rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>; 464*724ba675SRob Herring }; 465*724ba675SRob Herring spi1_cs1: spi1-cs1 { 466*724ba675SRob Herring rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; 467*724ba675SRob Herring }; 468*724ba675SRob Herring }; 469*724ba675SRob Herring 470*724ba675SRob Herring uart0 { 471*724ba675SRob Herring uart0_xfer: uart0-xfer { 472*724ba675SRob Herring rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>, 473*724ba675SRob Herring <1 RK_PA1 1 &pcfg_pull_none>; 474*724ba675SRob Herring }; 475*724ba675SRob Herring 476*724ba675SRob Herring uart0_cts: uart0-cts { 477*724ba675SRob Herring rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>; 478*724ba675SRob Herring }; 479*724ba675SRob Herring 480*724ba675SRob Herring uart0_rts: uart0-rts { 481*724ba675SRob Herring rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>; 482*724ba675SRob Herring }; 483*724ba675SRob Herring }; 484*724ba675SRob Herring 485*724ba675SRob Herring uart1 { 486*724ba675SRob Herring uart1_xfer: uart1-xfer { 487*724ba675SRob Herring rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>, 488*724ba675SRob Herring <1 RK_PA5 1 &pcfg_pull_none>; 489*724ba675SRob Herring }; 490*724ba675SRob Herring 491*724ba675SRob Herring uart1_cts: uart1-cts { 492*724ba675SRob Herring rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 493*724ba675SRob Herring }; 494*724ba675SRob Herring 495*724ba675SRob Herring uart1_rts: uart1-rts { 496*724ba675SRob Herring rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>; 497*724ba675SRob Herring }; 498*724ba675SRob Herring }; 499*724ba675SRob Herring 500*724ba675SRob Herring uart2 { 501*724ba675SRob Herring uart2_xfer: uart2-xfer { 502*724ba675SRob Herring rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>, 503*724ba675SRob Herring <1 RK_PB1 1 &pcfg_pull_none>; 504*724ba675SRob Herring }; 505*724ba675SRob Herring /* no rts / cts for uart2 */ 506*724ba675SRob Herring }; 507*724ba675SRob Herring 508*724ba675SRob Herring uart3 { 509*724ba675SRob Herring uart3_xfer: uart3-xfer { 510*724ba675SRob Herring rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>, 511*724ba675SRob Herring <1 RK_PB3 1 &pcfg_pull_none>; 512*724ba675SRob Herring }; 513*724ba675SRob Herring 514*724ba675SRob Herring uart3_cts: uart3-cts { 515*724ba675SRob Herring rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>; 516*724ba675SRob Herring }; 517*724ba675SRob Herring 518*724ba675SRob Herring uart3_rts: uart3-rts { 519*724ba675SRob Herring rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>; 520*724ba675SRob Herring }; 521*724ba675SRob Herring }; 522*724ba675SRob Herring 523*724ba675SRob Herring sd0 { 524*724ba675SRob Herring sd0_clk: sd0-clk { 525*724ba675SRob Herring rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>; 526*724ba675SRob Herring }; 527*724ba675SRob Herring 528*724ba675SRob Herring sd0_cmd: sd0-cmd { 529*724ba675SRob Herring rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; 530*724ba675SRob Herring }; 531*724ba675SRob Herring 532*724ba675SRob Herring sd0_cd: sd0-cd { 533*724ba675SRob Herring rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>; 534*724ba675SRob Herring }; 535*724ba675SRob Herring 536*724ba675SRob Herring sd0_wp: sd0-wp { 537*724ba675SRob Herring rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>; 538*724ba675SRob Herring }; 539*724ba675SRob Herring 540*724ba675SRob Herring sd0_pwr: sd0-pwr { 541*724ba675SRob Herring rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; 542*724ba675SRob Herring }; 543*724ba675SRob Herring 544*724ba675SRob Herring sd0_bus1: sd0-bus-width1 { 545*724ba675SRob Herring rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; 546*724ba675SRob Herring }; 547*724ba675SRob Herring 548*724ba675SRob Herring sd0_bus4: sd0-bus-width4 { 549*724ba675SRob Herring rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, 550*724ba675SRob Herring <3 RK_PA5 1 &pcfg_pull_none>, 551*724ba675SRob Herring <3 RK_PA6 1 &pcfg_pull_none>, 552*724ba675SRob Herring <3 RK_PA7 1 &pcfg_pull_none>; 553*724ba675SRob Herring }; 554*724ba675SRob Herring }; 555*724ba675SRob Herring 556*724ba675SRob Herring sd1 { 557*724ba675SRob Herring sd1_clk: sd1-clk { 558*724ba675SRob Herring rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; 559*724ba675SRob Herring }; 560*724ba675SRob Herring 561*724ba675SRob Herring sd1_cmd: sd1-cmd { 562*724ba675SRob Herring rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>; 563*724ba675SRob Herring }; 564*724ba675SRob Herring 565*724ba675SRob Herring sd1_cd: sd1-cd { 566*724ba675SRob Herring rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>; 567*724ba675SRob Herring }; 568*724ba675SRob Herring 569*724ba675SRob Herring sd1_wp: sd1-wp { 570*724ba675SRob Herring rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>; 571*724ba675SRob Herring }; 572*724ba675SRob Herring 573*724ba675SRob Herring sd1_bus1: sd1-bus-width1 { 574*724ba675SRob Herring rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>; 575*724ba675SRob Herring }; 576*724ba675SRob Herring 577*724ba675SRob Herring sd1_bus4: sd1-bus-width4 { 578*724ba675SRob Herring rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>, 579*724ba675SRob Herring <3 RK_PC2 1 &pcfg_pull_none>, 580*724ba675SRob Herring <3 RK_PC3 1 &pcfg_pull_none>, 581*724ba675SRob Herring <3 RK_PC4 1 &pcfg_pull_none>; 582*724ba675SRob Herring }; 583*724ba675SRob Herring }; 584*724ba675SRob Herring 585*724ba675SRob Herring i2s0 { 586*724ba675SRob Herring i2s0_bus: i2s0-bus { 587*724ba675SRob Herring rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, 588*724ba675SRob Herring <1 RK_PC1 1 &pcfg_pull_none>, 589*724ba675SRob Herring <1 RK_PC2 1 &pcfg_pull_none>, 590*724ba675SRob Herring <1 RK_PC3 1 &pcfg_pull_none>, 591*724ba675SRob Herring <1 RK_PC4 1 &pcfg_pull_none>, 592*724ba675SRob Herring <1 RK_PC5 1 &pcfg_pull_none>; 593*724ba675SRob Herring }; 594*724ba675SRob Herring }; 595*724ba675SRob Herring 596*724ba675SRob Herring spdif { 597*724ba675SRob Herring spdif_tx: spdif-tx { 598*724ba675SRob Herring rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>; 599*724ba675SRob Herring }; 600*724ba675SRob Herring }; 601*724ba675SRob Herring }; 602*724ba675SRob Herring}; 603*724ba675SRob Herring 604*724ba675SRob Herring&emac { 605*724ba675SRob Herring compatible = "rockchip,rk3188-emac"; 606*724ba675SRob Herring}; 607*724ba675SRob Herring 608*724ba675SRob Herring&global_timer { 609*724ba675SRob Herring interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 610*724ba675SRob Herring}; 611*724ba675SRob Herring 612*724ba675SRob Herring&local_timer { 613*724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 614*724ba675SRob Herring}; 615*724ba675SRob Herring 616*724ba675SRob Herring&gpu { 617*724ba675SRob Herring compatible = "rockchip,rk3188-mali", "arm,mali-400"; 618*724ba675SRob Herring interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 619*724ba675SRob Herring <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 620*724ba675SRob Herring <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 621*724ba675SRob Herring <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 622*724ba675SRob Herring <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 623*724ba675SRob Herring <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 624*724ba675SRob Herring <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 625*724ba675SRob Herring <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 626*724ba675SRob Herring <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 627*724ba675SRob Herring <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 628*724ba675SRob Herring interrupt-names = "gp", 629*724ba675SRob Herring "gpmmu", 630*724ba675SRob Herring "pp0", 631*724ba675SRob Herring "ppmmu0", 632*724ba675SRob Herring "pp1", 633*724ba675SRob Herring "ppmmu1", 634*724ba675SRob Herring "pp2", 635*724ba675SRob Herring "ppmmu2", 636*724ba675SRob Herring "pp3", 637*724ba675SRob Herring "ppmmu3"; 638*724ba675SRob Herring power-domains = <&power RK3188_PD_GPU>; 639*724ba675SRob Herring}; 640*724ba675SRob Herring 641*724ba675SRob Herring&grf { 642*724ba675SRob Herring compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd"; 643*724ba675SRob Herring 644*724ba675SRob Herring io_domains: io-domains { 645*724ba675SRob Herring compatible = "rockchip,rk3188-io-voltage-domain"; 646*724ba675SRob Herring status = "disabled"; 647*724ba675SRob Herring }; 648*724ba675SRob Herring 649*724ba675SRob Herring usbphy: usbphy { 650*724ba675SRob Herring compatible = "rockchip,rk3188-usb-phy"; 651*724ba675SRob Herring #address-cells = <1>; 652*724ba675SRob Herring #size-cells = <0>; 653*724ba675SRob Herring status = "disabled"; 654*724ba675SRob Herring 655*724ba675SRob Herring usbphy0: usb-phy@10c { 656*724ba675SRob Herring reg = <0x10c>; 657*724ba675SRob Herring clocks = <&cru SCLK_OTGPHY0>; 658*724ba675SRob Herring clock-names = "phyclk"; 659*724ba675SRob Herring #clock-cells = <0>; 660*724ba675SRob Herring #phy-cells = <0>; 661*724ba675SRob Herring }; 662*724ba675SRob Herring 663*724ba675SRob Herring usbphy1: usb-phy@11c { 664*724ba675SRob Herring reg = <0x11c>; 665*724ba675SRob Herring clocks = <&cru SCLK_OTGPHY1>; 666*724ba675SRob Herring clock-names = "phyclk"; 667*724ba675SRob Herring #clock-cells = <0>; 668*724ba675SRob Herring #phy-cells = <0>; 669*724ba675SRob Herring }; 670*724ba675SRob Herring }; 671*724ba675SRob Herring}; 672*724ba675SRob Herring 673*724ba675SRob Herring&i2c0 { 674*724ba675SRob Herring compatible = "rockchip,rk3188-i2c"; 675*724ba675SRob Herring pinctrl-names = "default"; 676*724ba675SRob Herring pinctrl-0 = <&i2c0_xfer>; 677*724ba675SRob Herring}; 678*724ba675SRob Herring 679*724ba675SRob Herring&i2c1 { 680*724ba675SRob Herring compatible = "rockchip,rk3188-i2c"; 681*724ba675SRob Herring pinctrl-names = "default"; 682*724ba675SRob Herring pinctrl-0 = <&i2c1_xfer>; 683*724ba675SRob Herring}; 684*724ba675SRob Herring 685*724ba675SRob Herring&i2c2 { 686*724ba675SRob Herring compatible = "rockchip,rk3188-i2c"; 687*724ba675SRob Herring pinctrl-names = "default"; 688*724ba675SRob Herring pinctrl-0 = <&i2c2_xfer>; 689*724ba675SRob Herring}; 690*724ba675SRob Herring 691*724ba675SRob Herring&i2c3 { 692*724ba675SRob Herring compatible = "rockchip,rk3188-i2c"; 693*724ba675SRob Herring pinctrl-names = "default"; 694*724ba675SRob Herring pinctrl-0 = <&i2c3_xfer>; 695*724ba675SRob Herring}; 696*724ba675SRob Herring 697*724ba675SRob Herring&i2c4 { 698*724ba675SRob Herring compatible = "rockchip,rk3188-i2c"; 699*724ba675SRob Herring pinctrl-names = "default"; 700*724ba675SRob Herring pinctrl-0 = <&i2c4_xfer>; 701*724ba675SRob Herring}; 702*724ba675SRob Herring 703*724ba675SRob Herring&pmu { 704*724ba675SRob Herring power: power-controller { 705*724ba675SRob Herring compatible = "rockchip,rk3188-power-controller"; 706*724ba675SRob Herring #power-domain-cells = <1>; 707*724ba675SRob Herring #address-cells = <1>; 708*724ba675SRob Herring #size-cells = <0>; 709*724ba675SRob Herring 710*724ba675SRob Herring power-domain@RK3188_PD_VIO { 711*724ba675SRob Herring reg = <RK3188_PD_VIO>; 712*724ba675SRob Herring clocks = <&cru ACLK_LCDC0>, 713*724ba675SRob Herring <&cru ACLK_LCDC1>, 714*724ba675SRob Herring <&cru DCLK_LCDC0>, 715*724ba675SRob Herring <&cru DCLK_LCDC1>, 716*724ba675SRob Herring <&cru HCLK_LCDC0>, 717*724ba675SRob Herring <&cru HCLK_LCDC1>, 718*724ba675SRob Herring <&cru SCLK_CIF0>, 719*724ba675SRob Herring <&cru ACLK_CIF0>, 720*724ba675SRob Herring <&cru HCLK_CIF0>, 721*724ba675SRob Herring <&cru ACLK_IPP>, 722*724ba675SRob Herring <&cru HCLK_IPP>, 723*724ba675SRob Herring <&cru ACLK_RGA>, 724*724ba675SRob Herring <&cru HCLK_RGA>; 725*724ba675SRob Herring pm_qos = <&qos_lcdc0>, 726*724ba675SRob Herring <&qos_lcdc1>, 727*724ba675SRob Herring <&qos_cif0>, 728*724ba675SRob Herring <&qos_ipp>, 729*724ba675SRob Herring <&qos_rga>; 730*724ba675SRob Herring #power-domain-cells = <0>; 731*724ba675SRob Herring }; 732*724ba675SRob Herring 733*724ba675SRob Herring power-domain@RK3188_PD_VIDEO { 734*724ba675SRob Herring reg = <RK3188_PD_VIDEO>; 735*724ba675SRob Herring clocks = <&cru ACLK_VDPU>, 736*724ba675SRob Herring <&cru ACLK_VEPU>, 737*724ba675SRob Herring <&cru HCLK_VDPU>, 738*724ba675SRob Herring <&cru HCLK_VEPU>; 739*724ba675SRob Herring pm_qos = <&qos_vpu>; 740*724ba675SRob Herring #power-domain-cells = <0>; 741*724ba675SRob Herring }; 742*724ba675SRob Herring 743*724ba675SRob Herring power-domain@RK3188_PD_GPU { 744*724ba675SRob Herring reg = <RK3188_PD_GPU>; 745*724ba675SRob Herring clocks = <&cru ACLK_GPU>; 746*724ba675SRob Herring pm_qos = <&qos_gpu>; 747*724ba675SRob Herring #power-domain-cells = <0>; 748*724ba675SRob Herring }; 749*724ba675SRob Herring }; 750*724ba675SRob Herring}; 751*724ba675SRob Herring 752*724ba675SRob Herring&pwm0 { 753*724ba675SRob Herring pinctrl-names = "default"; 754*724ba675SRob Herring pinctrl-0 = <&pwm0_out>; 755*724ba675SRob Herring}; 756*724ba675SRob Herring 757*724ba675SRob Herring&pwm1 { 758*724ba675SRob Herring pinctrl-names = "default"; 759*724ba675SRob Herring pinctrl-0 = <&pwm1_out>; 760*724ba675SRob Herring}; 761*724ba675SRob Herring 762*724ba675SRob Herring&pwm2 { 763*724ba675SRob Herring pinctrl-names = "default"; 764*724ba675SRob Herring pinctrl-0 = <&pwm2_out>; 765*724ba675SRob Herring}; 766*724ba675SRob Herring 767*724ba675SRob Herring&pwm3 { 768*724ba675SRob Herring pinctrl-names = "default"; 769*724ba675SRob Herring pinctrl-0 = <&pwm3_out>; 770*724ba675SRob Herring}; 771*724ba675SRob Herring 772*724ba675SRob Herring&spi0 { 773*724ba675SRob Herring compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; 774*724ba675SRob Herring pinctrl-names = "default"; 775*724ba675SRob Herring pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 776*724ba675SRob Herring}; 777*724ba675SRob Herring 778*724ba675SRob Herring&spi1 { 779*724ba675SRob Herring compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; 780*724ba675SRob Herring pinctrl-names = "default"; 781*724ba675SRob Herring pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 782*724ba675SRob Herring}; 783*724ba675SRob Herring 784*724ba675SRob Herring&uart0 { 785*724ba675SRob Herring compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 786*724ba675SRob Herring pinctrl-names = "default"; 787*724ba675SRob Herring pinctrl-0 = <&uart0_xfer>; 788*724ba675SRob Herring}; 789*724ba675SRob Herring 790*724ba675SRob Herring&uart1 { 791*724ba675SRob Herring compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 792*724ba675SRob Herring pinctrl-names = "default"; 793*724ba675SRob Herring pinctrl-0 = <&uart1_xfer>; 794*724ba675SRob Herring}; 795*724ba675SRob Herring 796*724ba675SRob Herring&uart2 { 797*724ba675SRob Herring compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 798*724ba675SRob Herring pinctrl-names = "default"; 799*724ba675SRob Herring pinctrl-0 = <&uart2_xfer>; 800*724ba675SRob Herring}; 801*724ba675SRob Herring 802*724ba675SRob Herring&uart3 { 803*724ba675SRob Herring compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 804*724ba675SRob Herring pinctrl-names = "default"; 805*724ba675SRob Herring pinctrl-0 = <&uart3_xfer>; 806*724ba675SRob Herring}; 807*724ba675SRob Herring 808*724ba675SRob Herring&vpu { 809*724ba675SRob Herring compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu"; 810*724ba675SRob Herring power-domains = <&power RK3188_PD_VIDEO>; 811*724ba675SRob Herring}; 812*724ba675SRob Herring 813*724ba675SRob Herring&wdt { 814*724ba675SRob Herring compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; 815*724ba675SRob Herring}; 816