1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree Source for the R-Car M2-N (R8A77930) SoC 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2014-2015 Renesas Electronics Corporation 6*724ba675SRob Herring */ 7*724ba675SRob Herring 8*724ba675SRob Herring#include <dt-bindings/clock/r8a7793-cpg-mssr.h> 9*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 10*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 11*724ba675SRob Herring#include <dt-bindings/power/r8a7793-sysc.h> 12*724ba675SRob Herring 13*724ba675SRob Herring/ { 14*724ba675SRob Herring compatible = "renesas,r8a7793"; 15*724ba675SRob Herring #address-cells = <2>; 16*724ba675SRob Herring #size-cells = <2>; 17*724ba675SRob Herring 18*724ba675SRob Herring aliases { 19*724ba675SRob Herring i2c0 = &i2c0; 20*724ba675SRob Herring i2c1 = &i2c1; 21*724ba675SRob Herring i2c2 = &i2c2; 22*724ba675SRob Herring i2c3 = &i2c3; 23*724ba675SRob Herring i2c4 = &i2c4; 24*724ba675SRob Herring i2c5 = &i2c5; 25*724ba675SRob Herring i2c6 = &i2c6; 26*724ba675SRob Herring i2c7 = &i2c7; 27*724ba675SRob Herring i2c8 = &i2c8; 28*724ba675SRob Herring spi0 = &qspi; 29*724ba675SRob Herring }; 30*724ba675SRob Herring 31*724ba675SRob Herring /* 32*724ba675SRob Herring * The external audio clocks are configured as 0 Hz fixed frequency 33*724ba675SRob Herring * clocks by default. 34*724ba675SRob Herring * Boards that provide audio clocks should override them. 35*724ba675SRob Herring */ 36*724ba675SRob Herring audio_clk_a: audio_clk_a { 37*724ba675SRob Herring compatible = "fixed-clock"; 38*724ba675SRob Herring #clock-cells = <0>; 39*724ba675SRob Herring clock-frequency = <0>; 40*724ba675SRob Herring }; 41*724ba675SRob Herring audio_clk_b: audio_clk_b { 42*724ba675SRob Herring compatible = "fixed-clock"; 43*724ba675SRob Herring #clock-cells = <0>; 44*724ba675SRob Herring clock-frequency = <0>; 45*724ba675SRob Herring }; 46*724ba675SRob Herring audio_clk_c: audio_clk_c { 47*724ba675SRob Herring compatible = "fixed-clock"; 48*724ba675SRob Herring #clock-cells = <0>; 49*724ba675SRob Herring clock-frequency = <0>; 50*724ba675SRob Herring }; 51*724ba675SRob Herring 52*724ba675SRob Herring /* External CAN clock */ 53*724ba675SRob Herring can_clk: can { 54*724ba675SRob Herring compatible = "fixed-clock"; 55*724ba675SRob Herring #clock-cells = <0>; 56*724ba675SRob Herring /* This value must be overridden by the board. */ 57*724ba675SRob Herring clock-frequency = <0>; 58*724ba675SRob Herring }; 59*724ba675SRob Herring 60*724ba675SRob Herring cpus { 61*724ba675SRob Herring #address-cells = <1>; 62*724ba675SRob Herring #size-cells = <0>; 63*724ba675SRob Herring 64*724ba675SRob Herring cpu0: cpu@0 { 65*724ba675SRob Herring device_type = "cpu"; 66*724ba675SRob Herring compatible = "arm,cortex-a15"; 67*724ba675SRob Herring reg = <0>; 68*724ba675SRob Herring clock-frequency = <1500000000>; 69*724ba675SRob Herring clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; 70*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_CA15_CPU0>; 71*724ba675SRob Herring enable-method = "renesas,apmu"; 72*724ba675SRob Herring voltage-tolerance = <1>; /* 1% */ 73*724ba675SRob Herring clock-latency = <300000>; /* 300 us */ 74*724ba675SRob Herring 75*724ba675SRob Herring /* kHz - uV - OPPs unknown yet */ 76*724ba675SRob Herring operating-points = <1500000 1000000>, 77*724ba675SRob Herring <1312500 1000000>, 78*724ba675SRob Herring <1125000 1000000>, 79*724ba675SRob Herring < 937500 1000000>, 80*724ba675SRob Herring < 750000 1000000>, 81*724ba675SRob Herring < 375000 1000000>; 82*724ba675SRob Herring next-level-cache = <&L2_CA15>; 83*724ba675SRob Herring }; 84*724ba675SRob Herring 85*724ba675SRob Herring cpu1: cpu@1 { 86*724ba675SRob Herring device_type = "cpu"; 87*724ba675SRob Herring compatible = "arm,cortex-a15"; 88*724ba675SRob Herring reg = <1>; 89*724ba675SRob Herring clock-frequency = <1500000000>; 90*724ba675SRob Herring clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; 91*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_CA15_CPU1>; 92*724ba675SRob Herring enable-method = "renesas,apmu"; 93*724ba675SRob Herring voltage-tolerance = <1>; /* 1% */ 94*724ba675SRob Herring clock-latency = <300000>; /* 300 us */ 95*724ba675SRob Herring 96*724ba675SRob Herring /* kHz - uV - OPPs unknown yet */ 97*724ba675SRob Herring operating-points = <1500000 1000000>, 98*724ba675SRob Herring <1312500 1000000>, 99*724ba675SRob Herring <1125000 1000000>, 100*724ba675SRob Herring < 937500 1000000>, 101*724ba675SRob Herring < 750000 1000000>, 102*724ba675SRob Herring < 375000 1000000>; 103*724ba675SRob Herring next-level-cache = <&L2_CA15>; 104*724ba675SRob Herring }; 105*724ba675SRob Herring 106*724ba675SRob Herring L2_CA15: cache-controller-0 { 107*724ba675SRob Herring compatible = "cache"; 108*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_CA15_SCU>; 109*724ba675SRob Herring cache-unified; 110*724ba675SRob Herring cache-level = <2>; 111*724ba675SRob Herring }; 112*724ba675SRob Herring }; 113*724ba675SRob Herring 114*724ba675SRob Herring /* External root clock */ 115*724ba675SRob Herring extal_clk: extal { 116*724ba675SRob Herring compatible = "fixed-clock"; 117*724ba675SRob Herring #clock-cells = <0>; 118*724ba675SRob Herring /* This value must be overridden by the board. */ 119*724ba675SRob Herring clock-frequency = <0>; 120*724ba675SRob Herring }; 121*724ba675SRob Herring 122*724ba675SRob Herring pmu { 123*724ba675SRob Herring compatible = "arm,cortex-a15-pmu"; 124*724ba675SRob Herring interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 125*724ba675SRob Herring <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 126*724ba675SRob Herring interrupt-affinity = <&cpu0>, <&cpu1>; 127*724ba675SRob Herring }; 128*724ba675SRob Herring 129*724ba675SRob Herring /* External SCIF clock */ 130*724ba675SRob Herring scif_clk: scif { 131*724ba675SRob Herring compatible = "fixed-clock"; 132*724ba675SRob Herring #clock-cells = <0>; 133*724ba675SRob Herring /* This value must be overridden by the board. */ 134*724ba675SRob Herring clock-frequency = <0>; 135*724ba675SRob Herring }; 136*724ba675SRob Herring 137*724ba675SRob Herring soc { 138*724ba675SRob Herring compatible = "simple-bus"; 139*724ba675SRob Herring interrupt-parent = <&gic>; 140*724ba675SRob Herring 141*724ba675SRob Herring #address-cells = <2>; 142*724ba675SRob Herring #size-cells = <2>; 143*724ba675SRob Herring ranges; 144*724ba675SRob Herring 145*724ba675SRob Herring rwdt: watchdog@e6020000 { 146*724ba675SRob Herring compatible = "renesas,r8a7793-wdt", 147*724ba675SRob Herring "renesas,rcar-gen2-wdt"; 148*724ba675SRob Herring reg = <0 0xe6020000 0 0x0c>; 149*724ba675SRob Herring interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 150*724ba675SRob Herring clocks = <&cpg CPG_MOD 402>; 151*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 152*724ba675SRob Herring resets = <&cpg 402>; 153*724ba675SRob Herring status = "disabled"; 154*724ba675SRob Herring }; 155*724ba675SRob Herring 156*724ba675SRob Herring gpio0: gpio@e6050000 { 157*724ba675SRob Herring compatible = "renesas,gpio-r8a7793", 158*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 159*724ba675SRob Herring reg = <0 0xe6050000 0 0x50>; 160*724ba675SRob Herring interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 161*724ba675SRob Herring #gpio-cells = <2>; 162*724ba675SRob Herring gpio-controller; 163*724ba675SRob Herring gpio-ranges = <&pfc 0 0 32>; 164*724ba675SRob Herring #interrupt-cells = <2>; 165*724ba675SRob Herring interrupt-controller; 166*724ba675SRob Herring clocks = <&cpg CPG_MOD 912>; 167*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 168*724ba675SRob Herring resets = <&cpg 912>; 169*724ba675SRob Herring }; 170*724ba675SRob Herring 171*724ba675SRob Herring gpio1: gpio@e6051000 { 172*724ba675SRob Herring compatible = "renesas,gpio-r8a7793", 173*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 174*724ba675SRob Herring reg = <0 0xe6051000 0 0x50>; 175*724ba675SRob Herring interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 176*724ba675SRob Herring #gpio-cells = <2>; 177*724ba675SRob Herring gpio-controller; 178*724ba675SRob Herring gpio-ranges = <&pfc 0 32 26>; 179*724ba675SRob Herring #interrupt-cells = <2>; 180*724ba675SRob Herring interrupt-controller; 181*724ba675SRob Herring clocks = <&cpg CPG_MOD 911>; 182*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 183*724ba675SRob Herring resets = <&cpg 911>; 184*724ba675SRob Herring }; 185*724ba675SRob Herring 186*724ba675SRob Herring gpio2: gpio@e6052000 { 187*724ba675SRob Herring compatible = "renesas,gpio-r8a7793", 188*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 189*724ba675SRob Herring reg = <0 0xe6052000 0 0x50>; 190*724ba675SRob Herring interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 191*724ba675SRob Herring #gpio-cells = <2>; 192*724ba675SRob Herring gpio-controller; 193*724ba675SRob Herring gpio-ranges = <&pfc 0 64 32>; 194*724ba675SRob Herring #interrupt-cells = <2>; 195*724ba675SRob Herring interrupt-controller; 196*724ba675SRob Herring clocks = <&cpg CPG_MOD 910>; 197*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 198*724ba675SRob Herring resets = <&cpg 910>; 199*724ba675SRob Herring }; 200*724ba675SRob Herring 201*724ba675SRob Herring gpio3: gpio@e6053000 { 202*724ba675SRob Herring compatible = "renesas,gpio-r8a7793", 203*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 204*724ba675SRob Herring reg = <0 0xe6053000 0 0x50>; 205*724ba675SRob Herring interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 206*724ba675SRob Herring #gpio-cells = <2>; 207*724ba675SRob Herring gpio-controller; 208*724ba675SRob Herring gpio-ranges = <&pfc 0 96 32>; 209*724ba675SRob Herring #interrupt-cells = <2>; 210*724ba675SRob Herring interrupt-controller; 211*724ba675SRob Herring clocks = <&cpg CPG_MOD 909>; 212*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 213*724ba675SRob Herring resets = <&cpg 909>; 214*724ba675SRob Herring }; 215*724ba675SRob Herring 216*724ba675SRob Herring gpio4: gpio@e6054000 { 217*724ba675SRob Herring compatible = "renesas,gpio-r8a7793", 218*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 219*724ba675SRob Herring reg = <0 0xe6054000 0 0x50>; 220*724ba675SRob Herring interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 221*724ba675SRob Herring #gpio-cells = <2>; 222*724ba675SRob Herring gpio-controller; 223*724ba675SRob Herring gpio-ranges = <&pfc 0 128 32>; 224*724ba675SRob Herring #interrupt-cells = <2>; 225*724ba675SRob Herring interrupt-controller; 226*724ba675SRob Herring clocks = <&cpg CPG_MOD 908>; 227*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 228*724ba675SRob Herring resets = <&cpg 908>; 229*724ba675SRob Herring }; 230*724ba675SRob Herring 231*724ba675SRob Herring gpio5: gpio@e6055000 { 232*724ba675SRob Herring compatible = "renesas,gpio-r8a7793", 233*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 234*724ba675SRob Herring reg = <0 0xe6055000 0 0x50>; 235*724ba675SRob Herring interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 236*724ba675SRob Herring #gpio-cells = <2>; 237*724ba675SRob Herring gpio-controller; 238*724ba675SRob Herring gpio-ranges = <&pfc 0 160 32>; 239*724ba675SRob Herring #interrupt-cells = <2>; 240*724ba675SRob Herring interrupt-controller; 241*724ba675SRob Herring clocks = <&cpg CPG_MOD 907>; 242*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 243*724ba675SRob Herring resets = <&cpg 907>; 244*724ba675SRob Herring }; 245*724ba675SRob Herring 246*724ba675SRob Herring gpio6: gpio@e6055400 { 247*724ba675SRob Herring compatible = "renesas,gpio-r8a7793", 248*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 249*724ba675SRob Herring reg = <0 0xe6055400 0 0x50>; 250*724ba675SRob Herring interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 251*724ba675SRob Herring #gpio-cells = <2>; 252*724ba675SRob Herring gpio-controller; 253*724ba675SRob Herring gpio-ranges = <&pfc 0 192 32>; 254*724ba675SRob Herring #interrupt-cells = <2>; 255*724ba675SRob Herring interrupt-controller; 256*724ba675SRob Herring clocks = <&cpg CPG_MOD 905>; 257*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 258*724ba675SRob Herring resets = <&cpg 905>; 259*724ba675SRob Herring }; 260*724ba675SRob Herring 261*724ba675SRob Herring gpio7: gpio@e6055800 { 262*724ba675SRob Herring compatible = "renesas,gpio-r8a7793", 263*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 264*724ba675SRob Herring reg = <0 0xe6055800 0 0x50>; 265*724ba675SRob Herring interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 266*724ba675SRob Herring #gpio-cells = <2>; 267*724ba675SRob Herring gpio-controller; 268*724ba675SRob Herring gpio-ranges = <&pfc 0 224 26>; 269*724ba675SRob Herring #interrupt-cells = <2>; 270*724ba675SRob Herring interrupt-controller; 271*724ba675SRob Herring clocks = <&cpg CPG_MOD 904>; 272*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 273*724ba675SRob Herring resets = <&cpg 904>; 274*724ba675SRob Herring }; 275*724ba675SRob Herring 276*724ba675SRob Herring pfc: pinctrl@e6060000 { 277*724ba675SRob Herring compatible = "renesas,pfc-r8a7793"; 278*724ba675SRob Herring reg = <0 0xe6060000 0 0x250>; 279*724ba675SRob Herring }; 280*724ba675SRob Herring 281*724ba675SRob Herring /* Special CPG clocks */ 282*724ba675SRob Herring cpg: clock-controller@e6150000 { 283*724ba675SRob Herring compatible = "renesas,r8a7793-cpg-mssr"; 284*724ba675SRob Herring reg = <0 0xe6150000 0 0x1000>; 285*724ba675SRob Herring clocks = <&extal_clk>, <&usb_extal_clk>; 286*724ba675SRob Herring clock-names = "extal", "usb_extal"; 287*724ba675SRob Herring #clock-cells = <2>; 288*724ba675SRob Herring #power-domain-cells = <0>; 289*724ba675SRob Herring #reset-cells = <1>; 290*724ba675SRob Herring }; 291*724ba675SRob Herring 292*724ba675SRob Herring apmu@e6152000 { 293*724ba675SRob Herring compatible = "renesas,r8a7793-apmu", "renesas,apmu"; 294*724ba675SRob Herring reg = <0 0xe6152000 0 0x188>; 295*724ba675SRob Herring cpus = <&cpu0>, <&cpu1>; 296*724ba675SRob Herring }; 297*724ba675SRob Herring 298*724ba675SRob Herring rst: reset-controller@e6160000 { 299*724ba675SRob Herring compatible = "renesas,r8a7793-rst"; 300*724ba675SRob Herring reg = <0 0xe6160000 0 0x0100>; 301*724ba675SRob Herring }; 302*724ba675SRob Herring 303*724ba675SRob Herring sysc: system-controller@e6180000 { 304*724ba675SRob Herring compatible = "renesas,r8a7793-sysc"; 305*724ba675SRob Herring reg = <0 0xe6180000 0 0x0200>; 306*724ba675SRob Herring #power-domain-cells = <1>; 307*724ba675SRob Herring }; 308*724ba675SRob Herring 309*724ba675SRob Herring irqc0: interrupt-controller@e61c0000 { 310*724ba675SRob Herring compatible = "renesas,irqc-r8a7793", "renesas,irqc"; 311*724ba675SRob Herring #interrupt-cells = <2>; 312*724ba675SRob Herring interrupt-controller; 313*724ba675SRob Herring reg = <0 0xe61c0000 0 0x200>; 314*724ba675SRob Herring interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 315*724ba675SRob Herring <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 316*724ba675SRob Herring <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 317*724ba675SRob Herring <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 318*724ba675SRob Herring <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 319*724ba675SRob Herring <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 320*724ba675SRob Herring <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 321*724ba675SRob Herring <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 322*724ba675SRob Herring <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 323*724ba675SRob Herring <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 324*724ba675SRob Herring clocks = <&cpg CPG_MOD 407>; 325*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 326*724ba675SRob Herring resets = <&cpg 407>; 327*724ba675SRob Herring }; 328*724ba675SRob Herring 329*724ba675SRob Herring thermal: thermal@e61f0000 { 330*724ba675SRob Herring compatible = "renesas,thermal-r8a7793", 331*724ba675SRob Herring "renesas,rcar-gen2-thermal", 332*724ba675SRob Herring "renesas,rcar-thermal"; 333*724ba675SRob Herring reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; 334*724ba675SRob Herring interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 335*724ba675SRob Herring clocks = <&cpg CPG_MOD 522>; 336*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 337*724ba675SRob Herring resets = <&cpg 522>; 338*724ba675SRob Herring #thermal-sensor-cells = <0>; 339*724ba675SRob Herring }; 340*724ba675SRob Herring 341*724ba675SRob Herring ipmmu_sy0: iommu@e6280000 { 342*724ba675SRob Herring compatible = "renesas,ipmmu-r8a7793", 343*724ba675SRob Herring "renesas,ipmmu-vmsa"; 344*724ba675SRob Herring reg = <0 0xe6280000 0 0x1000>; 345*724ba675SRob Herring interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 346*724ba675SRob Herring <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 347*724ba675SRob Herring #iommu-cells = <1>; 348*724ba675SRob Herring status = "disabled"; 349*724ba675SRob Herring }; 350*724ba675SRob Herring 351*724ba675SRob Herring ipmmu_sy1: iommu@e6290000 { 352*724ba675SRob Herring compatible = "renesas,ipmmu-r8a7793", 353*724ba675SRob Herring "renesas,ipmmu-vmsa"; 354*724ba675SRob Herring reg = <0 0xe6290000 0 0x1000>; 355*724ba675SRob Herring interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 356*724ba675SRob Herring #iommu-cells = <1>; 357*724ba675SRob Herring status = "disabled"; 358*724ba675SRob Herring }; 359*724ba675SRob Herring 360*724ba675SRob Herring ipmmu_ds: iommu@e6740000 { 361*724ba675SRob Herring compatible = "renesas,ipmmu-r8a7793", 362*724ba675SRob Herring "renesas,ipmmu-vmsa"; 363*724ba675SRob Herring reg = <0 0xe6740000 0 0x1000>; 364*724ba675SRob Herring interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 365*724ba675SRob Herring <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 366*724ba675SRob Herring #iommu-cells = <1>; 367*724ba675SRob Herring status = "disabled"; 368*724ba675SRob Herring }; 369*724ba675SRob Herring 370*724ba675SRob Herring ipmmu_mp: iommu@ec680000 { 371*724ba675SRob Herring compatible = "renesas,ipmmu-r8a7793", 372*724ba675SRob Herring "renesas,ipmmu-vmsa"; 373*724ba675SRob Herring reg = <0 0xec680000 0 0x1000>; 374*724ba675SRob Herring interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 375*724ba675SRob Herring #iommu-cells = <1>; 376*724ba675SRob Herring status = "disabled"; 377*724ba675SRob Herring }; 378*724ba675SRob Herring 379*724ba675SRob Herring ipmmu_mx: iommu@fe951000 { 380*724ba675SRob Herring compatible = "renesas,ipmmu-r8a7793", 381*724ba675SRob Herring "renesas,ipmmu-vmsa"; 382*724ba675SRob Herring reg = <0 0xfe951000 0 0x1000>; 383*724ba675SRob Herring interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 384*724ba675SRob Herring <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 385*724ba675SRob Herring #iommu-cells = <1>; 386*724ba675SRob Herring status = "disabled"; 387*724ba675SRob Herring }; 388*724ba675SRob Herring 389*724ba675SRob Herring ipmmu_rt: iommu@ffc80000 { 390*724ba675SRob Herring compatible = "renesas,ipmmu-r8a7793", 391*724ba675SRob Herring "renesas,ipmmu-vmsa"; 392*724ba675SRob Herring reg = <0 0xffc80000 0 0x1000>; 393*724ba675SRob Herring interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 394*724ba675SRob Herring #iommu-cells = <1>; 395*724ba675SRob Herring status = "disabled"; 396*724ba675SRob Herring }; 397*724ba675SRob Herring 398*724ba675SRob Herring ipmmu_gp: iommu@e62a0000 { 399*724ba675SRob Herring compatible = "renesas,ipmmu-r8a7793", 400*724ba675SRob Herring "renesas,ipmmu-vmsa"; 401*724ba675SRob Herring reg = <0 0xe62a0000 0 0x1000>; 402*724ba675SRob Herring interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 403*724ba675SRob Herring <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 404*724ba675SRob Herring #iommu-cells = <1>; 405*724ba675SRob Herring status = "disabled"; 406*724ba675SRob Herring }; 407*724ba675SRob Herring 408*724ba675SRob Herring icram0: sram@e63a0000 { 409*724ba675SRob Herring compatible = "mmio-sram"; 410*724ba675SRob Herring reg = <0 0xe63a0000 0 0x12000>; 411*724ba675SRob Herring #address-cells = <1>; 412*724ba675SRob Herring #size-cells = <1>; 413*724ba675SRob Herring ranges = <0 0 0xe63a0000 0x12000>; 414*724ba675SRob Herring }; 415*724ba675SRob Herring 416*724ba675SRob Herring icram1: sram@e63c0000 { 417*724ba675SRob Herring compatible = "mmio-sram"; 418*724ba675SRob Herring reg = <0 0xe63c0000 0 0x1000>; 419*724ba675SRob Herring #address-cells = <1>; 420*724ba675SRob Herring #size-cells = <1>; 421*724ba675SRob Herring ranges = <0 0 0xe63c0000 0x1000>; 422*724ba675SRob Herring 423*724ba675SRob Herring smp-sram@0 { 424*724ba675SRob Herring compatible = "renesas,smp-sram"; 425*724ba675SRob Herring reg = <0 0x100>; 426*724ba675SRob Herring }; 427*724ba675SRob Herring }; 428*724ba675SRob Herring 429*724ba675SRob Herring /* The memory map in the User's Manual maps the cores to 430*724ba675SRob Herring * bus numbers 431*724ba675SRob Herring */ 432*724ba675SRob Herring i2c0: i2c@e6508000 { 433*724ba675SRob Herring #address-cells = <1>; 434*724ba675SRob Herring #size-cells = <0>; 435*724ba675SRob Herring compatible = "renesas,i2c-r8a7793", 436*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 437*724ba675SRob Herring reg = <0 0xe6508000 0 0x40>; 438*724ba675SRob Herring interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 439*724ba675SRob Herring clocks = <&cpg CPG_MOD 931>; 440*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 441*724ba675SRob Herring resets = <&cpg 931>; 442*724ba675SRob Herring i2c-scl-internal-delay-ns = <6>; 443*724ba675SRob Herring status = "disabled"; 444*724ba675SRob Herring }; 445*724ba675SRob Herring 446*724ba675SRob Herring i2c1: i2c@e6518000 { 447*724ba675SRob Herring #address-cells = <1>; 448*724ba675SRob Herring #size-cells = <0>; 449*724ba675SRob Herring compatible = "renesas,i2c-r8a7793", 450*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 451*724ba675SRob Herring reg = <0 0xe6518000 0 0x40>; 452*724ba675SRob Herring interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 453*724ba675SRob Herring clocks = <&cpg CPG_MOD 930>; 454*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 455*724ba675SRob Herring resets = <&cpg 930>; 456*724ba675SRob Herring i2c-scl-internal-delay-ns = <6>; 457*724ba675SRob Herring status = "disabled"; 458*724ba675SRob Herring }; 459*724ba675SRob Herring 460*724ba675SRob Herring i2c2: i2c@e6530000 { 461*724ba675SRob Herring #address-cells = <1>; 462*724ba675SRob Herring #size-cells = <0>; 463*724ba675SRob Herring compatible = "renesas,i2c-r8a7793", 464*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 465*724ba675SRob Herring reg = <0 0xe6530000 0 0x40>; 466*724ba675SRob Herring interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 467*724ba675SRob Herring clocks = <&cpg CPG_MOD 929>; 468*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 469*724ba675SRob Herring resets = <&cpg 929>; 470*724ba675SRob Herring i2c-scl-internal-delay-ns = <6>; 471*724ba675SRob Herring status = "disabled"; 472*724ba675SRob Herring }; 473*724ba675SRob Herring 474*724ba675SRob Herring i2c3: i2c@e6540000 { 475*724ba675SRob Herring #address-cells = <1>; 476*724ba675SRob Herring #size-cells = <0>; 477*724ba675SRob Herring compatible = "renesas,i2c-r8a7793", 478*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 479*724ba675SRob Herring reg = <0 0xe6540000 0 0x40>; 480*724ba675SRob Herring interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 481*724ba675SRob Herring clocks = <&cpg CPG_MOD 928>; 482*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 483*724ba675SRob Herring resets = <&cpg 928>; 484*724ba675SRob Herring i2c-scl-internal-delay-ns = <6>; 485*724ba675SRob Herring status = "disabled"; 486*724ba675SRob Herring }; 487*724ba675SRob Herring 488*724ba675SRob Herring i2c4: i2c@e6520000 { 489*724ba675SRob Herring #address-cells = <1>; 490*724ba675SRob Herring #size-cells = <0>; 491*724ba675SRob Herring compatible = "renesas,i2c-r8a7793", 492*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 493*724ba675SRob Herring reg = <0 0xe6520000 0 0x40>; 494*724ba675SRob Herring interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 495*724ba675SRob Herring clocks = <&cpg CPG_MOD 927>; 496*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 497*724ba675SRob Herring resets = <&cpg 927>; 498*724ba675SRob Herring i2c-scl-internal-delay-ns = <6>; 499*724ba675SRob Herring status = "disabled"; 500*724ba675SRob Herring }; 501*724ba675SRob Herring 502*724ba675SRob Herring i2c5: i2c@e6528000 { 503*724ba675SRob Herring /* doesn't need pinmux */ 504*724ba675SRob Herring #address-cells = <1>; 505*724ba675SRob Herring #size-cells = <0>; 506*724ba675SRob Herring compatible = "renesas,i2c-r8a7793", 507*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 508*724ba675SRob Herring reg = <0 0xe6528000 0 0x40>; 509*724ba675SRob Herring interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 510*724ba675SRob Herring clocks = <&cpg CPG_MOD 925>; 511*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 512*724ba675SRob Herring resets = <&cpg 925>; 513*724ba675SRob Herring i2c-scl-internal-delay-ns = <110>; 514*724ba675SRob Herring status = "disabled"; 515*724ba675SRob Herring }; 516*724ba675SRob Herring 517*724ba675SRob Herring i2c6: i2c@e60b0000 { 518*724ba675SRob Herring /* doesn't need pinmux */ 519*724ba675SRob Herring #address-cells = <1>; 520*724ba675SRob Herring #size-cells = <0>; 521*724ba675SRob Herring compatible = "renesas,iic-r8a7793", 522*724ba675SRob Herring "renesas,rcar-gen2-iic", 523*724ba675SRob Herring "renesas,rmobile-iic"; 524*724ba675SRob Herring reg = <0 0xe60b0000 0 0x425>; 525*724ba675SRob Herring interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 526*724ba675SRob Herring clocks = <&cpg CPG_MOD 926>; 527*724ba675SRob Herring dmas = <&dmac0 0x77>, <&dmac0 0x78>, 528*724ba675SRob Herring <&dmac1 0x77>, <&dmac1 0x78>; 529*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 530*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 531*724ba675SRob Herring resets = <&cpg 926>; 532*724ba675SRob Herring status = "disabled"; 533*724ba675SRob Herring }; 534*724ba675SRob Herring 535*724ba675SRob Herring i2c7: i2c@e6500000 { 536*724ba675SRob Herring #address-cells = <1>; 537*724ba675SRob Herring #size-cells = <0>; 538*724ba675SRob Herring compatible = "renesas,iic-r8a7793", 539*724ba675SRob Herring "renesas,rcar-gen2-iic", 540*724ba675SRob Herring "renesas,rmobile-iic"; 541*724ba675SRob Herring reg = <0 0xe6500000 0 0x425>; 542*724ba675SRob Herring interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 543*724ba675SRob Herring clocks = <&cpg CPG_MOD 318>; 544*724ba675SRob Herring dmas = <&dmac0 0x61>, <&dmac0 0x62>, 545*724ba675SRob Herring <&dmac1 0x61>, <&dmac1 0x62>; 546*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 547*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 548*724ba675SRob Herring resets = <&cpg 318>; 549*724ba675SRob Herring status = "disabled"; 550*724ba675SRob Herring }; 551*724ba675SRob Herring 552*724ba675SRob Herring i2c8: i2c@e6510000 { 553*724ba675SRob Herring #address-cells = <1>; 554*724ba675SRob Herring #size-cells = <0>; 555*724ba675SRob Herring compatible = "renesas,iic-r8a7793", 556*724ba675SRob Herring "renesas,rcar-gen2-iic", 557*724ba675SRob Herring "renesas,rmobile-iic"; 558*724ba675SRob Herring reg = <0 0xe6510000 0 0x425>; 559*724ba675SRob Herring interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 560*724ba675SRob Herring clocks = <&cpg CPG_MOD 323>; 561*724ba675SRob Herring dmas = <&dmac0 0x65>, <&dmac0 0x66>, 562*724ba675SRob Herring <&dmac1 0x65>, <&dmac1 0x66>; 563*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 564*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 565*724ba675SRob Herring resets = <&cpg 323>; 566*724ba675SRob Herring status = "disabled"; 567*724ba675SRob Herring }; 568*724ba675SRob Herring 569*724ba675SRob Herring dmac0: dma-controller@e6700000 { 570*724ba675SRob Herring compatible = "renesas,dmac-r8a7793", 571*724ba675SRob Herring "renesas,rcar-dmac"; 572*724ba675SRob Herring reg = <0 0xe6700000 0 0x20000>; 573*724ba675SRob Herring interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 574*724ba675SRob Herring <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 575*724ba675SRob Herring <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 576*724ba675SRob Herring <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 577*724ba675SRob Herring <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 578*724ba675SRob Herring <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 579*724ba675SRob Herring <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 580*724ba675SRob Herring <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 581*724ba675SRob Herring <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 582*724ba675SRob Herring <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 583*724ba675SRob Herring <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 584*724ba675SRob Herring <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 585*724ba675SRob Herring <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 586*724ba675SRob Herring <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 587*724ba675SRob Herring <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 588*724ba675SRob Herring <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 589*724ba675SRob Herring interrupt-names = "error", 590*724ba675SRob Herring "ch0", "ch1", "ch2", "ch3", 591*724ba675SRob Herring "ch4", "ch5", "ch6", "ch7", 592*724ba675SRob Herring "ch8", "ch9", "ch10", "ch11", 593*724ba675SRob Herring "ch12", "ch13", "ch14"; 594*724ba675SRob Herring clocks = <&cpg CPG_MOD 219>; 595*724ba675SRob Herring clock-names = "fck"; 596*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 597*724ba675SRob Herring resets = <&cpg 219>; 598*724ba675SRob Herring #dma-cells = <1>; 599*724ba675SRob Herring dma-channels = <15>; 600*724ba675SRob Herring }; 601*724ba675SRob Herring 602*724ba675SRob Herring dmac1: dma-controller@e6720000 { 603*724ba675SRob Herring compatible = "renesas,dmac-r8a7793", 604*724ba675SRob Herring "renesas,rcar-dmac"; 605*724ba675SRob Herring reg = <0 0xe6720000 0 0x20000>; 606*724ba675SRob Herring interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 607*724ba675SRob Herring <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 608*724ba675SRob Herring <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 609*724ba675SRob Herring <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 610*724ba675SRob Herring <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 611*724ba675SRob Herring <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 612*724ba675SRob Herring <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 613*724ba675SRob Herring <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 614*724ba675SRob Herring <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 615*724ba675SRob Herring <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 616*724ba675SRob Herring <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 617*724ba675SRob Herring <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 618*724ba675SRob Herring <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 619*724ba675SRob Herring <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 620*724ba675SRob Herring <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 621*724ba675SRob Herring <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 622*724ba675SRob Herring interrupt-names = "error", 623*724ba675SRob Herring "ch0", "ch1", "ch2", "ch3", 624*724ba675SRob Herring "ch4", "ch5", "ch6", "ch7", 625*724ba675SRob Herring "ch8", "ch9", "ch10", "ch11", 626*724ba675SRob Herring "ch12", "ch13", "ch14"; 627*724ba675SRob Herring clocks = <&cpg CPG_MOD 218>; 628*724ba675SRob Herring clock-names = "fck"; 629*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 630*724ba675SRob Herring resets = <&cpg 218>; 631*724ba675SRob Herring #dma-cells = <1>; 632*724ba675SRob Herring dma-channels = <15>; 633*724ba675SRob Herring }; 634*724ba675SRob Herring 635*724ba675SRob Herring qspi: spi@e6b10000 { 636*724ba675SRob Herring compatible = "renesas,qspi-r8a7793", "renesas,qspi"; 637*724ba675SRob Herring reg = <0 0xe6b10000 0 0x2c>; 638*724ba675SRob Herring interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 639*724ba675SRob Herring clocks = <&cpg CPG_MOD 917>; 640*724ba675SRob Herring dmas = <&dmac0 0x17>, <&dmac0 0x18>, 641*724ba675SRob Herring <&dmac1 0x17>, <&dmac1 0x18>; 642*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 643*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 644*724ba675SRob Herring resets = <&cpg 917>; 645*724ba675SRob Herring num-cs = <1>; 646*724ba675SRob Herring #address-cells = <1>; 647*724ba675SRob Herring #size-cells = <0>; 648*724ba675SRob Herring status = "disabled"; 649*724ba675SRob Herring }; 650*724ba675SRob Herring 651*724ba675SRob Herring scifa0: serial@e6c40000 { 652*724ba675SRob Herring compatible = "renesas,scifa-r8a7793", 653*724ba675SRob Herring "renesas,rcar-gen2-scifa", "renesas,scifa"; 654*724ba675SRob Herring reg = <0 0xe6c40000 0 64>; 655*724ba675SRob Herring interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 656*724ba675SRob Herring clocks = <&cpg CPG_MOD 204>; 657*724ba675SRob Herring clock-names = "fck"; 658*724ba675SRob Herring dmas = <&dmac0 0x21>, <&dmac0 0x22>, 659*724ba675SRob Herring <&dmac1 0x21>, <&dmac1 0x22>; 660*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 661*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 662*724ba675SRob Herring resets = <&cpg 204>; 663*724ba675SRob Herring status = "disabled"; 664*724ba675SRob Herring }; 665*724ba675SRob Herring 666*724ba675SRob Herring scifa1: serial@e6c50000 { 667*724ba675SRob Herring compatible = "renesas,scifa-r8a7793", 668*724ba675SRob Herring "renesas,rcar-gen2-scifa", "renesas,scifa"; 669*724ba675SRob Herring reg = <0 0xe6c50000 0 64>; 670*724ba675SRob Herring interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 671*724ba675SRob Herring clocks = <&cpg CPG_MOD 203>; 672*724ba675SRob Herring clock-names = "fck"; 673*724ba675SRob Herring dmas = <&dmac0 0x25>, <&dmac0 0x26>, 674*724ba675SRob Herring <&dmac1 0x25>, <&dmac1 0x26>; 675*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 676*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 677*724ba675SRob Herring resets = <&cpg 203>; 678*724ba675SRob Herring status = "disabled"; 679*724ba675SRob Herring }; 680*724ba675SRob Herring 681*724ba675SRob Herring scifa2: serial@e6c60000 { 682*724ba675SRob Herring compatible = "renesas,scifa-r8a7793", 683*724ba675SRob Herring "renesas,rcar-gen2-scifa", "renesas,scifa"; 684*724ba675SRob Herring reg = <0 0xe6c60000 0 64>; 685*724ba675SRob Herring interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 686*724ba675SRob Herring clocks = <&cpg CPG_MOD 202>; 687*724ba675SRob Herring clock-names = "fck"; 688*724ba675SRob Herring dmas = <&dmac0 0x27>, <&dmac0 0x28>, 689*724ba675SRob Herring <&dmac1 0x27>, <&dmac1 0x28>; 690*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 691*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 692*724ba675SRob Herring resets = <&cpg 202>; 693*724ba675SRob Herring status = "disabled"; 694*724ba675SRob Herring }; 695*724ba675SRob Herring 696*724ba675SRob Herring scifa3: serial@e6c70000 { 697*724ba675SRob Herring compatible = "renesas,scifa-r8a7793", 698*724ba675SRob Herring "renesas,rcar-gen2-scifa", "renesas,scifa"; 699*724ba675SRob Herring reg = <0 0xe6c70000 0 64>; 700*724ba675SRob Herring interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 701*724ba675SRob Herring clocks = <&cpg CPG_MOD 1106>; 702*724ba675SRob Herring clock-names = "fck"; 703*724ba675SRob Herring dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, 704*724ba675SRob Herring <&dmac1 0x1b>, <&dmac1 0x1c>; 705*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 706*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 707*724ba675SRob Herring resets = <&cpg 1106>; 708*724ba675SRob Herring status = "disabled"; 709*724ba675SRob Herring }; 710*724ba675SRob Herring 711*724ba675SRob Herring scifa4: serial@e6c78000 { 712*724ba675SRob Herring compatible = "renesas,scifa-r8a7793", 713*724ba675SRob Herring "renesas,rcar-gen2-scifa", "renesas,scifa"; 714*724ba675SRob Herring reg = <0 0xe6c78000 0 64>; 715*724ba675SRob Herring interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 716*724ba675SRob Herring clocks = <&cpg CPG_MOD 1107>; 717*724ba675SRob Herring clock-names = "fck"; 718*724ba675SRob Herring dmas = <&dmac0 0x1f>, <&dmac0 0x20>, 719*724ba675SRob Herring <&dmac1 0x1f>, <&dmac1 0x20>; 720*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 721*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 722*724ba675SRob Herring resets = <&cpg 1107>; 723*724ba675SRob Herring status = "disabled"; 724*724ba675SRob Herring }; 725*724ba675SRob Herring 726*724ba675SRob Herring scifa5: serial@e6c80000 { 727*724ba675SRob Herring compatible = "renesas,scifa-r8a7793", 728*724ba675SRob Herring "renesas,rcar-gen2-scifa", "renesas,scifa"; 729*724ba675SRob Herring reg = <0 0xe6c80000 0 64>; 730*724ba675SRob Herring interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 731*724ba675SRob Herring clocks = <&cpg CPG_MOD 1108>; 732*724ba675SRob Herring clock-names = "fck"; 733*724ba675SRob Herring dmas = <&dmac0 0x23>, <&dmac0 0x24>, 734*724ba675SRob Herring <&dmac1 0x23>, <&dmac1 0x24>; 735*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 736*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 737*724ba675SRob Herring resets = <&cpg 1108>; 738*724ba675SRob Herring status = "disabled"; 739*724ba675SRob Herring }; 740*724ba675SRob Herring 741*724ba675SRob Herring scifb0: serial@e6c20000 { 742*724ba675SRob Herring compatible = "renesas,scifb-r8a7793", 743*724ba675SRob Herring "renesas,rcar-gen2-scifb", "renesas,scifb"; 744*724ba675SRob Herring reg = <0 0xe6c20000 0 0x100>; 745*724ba675SRob Herring interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 746*724ba675SRob Herring clocks = <&cpg CPG_MOD 206>; 747*724ba675SRob Herring clock-names = "fck"; 748*724ba675SRob Herring dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, 749*724ba675SRob Herring <&dmac1 0x3d>, <&dmac1 0x3e>; 750*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 751*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 752*724ba675SRob Herring resets = <&cpg 206>; 753*724ba675SRob Herring status = "disabled"; 754*724ba675SRob Herring }; 755*724ba675SRob Herring 756*724ba675SRob Herring scifb1: serial@e6c30000 { 757*724ba675SRob Herring compatible = "renesas,scifb-r8a7793", 758*724ba675SRob Herring "renesas,rcar-gen2-scifb", "renesas,scifb"; 759*724ba675SRob Herring reg = <0 0xe6c30000 0 0x100>; 760*724ba675SRob Herring interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 761*724ba675SRob Herring clocks = <&cpg CPG_MOD 207>; 762*724ba675SRob Herring clock-names = "fck"; 763*724ba675SRob Herring dmas = <&dmac0 0x19>, <&dmac0 0x1a>, 764*724ba675SRob Herring <&dmac1 0x19>, <&dmac1 0x1a>; 765*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 766*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 767*724ba675SRob Herring resets = <&cpg 207>; 768*724ba675SRob Herring status = "disabled"; 769*724ba675SRob Herring }; 770*724ba675SRob Herring 771*724ba675SRob Herring scifb2: serial@e6ce0000 { 772*724ba675SRob Herring compatible = "renesas,scifb-r8a7793", 773*724ba675SRob Herring "renesas,rcar-gen2-scifb", "renesas,scifb"; 774*724ba675SRob Herring reg = <0 0xe6ce0000 0 0x100>; 775*724ba675SRob Herring interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 776*724ba675SRob Herring clocks = <&cpg CPG_MOD 216>; 777*724ba675SRob Herring clock-names = "fck"; 778*724ba675SRob Herring dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, 779*724ba675SRob Herring <&dmac1 0x1d>, <&dmac1 0x1e>; 780*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 781*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 782*724ba675SRob Herring resets = <&cpg 216>; 783*724ba675SRob Herring status = "disabled"; 784*724ba675SRob Herring }; 785*724ba675SRob Herring 786*724ba675SRob Herring scif0: serial@e6e60000 { 787*724ba675SRob Herring compatible = "renesas,scif-r8a7793", 788*724ba675SRob Herring "renesas,rcar-gen2-scif", "renesas,scif"; 789*724ba675SRob Herring reg = <0 0xe6e60000 0 64>; 790*724ba675SRob Herring interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 791*724ba675SRob Herring clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 792*724ba675SRob Herring <&scif_clk>; 793*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 794*724ba675SRob Herring dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 795*724ba675SRob Herring <&dmac1 0x29>, <&dmac1 0x2a>; 796*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 797*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 798*724ba675SRob Herring resets = <&cpg 721>; 799*724ba675SRob Herring status = "disabled"; 800*724ba675SRob Herring }; 801*724ba675SRob Herring 802*724ba675SRob Herring scif1: serial@e6e68000 { 803*724ba675SRob Herring compatible = "renesas,scif-r8a7793", 804*724ba675SRob Herring "renesas,rcar-gen2-scif", "renesas,scif"; 805*724ba675SRob Herring reg = <0 0xe6e68000 0 64>; 806*724ba675SRob Herring interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 807*724ba675SRob Herring clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 808*724ba675SRob Herring <&scif_clk>; 809*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 810*724ba675SRob Herring dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 811*724ba675SRob Herring <&dmac1 0x2d>, <&dmac1 0x2e>; 812*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 813*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 814*724ba675SRob Herring resets = <&cpg 720>; 815*724ba675SRob Herring status = "disabled"; 816*724ba675SRob Herring }; 817*724ba675SRob Herring 818*724ba675SRob Herring scif2: serial@e6e58000 { 819*724ba675SRob Herring compatible = "renesas,scif-r8a7793", 820*724ba675SRob Herring "renesas,rcar-gen2-scif", "renesas,scif"; 821*724ba675SRob Herring reg = <0 0xe6e58000 0 64>; 822*724ba675SRob Herring interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 823*724ba675SRob Herring clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 824*724ba675SRob Herring <&scif_clk>; 825*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 826*724ba675SRob Herring dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 827*724ba675SRob Herring <&dmac1 0x2b>, <&dmac1 0x2c>; 828*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 829*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 830*724ba675SRob Herring resets = <&cpg 719>; 831*724ba675SRob Herring status = "disabled"; 832*724ba675SRob Herring }; 833*724ba675SRob Herring 834*724ba675SRob Herring scif3: serial@e6ea8000 { 835*724ba675SRob Herring compatible = "renesas,scif-r8a7793", 836*724ba675SRob Herring "renesas,rcar-gen2-scif", "renesas,scif"; 837*724ba675SRob Herring reg = <0 0xe6ea8000 0 64>; 838*724ba675SRob Herring interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 839*724ba675SRob Herring clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 840*724ba675SRob Herring <&scif_clk>; 841*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 842*724ba675SRob Herring dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 843*724ba675SRob Herring <&dmac1 0x2f>, <&dmac1 0x30>; 844*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 845*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 846*724ba675SRob Herring resets = <&cpg 718>; 847*724ba675SRob Herring status = "disabled"; 848*724ba675SRob Herring }; 849*724ba675SRob Herring 850*724ba675SRob Herring scif4: serial@e6ee0000 { 851*724ba675SRob Herring compatible = "renesas,scif-r8a7793", 852*724ba675SRob Herring "renesas,rcar-gen2-scif", "renesas,scif"; 853*724ba675SRob Herring reg = <0 0xe6ee0000 0 64>; 854*724ba675SRob Herring interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 855*724ba675SRob Herring clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 856*724ba675SRob Herring <&scif_clk>; 857*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 858*724ba675SRob Herring dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, 859*724ba675SRob Herring <&dmac1 0xfb>, <&dmac1 0xfc>; 860*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 861*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 862*724ba675SRob Herring resets = <&cpg 715>; 863*724ba675SRob Herring status = "disabled"; 864*724ba675SRob Herring }; 865*724ba675SRob Herring 866*724ba675SRob Herring scif5: serial@e6ee8000 { 867*724ba675SRob Herring compatible = "renesas,scif-r8a7793", 868*724ba675SRob Herring "renesas,rcar-gen2-scif", "renesas,scif"; 869*724ba675SRob Herring reg = <0 0xe6ee8000 0 64>; 870*724ba675SRob Herring interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 871*724ba675SRob Herring clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 872*724ba675SRob Herring <&scif_clk>; 873*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 874*724ba675SRob Herring dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, 875*724ba675SRob Herring <&dmac1 0xfd>, <&dmac1 0xfe>; 876*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 877*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 878*724ba675SRob Herring resets = <&cpg 714>; 879*724ba675SRob Herring status = "disabled"; 880*724ba675SRob Herring }; 881*724ba675SRob Herring 882*724ba675SRob Herring hscif0: serial@e62c0000 { 883*724ba675SRob Herring compatible = "renesas,hscif-r8a7793", 884*724ba675SRob Herring "renesas,rcar-gen2-hscif", "renesas,hscif"; 885*724ba675SRob Herring reg = <0 0xe62c0000 0 96>; 886*724ba675SRob Herring interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 887*724ba675SRob Herring clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 888*724ba675SRob Herring <&scif_clk>; 889*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 890*724ba675SRob Herring dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 891*724ba675SRob Herring <&dmac1 0x39>, <&dmac1 0x3a>; 892*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 893*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 894*724ba675SRob Herring resets = <&cpg 717>; 895*724ba675SRob Herring status = "disabled"; 896*724ba675SRob Herring }; 897*724ba675SRob Herring 898*724ba675SRob Herring hscif1: serial@e62c8000 { 899*724ba675SRob Herring compatible = "renesas,hscif-r8a7793", 900*724ba675SRob Herring "renesas,rcar-gen2-hscif", "renesas,hscif"; 901*724ba675SRob Herring reg = <0 0xe62c8000 0 96>; 902*724ba675SRob Herring interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 903*724ba675SRob Herring clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 904*724ba675SRob Herring <&scif_clk>; 905*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 906*724ba675SRob Herring dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 907*724ba675SRob Herring <&dmac1 0x4d>, <&dmac1 0x4e>; 908*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 909*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 910*724ba675SRob Herring resets = <&cpg 716>; 911*724ba675SRob Herring status = "disabled"; 912*724ba675SRob Herring }; 913*724ba675SRob Herring 914*724ba675SRob Herring hscif2: serial@e62d0000 { 915*724ba675SRob Herring compatible = "renesas,hscif-r8a7793", 916*724ba675SRob Herring "renesas,rcar-gen2-hscif", "renesas,hscif"; 917*724ba675SRob Herring reg = <0 0xe62d0000 0 96>; 918*724ba675SRob Herring interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 919*724ba675SRob Herring clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 920*724ba675SRob Herring <&scif_clk>; 921*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 922*724ba675SRob Herring dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, 923*724ba675SRob Herring <&dmac1 0x3b>, <&dmac1 0x3c>; 924*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 925*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 926*724ba675SRob Herring resets = <&cpg 713>; 927*724ba675SRob Herring status = "disabled"; 928*724ba675SRob Herring }; 929*724ba675SRob Herring 930*724ba675SRob Herring can0: can@e6e80000 { 931*724ba675SRob Herring compatible = "renesas,can-r8a7793", 932*724ba675SRob Herring "renesas,rcar-gen2-can"; 933*724ba675SRob Herring reg = <0 0xe6e80000 0 0x1000>; 934*724ba675SRob Herring interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 935*724ba675SRob Herring clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, 936*724ba675SRob Herring <&can_clk>; 937*724ba675SRob Herring clock-names = "clkp1", "clkp2", "can_clk"; 938*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 939*724ba675SRob Herring resets = <&cpg 916>; 940*724ba675SRob Herring status = "disabled"; 941*724ba675SRob Herring }; 942*724ba675SRob Herring 943*724ba675SRob Herring can1: can@e6e88000 { 944*724ba675SRob Herring compatible = "renesas,can-r8a7793", 945*724ba675SRob Herring "renesas,rcar-gen2-can"; 946*724ba675SRob Herring reg = <0 0xe6e88000 0 0x1000>; 947*724ba675SRob Herring interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 948*724ba675SRob Herring clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, 949*724ba675SRob Herring <&can_clk>; 950*724ba675SRob Herring clock-names = "clkp1", "clkp2", "can_clk"; 951*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 952*724ba675SRob Herring resets = <&cpg 915>; 953*724ba675SRob Herring status = "disabled"; 954*724ba675SRob Herring }; 955*724ba675SRob Herring 956*724ba675SRob Herring vin0: video@e6ef0000 { 957*724ba675SRob Herring compatible = "renesas,vin-r8a7793", 958*724ba675SRob Herring "renesas,rcar-gen2-vin"; 959*724ba675SRob Herring reg = <0 0xe6ef0000 0 0x1000>; 960*724ba675SRob Herring interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 961*724ba675SRob Herring clocks = <&cpg CPG_MOD 811>; 962*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 963*724ba675SRob Herring resets = <&cpg 811>; 964*724ba675SRob Herring status = "disabled"; 965*724ba675SRob Herring }; 966*724ba675SRob Herring 967*724ba675SRob Herring vin1: video@e6ef1000 { 968*724ba675SRob Herring compatible = "renesas,vin-r8a7793", 969*724ba675SRob Herring "renesas,rcar-gen2-vin"; 970*724ba675SRob Herring reg = <0 0xe6ef1000 0 0x1000>; 971*724ba675SRob Herring interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 972*724ba675SRob Herring clocks = <&cpg CPG_MOD 810>; 973*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 974*724ba675SRob Herring resets = <&cpg 810>; 975*724ba675SRob Herring status = "disabled"; 976*724ba675SRob Herring }; 977*724ba675SRob Herring 978*724ba675SRob Herring vin2: video@e6ef2000 { 979*724ba675SRob Herring compatible = "renesas,vin-r8a7793", 980*724ba675SRob Herring "renesas,rcar-gen2-vin"; 981*724ba675SRob Herring reg = <0 0xe6ef2000 0 0x1000>; 982*724ba675SRob Herring interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 983*724ba675SRob Herring clocks = <&cpg CPG_MOD 809>; 984*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 985*724ba675SRob Herring resets = <&cpg 809>; 986*724ba675SRob Herring status = "disabled"; 987*724ba675SRob Herring }; 988*724ba675SRob Herring 989*724ba675SRob Herring rcar_sound: sound@ec500000 { 990*724ba675SRob Herring /* 991*724ba675SRob Herring * #sound-dai-cells is required if simple-card 992*724ba675SRob Herring * 993*724ba675SRob Herring * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 994*724ba675SRob Herring * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 995*724ba675SRob Herring */ 996*724ba675SRob Herring compatible = "renesas,rcar_sound-r8a7793", 997*724ba675SRob Herring "renesas,rcar_sound-gen2"; 998*724ba675SRob Herring reg = <0 0xec500000 0 0x1000>, /* SCU */ 999*724ba675SRob Herring <0 0xec5a0000 0 0x100>, /* ADG */ 1000*724ba675SRob Herring <0 0xec540000 0 0x1000>, /* SSIU */ 1001*724ba675SRob Herring <0 0xec541000 0 0x280>, /* SSI */ 1002*724ba675SRob Herring <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1003*724ba675SRob Herring reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1004*724ba675SRob Herring 1005*724ba675SRob Herring clocks = <&cpg CPG_MOD 1005>, 1006*724ba675SRob Herring <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1007*724ba675SRob Herring <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1008*724ba675SRob Herring <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1009*724ba675SRob Herring <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1010*724ba675SRob Herring <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1011*724ba675SRob Herring <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1012*724ba675SRob Herring <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1013*724ba675SRob Herring <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1014*724ba675SRob Herring <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1015*724ba675SRob Herring <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1016*724ba675SRob Herring <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1017*724ba675SRob Herring <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, 1018*724ba675SRob Herring <&cpg CPG_CORE R8A7793_CLK_M2>; 1019*724ba675SRob Herring clock-names = "ssi-all", 1020*724ba675SRob Herring "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1021*724ba675SRob Herring "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1022*724ba675SRob Herring "ssi.1", "ssi.0", 1023*724ba675SRob Herring "src.9", "src.8", "src.7", "src.6", 1024*724ba675SRob Herring "src.5", "src.4", "src.3", "src.2", 1025*724ba675SRob Herring "src.1", "src.0", 1026*724ba675SRob Herring "dvc.0", "dvc.1", 1027*724ba675SRob Herring "clk_a", "clk_b", "clk_c", "clk_i"; 1028*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1029*724ba675SRob Herring resets = <&cpg 1005>, 1030*724ba675SRob Herring <&cpg 1006>, <&cpg 1007>, 1031*724ba675SRob Herring <&cpg 1008>, <&cpg 1009>, 1032*724ba675SRob Herring <&cpg 1010>, <&cpg 1011>, 1033*724ba675SRob Herring <&cpg 1012>, <&cpg 1013>, 1034*724ba675SRob Herring <&cpg 1014>, <&cpg 1015>; 1035*724ba675SRob Herring reset-names = "ssi-all", 1036*724ba675SRob Herring "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1037*724ba675SRob Herring "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1038*724ba675SRob Herring "ssi.1", "ssi.0"; 1039*724ba675SRob Herring 1040*724ba675SRob Herring status = "disabled"; 1041*724ba675SRob Herring 1042*724ba675SRob Herring rcar_sound,dvc { 1043*724ba675SRob Herring dvc0: dvc-0 { 1044*724ba675SRob Herring dmas = <&audma1 0xbc>; 1045*724ba675SRob Herring dma-names = "tx"; 1046*724ba675SRob Herring }; 1047*724ba675SRob Herring dvc1: dvc-1 { 1048*724ba675SRob Herring dmas = <&audma1 0xbe>; 1049*724ba675SRob Herring dma-names = "tx"; 1050*724ba675SRob Herring }; 1051*724ba675SRob Herring }; 1052*724ba675SRob Herring 1053*724ba675SRob Herring rcar_sound,src { 1054*724ba675SRob Herring src0: src-0 { 1055*724ba675SRob Herring interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1056*724ba675SRob Herring dmas = <&audma0 0x85>, <&audma1 0x9a>; 1057*724ba675SRob Herring dma-names = "rx", "tx"; 1058*724ba675SRob Herring }; 1059*724ba675SRob Herring src1: src-1 { 1060*724ba675SRob Herring interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1061*724ba675SRob Herring dmas = <&audma0 0x87>, <&audma1 0x9c>; 1062*724ba675SRob Herring dma-names = "rx", "tx"; 1063*724ba675SRob Herring }; 1064*724ba675SRob Herring src2: src-2 { 1065*724ba675SRob Herring interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1066*724ba675SRob Herring dmas = <&audma0 0x89>, <&audma1 0x9e>; 1067*724ba675SRob Herring dma-names = "rx", "tx"; 1068*724ba675SRob Herring }; 1069*724ba675SRob Herring src3: src-3 { 1070*724ba675SRob Herring interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1071*724ba675SRob Herring dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1072*724ba675SRob Herring dma-names = "rx", "tx"; 1073*724ba675SRob Herring }; 1074*724ba675SRob Herring src4: src-4 { 1075*724ba675SRob Herring interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1076*724ba675SRob Herring dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1077*724ba675SRob Herring dma-names = "rx", "tx"; 1078*724ba675SRob Herring }; 1079*724ba675SRob Herring src5: src-5 { 1080*724ba675SRob Herring interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1081*724ba675SRob Herring dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1082*724ba675SRob Herring dma-names = "rx", "tx"; 1083*724ba675SRob Herring }; 1084*724ba675SRob Herring src6: src-6 { 1085*724ba675SRob Herring interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1086*724ba675SRob Herring dmas = <&audma0 0x91>, <&audma1 0xb4>; 1087*724ba675SRob Herring dma-names = "rx", "tx"; 1088*724ba675SRob Herring }; 1089*724ba675SRob Herring src7: src-7 { 1090*724ba675SRob Herring interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1091*724ba675SRob Herring dmas = <&audma0 0x93>, <&audma1 0xb6>; 1092*724ba675SRob Herring dma-names = "rx", "tx"; 1093*724ba675SRob Herring }; 1094*724ba675SRob Herring src8: src-8 { 1095*724ba675SRob Herring interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1096*724ba675SRob Herring dmas = <&audma0 0x95>, <&audma1 0xb8>; 1097*724ba675SRob Herring dma-names = "rx", "tx"; 1098*724ba675SRob Herring }; 1099*724ba675SRob Herring src9: src-9 { 1100*724ba675SRob Herring interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1101*724ba675SRob Herring dmas = <&audma0 0x97>, <&audma1 0xba>; 1102*724ba675SRob Herring dma-names = "rx", "tx"; 1103*724ba675SRob Herring }; 1104*724ba675SRob Herring }; 1105*724ba675SRob Herring 1106*724ba675SRob Herring rcar_sound,ssi { 1107*724ba675SRob Herring ssi0: ssi-0 { 1108*724ba675SRob Herring interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1109*724ba675SRob Herring dmas = <&audma0 0x01>, <&audma1 0x02>, 1110*724ba675SRob Herring <&audma0 0x15>, <&audma1 0x16>; 1111*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1112*724ba675SRob Herring }; 1113*724ba675SRob Herring ssi1: ssi-1 { 1114*724ba675SRob Herring interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1115*724ba675SRob Herring dmas = <&audma0 0x03>, <&audma1 0x04>, 1116*724ba675SRob Herring <&audma0 0x49>, <&audma1 0x4a>; 1117*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1118*724ba675SRob Herring }; 1119*724ba675SRob Herring ssi2: ssi-2 { 1120*724ba675SRob Herring interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1121*724ba675SRob Herring dmas = <&audma0 0x05>, <&audma1 0x06>, 1122*724ba675SRob Herring <&audma0 0x63>, <&audma1 0x64>; 1123*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1124*724ba675SRob Herring }; 1125*724ba675SRob Herring ssi3: ssi-3 { 1126*724ba675SRob Herring interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1127*724ba675SRob Herring dmas = <&audma0 0x07>, <&audma1 0x08>, 1128*724ba675SRob Herring <&audma0 0x6f>, <&audma1 0x70>; 1129*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1130*724ba675SRob Herring }; 1131*724ba675SRob Herring ssi4: ssi-4 { 1132*724ba675SRob Herring interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1133*724ba675SRob Herring dmas = <&audma0 0x09>, <&audma1 0x0a>, 1134*724ba675SRob Herring <&audma0 0x71>, <&audma1 0x72>; 1135*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1136*724ba675SRob Herring }; 1137*724ba675SRob Herring ssi5: ssi-5 { 1138*724ba675SRob Herring interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1139*724ba675SRob Herring dmas = <&audma0 0x0b>, <&audma1 0x0c>, 1140*724ba675SRob Herring <&audma0 0x73>, <&audma1 0x74>; 1141*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1142*724ba675SRob Herring }; 1143*724ba675SRob Herring ssi6: ssi-6 { 1144*724ba675SRob Herring interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1145*724ba675SRob Herring dmas = <&audma0 0x0d>, <&audma1 0x0e>, 1146*724ba675SRob Herring <&audma0 0x75>, <&audma1 0x76>; 1147*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1148*724ba675SRob Herring }; 1149*724ba675SRob Herring ssi7: ssi-7 { 1150*724ba675SRob Herring interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1151*724ba675SRob Herring dmas = <&audma0 0x0f>, <&audma1 0x10>, 1152*724ba675SRob Herring <&audma0 0x79>, <&audma1 0x7a>; 1153*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1154*724ba675SRob Herring }; 1155*724ba675SRob Herring ssi8: ssi-8 { 1156*724ba675SRob Herring interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1157*724ba675SRob Herring dmas = <&audma0 0x11>, <&audma1 0x12>, 1158*724ba675SRob Herring <&audma0 0x7b>, <&audma1 0x7c>; 1159*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1160*724ba675SRob Herring }; 1161*724ba675SRob Herring ssi9: ssi-9 { 1162*724ba675SRob Herring interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1163*724ba675SRob Herring dmas = <&audma0 0x13>, <&audma1 0x14>, 1164*724ba675SRob Herring <&audma0 0x7d>, <&audma1 0x7e>; 1165*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1166*724ba675SRob Herring }; 1167*724ba675SRob Herring }; 1168*724ba675SRob Herring }; 1169*724ba675SRob Herring 1170*724ba675SRob Herring audma0: dma-controller@ec700000 { 1171*724ba675SRob Herring compatible = "renesas,dmac-r8a7793", 1172*724ba675SRob Herring "renesas,rcar-dmac"; 1173*724ba675SRob Herring reg = <0 0xec700000 0 0x10000>; 1174*724ba675SRob Herring interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 1175*724ba675SRob Herring <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1176*724ba675SRob Herring <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1177*724ba675SRob Herring <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1178*724ba675SRob Herring <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1179*724ba675SRob Herring <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1180*724ba675SRob Herring <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1181*724ba675SRob Herring <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1182*724ba675SRob Herring <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1183*724ba675SRob Herring <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1184*724ba675SRob Herring <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1185*724ba675SRob Herring <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1186*724ba675SRob Herring <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1187*724ba675SRob Herring <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1188*724ba675SRob Herring interrupt-names = "error", 1189*724ba675SRob Herring "ch0", "ch1", "ch2", "ch3", 1190*724ba675SRob Herring "ch4", "ch5", "ch6", "ch7", 1191*724ba675SRob Herring "ch8", "ch9", "ch10", "ch11", 1192*724ba675SRob Herring "ch12"; 1193*724ba675SRob Herring clocks = <&cpg CPG_MOD 502>; 1194*724ba675SRob Herring clock-names = "fck"; 1195*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1196*724ba675SRob Herring resets = <&cpg 502>; 1197*724ba675SRob Herring #dma-cells = <1>; 1198*724ba675SRob Herring dma-channels = <13>; 1199*724ba675SRob Herring }; 1200*724ba675SRob Herring 1201*724ba675SRob Herring audma1: dma-controller@ec720000 { 1202*724ba675SRob Herring compatible = "renesas,dmac-r8a7793", 1203*724ba675SRob Herring "renesas,rcar-dmac"; 1204*724ba675SRob Herring reg = <0 0xec720000 0 0x10000>; 1205*724ba675SRob Herring interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1206*724ba675SRob Herring <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1207*724ba675SRob Herring <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1208*724ba675SRob Herring <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1209*724ba675SRob Herring <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1210*724ba675SRob Herring <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1211*724ba675SRob Herring <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1212*724ba675SRob Herring <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1213*724ba675SRob Herring <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1214*724ba675SRob Herring <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1215*724ba675SRob Herring <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1216*724ba675SRob Herring <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1217*724ba675SRob Herring <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1218*724ba675SRob Herring <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 1219*724ba675SRob Herring interrupt-names = "error", 1220*724ba675SRob Herring "ch0", "ch1", "ch2", "ch3", 1221*724ba675SRob Herring "ch4", "ch5", "ch6", "ch7", 1222*724ba675SRob Herring "ch8", "ch9", "ch10", "ch11", 1223*724ba675SRob Herring "ch12"; 1224*724ba675SRob Herring clocks = <&cpg CPG_MOD 501>; 1225*724ba675SRob Herring clock-names = "fck"; 1226*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1227*724ba675SRob Herring resets = <&cpg 501>; 1228*724ba675SRob Herring #dma-cells = <1>; 1229*724ba675SRob Herring dma-channels = <13>; 1230*724ba675SRob Herring }; 1231*724ba675SRob Herring 1232*724ba675SRob Herring sdhi0: mmc@ee100000 { 1233*724ba675SRob Herring compatible = "renesas,sdhi-r8a7793", 1234*724ba675SRob Herring "renesas,rcar-gen2-sdhi"; 1235*724ba675SRob Herring reg = <0 0xee100000 0 0x328>; 1236*724ba675SRob Herring interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1237*724ba675SRob Herring clocks = <&cpg CPG_MOD 314>; 1238*724ba675SRob Herring dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 1239*724ba675SRob Herring <&dmac1 0xcd>, <&dmac1 0xce>; 1240*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 1241*724ba675SRob Herring max-frequency = <195000000>; 1242*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1243*724ba675SRob Herring resets = <&cpg 314>; 1244*724ba675SRob Herring status = "disabled"; 1245*724ba675SRob Herring }; 1246*724ba675SRob Herring 1247*724ba675SRob Herring sdhi1: mmc@ee140000 { 1248*724ba675SRob Herring compatible = "renesas,sdhi-r8a7793", 1249*724ba675SRob Herring "renesas,rcar-gen2-sdhi"; 1250*724ba675SRob Herring reg = <0 0xee140000 0 0x100>; 1251*724ba675SRob Herring interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1252*724ba675SRob Herring clocks = <&cpg CPG_MOD 312>; 1253*724ba675SRob Herring dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, 1254*724ba675SRob Herring <&dmac1 0xc1>, <&dmac1 0xc2>; 1255*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 1256*724ba675SRob Herring max-frequency = <97500000>; 1257*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1258*724ba675SRob Herring resets = <&cpg 312>; 1259*724ba675SRob Herring status = "disabled"; 1260*724ba675SRob Herring }; 1261*724ba675SRob Herring 1262*724ba675SRob Herring sdhi2: mmc@ee160000 { 1263*724ba675SRob Herring compatible = "renesas,sdhi-r8a7793", 1264*724ba675SRob Herring "renesas,rcar-gen2-sdhi"; 1265*724ba675SRob Herring reg = <0 0xee160000 0 0x100>; 1266*724ba675SRob Herring interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1267*724ba675SRob Herring clocks = <&cpg CPG_MOD 311>; 1268*724ba675SRob Herring dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, 1269*724ba675SRob Herring <&dmac1 0xd3>, <&dmac1 0xd4>; 1270*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 1271*724ba675SRob Herring max-frequency = <97500000>; 1272*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1273*724ba675SRob Herring resets = <&cpg 311>; 1274*724ba675SRob Herring status = "disabled"; 1275*724ba675SRob Herring }; 1276*724ba675SRob Herring 1277*724ba675SRob Herring mmcif0: mmc@ee200000 { 1278*724ba675SRob Herring compatible = "renesas,mmcif-r8a7793", 1279*724ba675SRob Herring "renesas,sh-mmcif"; 1280*724ba675SRob Herring reg = <0 0xee200000 0 0x80>; 1281*724ba675SRob Herring interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1282*724ba675SRob Herring clocks = <&cpg CPG_MOD 315>; 1283*724ba675SRob Herring dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, 1284*724ba675SRob Herring <&dmac1 0xd1>, <&dmac1 0xd2>; 1285*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 1286*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1287*724ba675SRob Herring resets = <&cpg 315>; 1288*724ba675SRob Herring reg-io-width = <4>; 1289*724ba675SRob Herring status = "disabled"; 1290*724ba675SRob Herring max-frequency = <97500000>; 1291*724ba675SRob Herring }; 1292*724ba675SRob Herring 1293*724ba675SRob Herring ether: ethernet@ee700000 { 1294*724ba675SRob Herring compatible = "renesas,ether-r8a7793", 1295*724ba675SRob Herring "renesas,rcar-gen2-ether"; 1296*724ba675SRob Herring reg = <0 0xee700000 0 0x400>; 1297*724ba675SRob Herring interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1298*724ba675SRob Herring clocks = <&cpg CPG_MOD 813>; 1299*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1300*724ba675SRob Herring resets = <&cpg 813>; 1301*724ba675SRob Herring phy-mode = "rmii"; 1302*724ba675SRob Herring #address-cells = <1>; 1303*724ba675SRob Herring #size-cells = <0>; 1304*724ba675SRob Herring status = "disabled"; 1305*724ba675SRob Herring }; 1306*724ba675SRob Herring 1307*724ba675SRob Herring gic: interrupt-controller@f1001000 { 1308*724ba675SRob Herring compatible = "arm,gic-400"; 1309*724ba675SRob Herring #interrupt-cells = <3>; 1310*724ba675SRob Herring #address-cells = <0>; 1311*724ba675SRob Herring interrupt-controller; 1312*724ba675SRob Herring reg = <0 0xf1001000 0 0x1000>, 1313*724ba675SRob Herring <0 0xf1002000 0 0x2000>, 1314*724ba675SRob Herring <0 0xf1004000 0 0x2000>, 1315*724ba675SRob Herring <0 0xf1006000 0 0x2000>; 1316*724ba675SRob Herring interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 1317*724ba675SRob Herring clocks = <&cpg CPG_MOD 408>; 1318*724ba675SRob Herring clock-names = "clk"; 1319*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1320*724ba675SRob Herring resets = <&cpg 408>; 1321*724ba675SRob Herring }; 1322*724ba675SRob Herring 1323*724ba675SRob Herring fdp1@fe940000 { 1324*724ba675SRob Herring compatible = "renesas,fdp1"; 1325*724ba675SRob Herring reg = <0 0xfe940000 0 0x2400>; 1326*724ba675SRob Herring interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 1327*724ba675SRob Herring clocks = <&cpg CPG_MOD 119>; 1328*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1329*724ba675SRob Herring resets = <&cpg 119>; 1330*724ba675SRob Herring }; 1331*724ba675SRob Herring 1332*724ba675SRob Herring fdp1@fe944000 { 1333*724ba675SRob Herring compatible = "renesas,fdp1"; 1334*724ba675SRob Herring reg = <0 0xfe944000 0 0x2400>; 1335*724ba675SRob Herring interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1336*724ba675SRob Herring clocks = <&cpg CPG_MOD 118>; 1337*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1338*724ba675SRob Herring resets = <&cpg 118>; 1339*724ba675SRob Herring }; 1340*724ba675SRob Herring 1341*724ba675SRob Herring du: display@feb00000 { 1342*724ba675SRob Herring compatible = "renesas,du-r8a7793"; 1343*724ba675SRob Herring reg = <0 0xfeb00000 0 0x40000>; 1344*724ba675SRob Herring interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1345*724ba675SRob Herring <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1346*724ba675SRob Herring clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 1347*724ba675SRob Herring clock-names = "du.0", "du.1"; 1348*724ba675SRob Herring resets = <&cpg 724>; 1349*724ba675SRob Herring reset-names = "du.0"; 1350*724ba675SRob Herring status = "disabled"; 1351*724ba675SRob Herring 1352*724ba675SRob Herring ports { 1353*724ba675SRob Herring #address-cells = <1>; 1354*724ba675SRob Herring #size-cells = <0>; 1355*724ba675SRob Herring 1356*724ba675SRob Herring port@0 { 1357*724ba675SRob Herring reg = <0>; 1358*724ba675SRob Herring du_out_rgb: endpoint { 1359*724ba675SRob Herring }; 1360*724ba675SRob Herring }; 1361*724ba675SRob Herring port@1 { 1362*724ba675SRob Herring reg = <1>; 1363*724ba675SRob Herring du_out_lvds0: endpoint { 1364*724ba675SRob Herring remote-endpoint = <&lvds0_in>; 1365*724ba675SRob Herring }; 1366*724ba675SRob Herring }; 1367*724ba675SRob Herring }; 1368*724ba675SRob Herring }; 1369*724ba675SRob Herring 1370*724ba675SRob Herring lvds0: lvds@feb90000 { 1371*724ba675SRob Herring compatible = "renesas,r8a7793-lvds"; 1372*724ba675SRob Herring reg = <0 0xfeb90000 0 0x1c>; 1373*724ba675SRob Herring clocks = <&cpg CPG_MOD 726>; 1374*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1375*724ba675SRob Herring resets = <&cpg 726>; 1376*724ba675SRob Herring 1377*724ba675SRob Herring status = "disabled"; 1378*724ba675SRob Herring 1379*724ba675SRob Herring ports { 1380*724ba675SRob Herring #address-cells = <1>; 1381*724ba675SRob Herring #size-cells = <0>; 1382*724ba675SRob Herring 1383*724ba675SRob Herring port@0 { 1384*724ba675SRob Herring reg = <0>; 1385*724ba675SRob Herring lvds0_in: endpoint { 1386*724ba675SRob Herring remote-endpoint = <&du_out_lvds0>; 1387*724ba675SRob Herring }; 1388*724ba675SRob Herring }; 1389*724ba675SRob Herring port@1 { 1390*724ba675SRob Herring reg = <1>; 1391*724ba675SRob Herring lvds0_out: endpoint { 1392*724ba675SRob Herring }; 1393*724ba675SRob Herring }; 1394*724ba675SRob Herring }; 1395*724ba675SRob Herring }; 1396*724ba675SRob Herring 1397*724ba675SRob Herring prr: chipid@ff000044 { 1398*724ba675SRob Herring compatible = "renesas,prr"; 1399*724ba675SRob Herring reg = <0 0xff000044 0 4>; 1400*724ba675SRob Herring }; 1401*724ba675SRob Herring 1402*724ba675SRob Herring cmt0: timer@ffca0000 { 1403*724ba675SRob Herring compatible = "renesas,r8a7793-cmt0", 1404*724ba675SRob Herring "renesas,rcar-gen2-cmt0"; 1405*724ba675SRob Herring reg = <0 0xffca0000 0 0x1004>; 1406*724ba675SRob Herring interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1407*724ba675SRob Herring <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1408*724ba675SRob Herring clocks = <&cpg CPG_MOD 124>; 1409*724ba675SRob Herring clock-names = "fck"; 1410*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1411*724ba675SRob Herring resets = <&cpg 124>; 1412*724ba675SRob Herring 1413*724ba675SRob Herring status = "disabled"; 1414*724ba675SRob Herring }; 1415*724ba675SRob Herring 1416*724ba675SRob Herring cmt1: timer@e6130000 { 1417*724ba675SRob Herring compatible = "renesas,r8a7793-cmt1", 1418*724ba675SRob Herring "renesas,rcar-gen2-cmt1"; 1419*724ba675SRob Herring reg = <0 0xe6130000 0 0x1004>; 1420*724ba675SRob Herring interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1421*724ba675SRob Herring <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1422*724ba675SRob Herring <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1423*724ba675SRob Herring <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1424*724ba675SRob Herring <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1425*724ba675SRob Herring <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1426*724ba675SRob Herring <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1427*724ba675SRob Herring <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1428*724ba675SRob Herring clocks = <&cpg CPG_MOD 329>; 1429*724ba675SRob Herring clock-names = "fck"; 1430*724ba675SRob Herring power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1431*724ba675SRob Herring resets = <&cpg 329>; 1432*724ba675SRob Herring 1433*724ba675SRob Herring status = "disabled"; 1434*724ba675SRob Herring }; 1435*724ba675SRob Herring }; 1436*724ba675SRob Herring 1437*724ba675SRob Herring thermal-zones { 1438*724ba675SRob Herring cpu_thermal: cpu-thermal { 1439*724ba675SRob Herring polling-delay-passive = <0>; 1440*724ba675SRob Herring polling-delay = <0>; 1441*724ba675SRob Herring 1442*724ba675SRob Herring thermal-sensors = <&thermal>; 1443*724ba675SRob Herring 1444*724ba675SRob Herring trips { 1445*724ba675SRob Herring cpu-crit { 1446*724ba675SRob Herring temperature = <95000>; 1447*724ba675SRob Herring hysteresis = <0>; 1448*724ba675SRob Herring type = "critical"; 1449*724ba675SRob Herring }; 1450*724ba675SRob Herring }; 1451*724ba675SRob Herring cooling-maps { 1452*724ba675SRob Herring }; 1453*724ba675SRob Herring }; 1454*724ba675SRob Herring }; 1455*724ba675SRob Herring 1456*724ba675SRob Herring timer { 1457*724ba675SRob Herring compatible = "arm,armv7-timer"; 1458*724ba675SRob Herring interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1459*724ba675SRob Herring <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1460*724ba675SRob Herring <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1461*724ba675SRob Herring <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1462*724ba675SRob Herring }; 1463*724ba675SRob Herring 1464*724ba675SRob Herring /* External USB clock - can be overridden by the board */ 1465*724ba675SRob Herring usb_extal_clk: usb_extal { 1466*724ba675SRob Herring compatible = "fixed-clock"; 1467*724ba675SRob Herring #clock-cells = <0>; 1468*724ba675SRob Herring clock-frequency = <48000000>; 1469*724ba675SRob Herring }; 1470*724ba675SRob Herring}; 1471