1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree Source for the R-Car V2H (R8A77920) SoC 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2016 Cogent Embedded Inc. 6*724ba675SRob Herring */ 7*724ba675SRob Herring 8*724ba675SRob Herring#include <dt-bindings/clock/r8a7792-cpg-mssr.h> 9*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 10*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 11*724ba675SRob Herring#include <dt-bindings/power/r8a7792-sysc.h> 12*724ba675SRob Herring 13*724ba675SRob Herring/ { 14*724ba675SRob Herring compatible = "renesas,r8a7792"; 15*724ba675SRob Herring #address-cells = <2>; 16*724ba675SRob Herring #size-cells = <2>; 17*724ba675SRob Herring 18*724ba675SRob Herring aliases { 19*724ba675SRob Herring i2c0 = &i2c0; 20*724ba675SRob Herring i2c1 = &i2c1; 21*724ba675SRob Herring i2c2 = &i2c2; 22*724ba675SRob Herring i2c3 = &i2c3; 23*724ba675SRob Herring i2c4 = &i2c4; 24*724ba675SRob Herring i2c5 = &i2c5; 25*724ba675SRob Herring i2c6 = &iic3; 26*724ba675SRob Herring spi0 = &qspi; 27*724ba675SRob Herring spi1 = &msiof0; 28*724ba675SRob Herring spi2 = &msiof1; 29*724ba675SRob Herring vin0 = &vin0; 30*724ba675SRob Herring vin1 = &vin1; 31*724ba675SRob Herring vin2 = &vin2; 32*724ba675SRob Herring vin3 = &vin3; 33*724ba675SRob Herring vin4 = &vin4; 34*724ba675SRob Herring vin5 = &vin5; 35*724ba675SRob Herring }; 36*724ba675SRob Herring 37*724ba675SRob Herring /* External CAN clock */ 38*724ba675SRob Herring can_clk: can { 39*724ba675SRob Herring compatible = "fixed-clock"; 40*724ba675SRob Herring #clock-cells = <0>; 41*724ba675SRob Herring /* This value must be overridden by the board. */ 42*724ba675SRob Herring clock-frequency = <0>; 43*724ba675SRob Herring }; 44*724ba675SRob Herring 45*724ba675SRob Herring cpus { 46*724ba675SRob Herring #address-cells = <1>; 47*724ba675SRob Herring #size-cells = <0>; 48*724ba675SRob Herring 49*724ba675SRob Herring cpu0: cpu@0 { 50*724ba675SRob Herring device_type = "cpu"; 51*724ba675SRob Herring compatible = "arm,cortex-a15"; 52*724ba675SRob Herring reg = <0>; 53*724ba675SRob Herring clock-frequency = <1000000000>; 54*724ba675SRob Herring clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; 55*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_CA15_CPU0>; 56*724ba675SRob Herring enable-method = "renesas,apmu"; 57*724ba675SRob Herring next-level-cache = <&L2_CA15>; 58*724ba675SRob Herring }; 59*724ba675SRob Herring 60*724ba675SRob Herring cpu1: cpu@1 { 61*724ba675SRob Herring device_type = "cpu"; 62*724ba675SRob Herring compatible = "arm,cortex-a15"; 63*724ba675SRob Herring reg = <1>; 64*724ba675SRob Herring clock-frequency = <1000000000>; 65*724ba675SRob Herring clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; 66*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_CA15_CPU1>; 67*724ba675SRob Herring enable-method = "renesas,apmu"; 68*724ba675SRob Herring next-level-cache = <&L2_CA15>; 69*724ba675SRob Herring }; 70*724ba675SRob Herring 71*724ba675SRob Herring L2_CA15: cache-controller-0 { 72*724ba675SRob Herring compatible = "cache"; 73*724ba675SRob Herring cache-unified; 74*724ba675SRob Herring cache-level = <2>; 75*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_CA15_SCU>; 76*724ba675SRob Herring }; 77*724ba675SRob Herring }; 78*724ba675SRob Herring 79*724ba675SRob Herring /* External root clock */ 80*724ba675SRob Herring extal_clk: extal { 81*724ba675SRob Herring compatible = "fixed-clock"; 82*724ba675SRob Herring #clock-cells = <0>; 83*724ba675SRob Herring /* This value must be overridden by the board. */ 84*724ba675SRob Herring clock-frequency = <0>; 85*724ba675SRob Herring }; 86*724ba675SRob Herring 87*724ba675SRob Herring pmu { 88*724ba675SRob Herring compatible = "arm,cortex-a15-pmu"; 89*724ba675SRob Herring interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 90*724ba675SRob Herring <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 91*724ba675SRob Herring interrupt-affinity = <&cpu0>, <&cpu1>; 92*724ba675SRob Herring }; 93*724ba675SRob Herring 94*724ba675SRob Herring /* External SCIF clock */ 95*724ba675SRob Herring scif_clk: scif { 96*724ba675SRob Herring compatible = "fixed-clock"; 97*724ba675SRob Herring #clock-cells = <0>; 98*724ba675SRob Herring /* This value must be overridden by the board. */ 99*724ba675SRob Herring clock-frequency = <0>; 100*724ba675SRob Herring }; 101*724ba675SRob Herring 102*724ba675SRob Herring soc { 103*724ba675SRob Herring compatible = "simple-bus"; 104*724ba675SRob Herring interrupt-parent = <&gic>; 105*724ba675SRob Herring 106*724ba675SRob Herring #address-cells = <2>; 107*724ba675SRob Herring #size-cells = <2>; 108*724ba675SRob Herring ranges; 109*724ba675SRob Herring 110*724ba675SRob Herring rwdt: watchdog@e6020000 { 111*724ba675SRob Herring compatible = "renesas,r8a7792-wdt", 112*724ba675SRob Herring "renesas,rcar-gen2-wdt"; 113*724ba675SRob Herring reg = <0 0xe6020000 0 0x0c>; 114*724ba675SRob Herring interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 115*724ba675SRob Herring clocks = <&cpg CPG_MOD 402>; 116*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 117*724ba675SRob Herring resets = <&cpg 402>; 118*724ba675SRob Herring status = "disabled"; 119*724ba675SRob Herring }; 120*724ba675SRob Herring 121*724ba675SRob Herring gpio0: gpio@e6050000 { 122*724ba675SRob Herring compatible = "renesas,gpio-r8a7792", 123*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 124*724ba675SRob Herring reg = <0 0xe6050000 0 0x50>; 125*724ba675SRob Herring interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 126*724ba675SRob Herring #gpio-cells = <2>; 127*724ba675SRob Herring gpio-controller; 128*724ba675SRob Herring gpio-ranges = <&pfc 0 0 29>; 129*724ba675SRob Herring #interrupt-cells = <2>; 130*724ba675SRob Herring interrupt-controller; 131*724ba675SRob Herring clocks = <&cpg CPG_MOD 912>; 132*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 133*724ba675SRob Herring resets = <&cpg 912>; 134*724ba675SRob Herring }; 135*724ba675SRob Herring 136*724ba675SRob Herring gpio1: gpio@e6051000 { 137*724ba675SRob Herring compatible = "renesas,gpio-r8a7792", 138*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 139*724ba675SRob Herring reg = <0 0xe6051000 0 0x50>; 140*724ba675SRob Herring interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 141*724ba675SRob Herring #gpio-cells = <2>; 142*724ba675SRob Herring gpio-controller; 143*724ba675SRob Herring gpio-ranges = <&pfc 0 32 23>; 144*724ba675SRob Herring #interrupt-cells = <2>; 145*724ba675SRob Herring interrupt-controller; 146*724ba675SRob Herring clocks = <&cpg CPG_MOD 911>; 147*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 148*724ba675SRob Herring resets = <&cpg 911>; 149*724ba675SRob Herring }; 150*724ba675SRob Herring 151*724ba675SRob Herring gpio2: gpio@e6052000 { 152*724ba675SRob Herring compatible = "renesas,gpio-r8a7792", 153*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 154*724ba675SRob Herring reg = <0 0xe6052000 0 0x50>; 155*724ba675SRob Herring interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 156*724ba675SRob Herring #gpio-cells = <2>; 157*724ba675SRob Herring gpio-controller; 158*724ba675SRob Herring gpio-ranges = <&pfc 0 64 32>; 159*724ba675SRob Herring #interrupt-cells = <2>; 160*724ba675SRob Herring interrupt-controller; 161*724ba675SRob Herring clocks = <&cpg CPG_MOD 910>; 162*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 163*724ba675SRob Herring resets = <&cpg 910>; 164*724ba675SRob Herring }; 165*724ba675SRob Herring 166*724ba675SRob Herring gpio3: gpio@e6053000 { 167*724ba675SRob Herring compatible = "renesas,gpio-r8a7792", 168*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 169*724ba675SRob Herring reg = <0 0xe6053000 0 0x50>; 170*724ba675SRob Herring interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 171*724ba675SRob Herring #gpio-cells = <2>; 172*724ba675SRob Herring gpio-controller; 173*724ba675SRob Herring gpio-ranges = <&pfc 0 96 28>; 174*724ba675SRob Herring #interrupt-cells = <2>; 175*724ba675SRob Herring interrupt-controller; 176*724ba675SRob Herring clocks = <&cpg CPG_MOD 909>; 177*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 178*724ba675SRob Herring resets = <&cpg 909>; 179*724ba675SRob Herring }; 180*724ba675SRob Herring 181*724ba675SRob Herring gpio4: gpio@e6054000 { 182*724ba675SRob Herring compatible = "renesas,gpio-r8a7792", 183*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 184*724ba675SRob Herring reg = <0 0xe6054000 0 0x50>; 185*724ba675SRob Herring interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 186*724ba675SRob Herring #gpio-cells = <2>; 187*724ba675SRob Herring gpio-controller; 188*724ba675SRob Herring gpio-ranges = <&pfc 0 128 17>; 189*724ba675SRob Herring #interrupt-cells = <2>; 190*724ba675SRob Herring interrupt-controller; 191*724ba675SRob Herring clocks = <&cpg CPG_MOD 908>; 192*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 193*724ba675SRob Herring resets = <&cpg 908>; 194*724ba675SRob Herring }; 195*724ba675SRob Herring 196*724ba675SRob Herring gpio5: gpio@e6055000 { 197*724ba675SRob Herring compatible = "renesas,gpio-r8a7792", 198*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 199*724ba675SRob Herring reg = <0 0xe6055000 0 0x50>; 200*724ba675SRob Herring interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 201*724ba675SRob Herring #gpio-cells = <2>; 202*724ba675SRob Herring gpio-controller; 203*724ba675SRob Herring gpio-ranges = <&pfc 0 160 17>; 204*724ba675SRob Herring #interrupt-cells = <2>; 205*724ba675SRob Herring interrupt-controller; 206*724ba675SRob Herring clocks = <&cpg CPG_MOD 907>; 207*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 208*724ba675SRob Herring resets = <&cpg 907>; 209*724ba675SRob Herring }; 210*724ba675SRob Herring 211*724ba675SRob Herring gpio6: gpio@e6055100 { 212*724ba675SRob Herring compatible = "renesas,gpio-r8a7792", 213*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 214*724ba675SRob Herring reg = <0 0xe6055100 0 0x50>; 215*724ba675SRob Herring interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 216*724ba675SRob Herring #gpio-cells = <2>; 217*724ba675SRob Herring gpio-controller; 218*724ba675SRob Herring gpio-ranges = <&pfc 0 192 17>; 219*724ba675SRob Herring #interrupt-cells = <2>; 220*724ba675SRob Herring interrupt-controller; 221*724ba675SRob Herring clocks = <&cpg CPG_MOD 905>; 222*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 223*724ba675SRob Herring resets = <&cpg 905>; 224*724ba675SRob Herring }; 225*724ba675SRob Herring 226*724ba675SRob Herring gpio7: gpio@e6055200 { 227*724ba675SRob Herring compatible = "renesas,gpio-r8a7792", 228*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 229*724ba675SRob Herring reg = <0 0xe6055200 0 0x50>; 230*724ba675SRob Herring interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 231*724ba675SRob Herring #gpio-cells = <2>; 232*724ba675SRob Herring gpio-controller; 233*724ba675SRob Herring gpio-ranges = <&pfc 0 224 17>; 234*724ba675SRob Herring #interrupt-cells = <2>; 235*724ba675SRob Herring interrupt-controller; 236*724ba675SRob Herring clocks = <&cpg CPG_MOD 904>; 237*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 238*724ba675SRob Herring resets = <&cpg 904>; 239*724ba675SRob Herring }; 240*724ba675SRob Herring 241*724ba675SRob Herring gpio8: gpio@e6055300 { 242*724ba675SRob Herring compatible = "renesas,gpio-r8a7792", 243*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 244*724ba675SRob Herring reg = <0 0xe6055300 0 0x50>; 245*724ba675SRob Herring interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 246*724ba675SRob Herring #gpio-cells = <2>; 247*724ba675SRob Herring gpio-controller; 248*724ba675SRob Herring gpio-ranges = <&pfc 0 256 17>; 249*724ba675SRob Herring #interrupt-cells = <2>; 250*724ba675SRob Herring interrupt-controller; 251*724ba675SRob Herring clocks = <&cpg CPG_MOD 921>; 252*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 253*724ba675SRob Herring resets = <&cpg 921>; 254*724ba675SRob Herring }; 255*724ba675SRob Herring 256*724ba675SRob Herring gpio9: gpio@e6055400 { 257*724ba675SRob Herring compatible = "renesas,gpio-r8a7792", 258*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 259*724ba675SRob Herring reg = <0 0xe6055400 0 0x50>; 260*724ba675SRob Herring interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 261*724ba675SRob Herring #gpio-cells = <2>; 262*724ba675SRob Herring gpio-controller; 263*724ba675SRob Herring gpio-ranges = <&pfc 0 288 17>; 264*724ba675SRob Herring #interrupt-cells = <2>; 265*724ba675SRob Herring interrupt-controller; 266*724ba675SRob Herring clocks = <&cpg CPG_MOD 919>; 267*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 268*724ba675SRob Herring resets = <&cpg 919>; 269*724ba675SRob Herring }; 270*724ba675SRob Herring 271*724ba675SRob Herring gpio10: gpio@e6055500 { 272*724ba675SRob Herring compatible = "renesas,gpio-r8a7792", 273*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 274*724ba675SRob Herring reg = <0 0xe6055500 0 0x50>; 275*724ba675SRob Herring interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 276*724ba675SRob Herring #gpio-cells = <2>; 277*724ba675SRob Herring gpio-controller; 278*724ba675SRob Herring gpio-ranges = <&pfc 0 320 32>; 279*724ba675SRob Herring #interrupt-cells = <2>; 280*724ba675SRob Herring interrupt-controller; 281*724ba675SRob Herring clocks = <&cpg CPG_MOD 914>; 282*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 283*724ba675SRob Herring resets = <&cpg 914>; 284*724ba675SRob Herring }; 285*724ba675SRob Herring 286*724ba675SRob Herring gpio11: gpio@e6055600 { 287*724ba675SRob Herring compatible = "renesas,gpio-r8a7792", 288*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 289*724ba675SRob Herring reg = <0 0xe6055600 0 0x50>; 290*724ba675SRob Herring interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 291*724ba675SRob Herring #gpio-cells = <2>; 292*724ba675SRob Herring gpio-controller; 293*724ba675SRob Herring gpio-ranges = <&pfc 0 352 30>; 294*724ba675SRob Herring #interrupt-cells = <2>; 295*724ba675SRob Herring interrupt-controller; 296*724ba675SRob Herring clocks = <&cpg CPG_MOD 913>; 297*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 298*724ba675SRob Herring resets = <&cpg 913>; 299*724ba675SRob Herring }; 300*724ba675SRob Herring 301*724ba675SRob Herring pfc: pinctrl@e6060000 { 302*724ba675SRob Herring compatible = "renesas,pfc-r8a7792"; 303*724ba675SRob Herring reg = <0 0xe6060000 0 0x144>; 304*724ba675SRob Herring }; 305*724ba675SRob Herring 306*724ba675SRob Herring cpg: clock-controller@e6150000 { 307*724ba675SRob Herring compatible = "renesas,r8a7792-cpg-mssr"; 308*724ba675SRob Herring reg = <0 0xe6150000 0 0x1000>; 309*724ba675SRob Herring clocks = <&extal_clk>; 310*724ba675SRob Herring clock-names = "extal"; 311*724ba675SRob Herring #clock-cells = <2>; 312*724ba675SRob Herring #power-domain-cells = <0>; 313*724ba675SRob Herring #reset-cells = <1>; 314*724ba675SRob Herring }; 315*724ba675SRob Herring 316*724ba675SRob Herring apmu@e6152000 { 317*724ba675SRob Herring compatible = "renesas,r8a7792-apmu", "renesas,apmu"; 318*724ba675SRob Herring reg = <0 0xe6152000 0 0x188>; 319*724ba675SRob Herring cpus = <&cpu0>, <&cpu1>; 320*724ba675SRob Herring }; 321*724ba675SRob Herring 322*724ba675SRob Herring rst: reset-controller@e6160000 { 323*724ba675SRob Herring compatible = "renesas,r8a7792-rst"; 324*724ba675SRob Herring reg = <0 0xe6160000 0 0x0100>; 325*724ba675SRob Herring }; 326*724ba675SRob Herring 327*724ba675SRob Herring sysc: system-controller@e6180000 { 328*724ba675SRob Herring compatible = "renesas,r8a7792-sysc"; 329*724ba675SRob Herring reg = <0 0xe6180000 0 0x0200>; 330*724ba675SRob Herring #power-domain-cells = <1>; 331*724ba675SRob Herring }; 332*724ba675SRob Herring 333*724ba675SRob Herring irqc: interrupt-controller@e61c0000 { 334*724ba675SRob Herring compatible = "renesas,irqc-r8a7792", "renesas,irqc"; 335*724ba675SRob Herring #interrupt-cells = <2>; 336*724ba675SRob Herring interrupt-controller; 337*724ba675SRob Herring reg = <0 0xe61c0000 0 0x200>; 338*724ba675SRob Herring interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 339*724ba675SRob Herring <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 340*724ba675SRob Herring <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 341*724ba675SRob Herring <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 342*724ba675SRob Herring clocks = <&cpg CPG_MOD 407>; 343*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 344*724ba675SRob Herring resets = <&cpg 407>; 345*724ba675SRob Herring }; 346*724ba675SRob Herring 347*724ba675SRob Herring icram0: sram@e63a0000 { 348*724ba675SRob Herring compatible = "mmio-sram"; 349*724ba675SRob Herring reg = <0 0xe63a0000 0 0x12000>; 350*724ba675SRob Herring #address-cells = <1>; 351*724ba675SRob Herring #size-cells = <1>; 352*724ba675SRob Herring ranges = <0 0 0xe63a0000 0x12000>; 353*724ba675SRob Herring }; 354*724ba675SRob Herring 355*724ba675SRob Herring icram1: sram@e63c0000 { 356*724ba675SRob Herring compatible = "mmio-sram"; 357*724ba675SRob Herring reg = <0 0xe63c0000 0 0x1000>; 358*724ba675SRob Herring #address-cells = <1>; 359*724ba675SRob Herring #size-cells = <1>; 360*724ba675SRob Herring ranges = <0 0 0xe63c0000 0x1000>; 361*724ba675SRob Herring 362*724ba675SRob Herring smp-sram@0 { 363*724ba675SRob Herring compatible = "renesas,smp-sram"; 364*724ba675SRob Herring reg = <0 0x100>; 365*724ba675SRob Herring }; 366*724ba675SRob Herring }; 367*724ba675SRob Herring 368*724ba675SRob Herring /* I2C doesn't need pinmux */ 369*724ba675SRob Herring i2c0: i2c@e6508000 { 370*724ba675SRob Herring compatible = "renesas,i2c-r8a7792", 371*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 372*724ba675SRob Herring reg = <0 0xe6508000 0 0x40>; 373*724ba675SRob Herring interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 374*724ba675SRob Herring clocks = <&cpg CPG_MOD 931>; 375*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 376*724ba675SRob Herring resets = <&cpg 931>; 377*724ba675SRob Herring i2c-scl-internal-delay-ns = <6>; 378*724ba675SRob Herring #address-cells = <1>; 379*724ba675SRob Herring #size-cells = <0>; 380*724ba675SRob Herring status = "disabled"; 381*724ba675SRob Herring }; 382*724ba675SRob Herring 383*724ba675SRob Herring i2c1: i2c@e6518000 { 384*724ba675SRob Herring compatible = "renesas,i2c-r8a7792", 385*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 386*724ba675SRob Herring reg = <0 0xe6518000 0 0x40>; 387*724ba675SRob Herring interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 388*724ba675SRob Herring clocks = <&cpg CPG_MOD 930>; 389*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 390*724ba675SRob Herring resets = <&cpg 930>; 391*724ba675SRob Herring i2c-scl-internal-delay-ns = <6>; 392*724ba675SRob Herring #address-cells = <1>; 393*724ba675SRob Herring #size-cells = <0>; 394*724ba675SRob Herring status = "disabled"; 395*724ba675SRob Herring }; 396*724ba675SRob Herring 397*724ba675SRob Herring i2c2: i2c@e6530000 { 398*724ba675SRob Herring compatible = "renesas,i2c-r8a7792", 399*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 400*724ba675SRob Herring reg = <0 0xe6530000 0 0x40>; 401*724ba675SRob Herring interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 402*724ba675SRob Herring clocks = <&cpg CPG_MOD 929>; 403*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 404*724ba675SRob Herring resets = <&cpg 929>; 405*724ba675SRob Herring i2c-scl-internal-delay-ns = <6>; 406*724ba675SRob Herring #address-cells = <1>; 407*724ba675SRob Herring #size-cells = <0>; 408*724ba675SRob Herring status = "disabled"; 409*724ba675SRob Herring }; 410*724ba675SRob Herring 411*724ba675SRob Herring i2c3: i2c@e6540000 { 412*724ba675SRob Herring compatible = "renesas,i2c-r8a7792", 413*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 414*724ba675SRob Herring reg = <0 0xe6540000 0 0x40>; 415*724ba675SRob Herring interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 416*724ba675SRob Herring clocks = <&cpg CPG_MOD 928>; 417*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 418*724ba675SRob Herring resets = <&cpg 928>; 419*724ba675SRob Herring i2c-scl-internal-delay-ns = <6>; 420*724ba675SRob Herring #address-cells = <1>; 421*724ba675SRob Herring #size-cells = <0>; 422*724ba675SRob Herring status = "disabled"; 423*724ba675SRob Herring }; 424*724ba675SRob Herring 425*724ba675SRob Herring i2c4: i2c@e6520000 { 426*724ba675SRob Herring compatible = "renesas,i2c-r8a7792", 427*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 428*724ba675SRob Herring reg = <0 0xe6520000 0 0x40>; 429*724ba675SRob Herring interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 430*724ba675SRob Herring clocks = <&cpg CPG_MOD 927>; 431*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 432*724ba675SRob Herring resets = <&cpg 927>; 433*724ba675SRob Herring i2c-scl-internal-delay-ns = <6>; 434*724ba675SRob Herring #address-cells = <1>; 435*724ba675SRob Herring #size-cells = <0>; 436*724ba675SRob Herring status = "disabled"; 437*724ba675SRob Herring }; 438*724ba675SRob Herring 439*724ba675SRob Herring i2c5: i2c@e6528000 { 440*724ba675SRob Herring compatible = "renesas,i2c-r8a7792", 441*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 442*724ba675SRob Herring reg = <0 0xe6528000 0 0x40>; 443*724ba675SRob Herring interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 444*724ba675SRob Herring clocks = <&cpg CPG_MOD 925>; 445*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 446*724ba675SRob Herring resets = <&cpg 925>; 447*724ba675SRob Herring i2c-scl-internal-delay-ns = <110>; 448*724ba675SRob Herring #address-cells = <1>; 449*724ba675SRob Herring #size-cells = <0>; 450*724ba675SRob Herring status = "disabled"; 451*724ba675SRob Herring }; 452*724ba675SRob Herring 453*724ba675SRob Herring iic3: i2c@e60b0000 { 454*724ba675SRob Herring #address-cells = <1>; 455*724ba675SRob Herring #size-cells = <0>; 456*724ba675SRob Herring compatible = "renesas,iic-r8a7792", 457*724ba675SRob Herring "renesas,rcar-gen2-iic", 458*724ba675SRob Herring "renesas,rmobile-iic"; 459*724ba675SRob Herring reg = <0 0xe60b0000 0 0x425>; 460*724ba675SRob Herring interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 461*724ba675SRob Herring clocks = <&cpg CPG_MOD 926>; 462*724ba675SRob Herring dmas = <&dmac0 0x77>, <&dmac0 0x78>, 463*724ba675SRob Herring <&dmac1 0x77>, <&dmac1 0x78>; 464*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 465*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 466*724ba675SRob Herring resets = <&cpg 926>; 467*724ba675SRob Herring status = "disabled"; 468*724ba675SRob Herring }; 469*724ba675SRob Herring 470*724ba675SRob Herring dmac0: dma-controller@e6700000 { 471*724ba675SRob Herring compatible = "renesas,dmac-r8a7792", 472*724ba675SRob Herring "renesas,rcar-dmac"; 473*724ba675SRob Herring reg = <0 0xe6700000 0 0x20000>; 474*724ba675SRob Herring interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 475*724ba675SRob Herring <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 476*724ba675SRob Herring <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 477*724ba675SRob Herring <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 478*724ba675SRob Herring <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 479*724ba675SRob Herring <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 480*724ba675SRob Herring <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 481*724ba675SRob Herring <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 482*724ba675SRob Herring <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 483*724ba675SRob Herring <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 484*724ba675SRob Herring <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 485*724ba675SRob Herring <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 486*724ba675SRob Herring <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 487*724ba675SRob Herring <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 488*724ba675SRob Herring <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 489*724ba675SRob Herring <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 490*724ba675SRob Herring interrupt-names = "error", 491*724ba675SRob Herring "ch0", "ch1", "ch2", "ch3", 492*724ba675SRob Herring "ch4", "ch5", "ch6", "ch7", 493*724ba675SRob Herring "ch8", "ch9", "ch10", "ch11", 494*724ba675SRob Herring "ch12", "ch13", "ch14"; 495*724ba675SRob Herring clocks = <&cpg CPG_MOD 219>; 496*724ba675SRob Herring clock-names = "fck"; 497*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 498*724ba675SRob Herring resets = <&cpg 219>; 499*724ba675SRob Herring #dma-cells = <1>; 500*724ba675SRob Herring dma-channels = <15>; 501*724ba675SRob Herring }; 502*724ba675SRob Herring 503*724ba675SRob Herring dmac1: dma-controller@e6720000 { 504*724ba675SRob Herring compatible = "renesas,dmac-r8a7792", 505*724ba675SRob Herring "renesas,rcar-dmac"; 506*724ba675SRob Herring reg = <0 0xe6720000 0 0x20000>; 507*724ba675SRob Herring interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 508*724ba675SRob Herring <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 509*724ba675SRob Herring <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 510*724ba675SRob Herring <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 511*724ba675SRob Herring <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 512*724ba675SRob Herring <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 513*724ba675SRob Herring <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 514*724ba675SRob Herring <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 515*724ba675SRob Herring <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 516*724ba675SRob Herring <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 517*724ba675SRob Herring <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 518*724ba675SRob Herring <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 519*724ba675SRob Herring <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 520*724ba675SRob Herring <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 521*724ba675SRob Herring <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 522*724ba675SRob Herring <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 523*724ba675SRob Herring interrupt-names = "error", 524*724ba675SRob Herring "ch0", "ch1", "ch2", "ch3", 525*724ba675SRob Herring "ch4", "ch5", "ch6", "ch7", 526*724ba675SRob Herring "ch8", "ch9", "ch10", "ch11", 527*724ba675SRob Herring "ch12", "ch13", "ch14"; 528*724ba675SRob Herring clocks = <&cpg CPG_MOD 218>; 529*724ba675SRob Herring clock-names = "fck"; 530*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 531*724ba675SRob Herring resets = <&cpg 218>; 532*724ba675SRob Herring #dma-cells = <1>; 533*724ba675SRob Herring dma-channels = <15>; 534*724ba675SRob Herring }; 535*724ba675SRob Herring 536*724ba675SRob Herring avb: ethernet@e6800000 { 537*724ba675SRob Herring compatible = "renesas,etheravb-r8a7792", 538*724ba675SRob Herring "renesas,etheravb-rcar-gen2"; 539*724ba675SRob Herring reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 540*724ba675SRob Herring interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 541*724ba675SRob Herring clocks = <&cpg CPG_MOD 812>; 542*724ba675SRob Herring clock-names = "fck"; 543*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 544*724ba675SRob Herring resets = <&cpg 812>; 545*724ba675SRob Herring #address-cells = <1>; 546*724ba675SRob Herring #size-cells = <0>; 547*724ba675SRob Herring status = "disabled"; 548*724ba675SRob Herring }; 549*724ba675SRob Herring 550*724ba675SRob Herring qspi: spi@e6b10000 { 551*724ba675SRob Herring compatible = "renesas,qspi-r8a7792", "renesas,qspi"; 552*724ba675SRob Herring reg = <0 0xe6b10000 0 0x2c>; 553*724ba675SRob Herring interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 554*724ba675SRob Herring clocks = <&cpg CPG_MOD 917>; 555*724ba675SRob Herring dmas = <&dmac0 0x17>, <&dmac0 0x18>, 556*724ba675SRob Herring <&dmac1 0x17>, <&dmac1 0x18>; 557*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 558*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 559*724ba675SRob Herring resets = <&cpg 917>; 560*724ba675SRob Herring num-cs = <1>; 561*724ba675SRob Herring #address-cells = <1>; 562*724ba675SRob Herring #size-cells = <0>; 563*724ba675SRob Herring status = "disabled"; 564*724ba675SRob Herring }; 565*724ba675SRob Herring 566*724ba675SRob Herring scif0: serial@e6e60000 { 567*724ba675SRob Herring compatible = "renesas,scif-r8a7792", 568*724ba675SRob Herring "renesas,rcar-gen2-scif", "renesas,scif"; 569*724ba675SRob Herring reg = <0 0xe6e60000 0 64>; 570*724ba675SRob Herring interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 571*724ba675SRob Herring clocks = <&cpg CPG_MOD 721>, 572*724ba675SRob Herring <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 573*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 574*724ba675SRob Herring dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 575*724ba675SRob Herring <&dmac1 0x29>, <&dmac1 0x2a>; 576*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 577*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 578*724ba675SRob Herring resets = <&cpg 721>; 579*724ba675SRob Herring status = "disabled"; 580*724ba675SRob Herring }; 581*724ba675SRob Herring 582*724ba675SRob Herring scif1: serial@e6e68000 { 583*724ba675SRob Herring compatible = "renesas,scif-r8a7792", 584*724ba675SRob Herring "renesas,rcar-gen2-scif", "renesas,scif"; 585*724ba675SRob Herring reg = <0 0xe6e68000 0 64>; 586*724ba675SRob Herring interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 587*724ba675SRob Herring clocks = <&cpg CPG_MOD 720>, 588*724ba675SRob Herring <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 589*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 590*724ba675SRob Herring dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 591*724ba675SRob Herring <&dmac1 0x2d>, <&dmac1 0x2e>; 592*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 593*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 594*724ba675SRob Herring resets = <&cpg 720>; 595*724ba675SRob Herring status = "disabled"; 596*724ba675SRob Herring }; 597*724ba675SRob Herring 598*724ba675SRob Herring scif2: serial@e6e58000 { 599*724ba675SRob Herring compatible = "renesas,scif-r8a7792", 600*724ba675SRob Herring "renesas,rcar-gen2-scif", "renesas,scif"; 601*724ba675SRob Herring reg = <0 0xe6e58000 0 64>; 602*724ba675SRob Herring interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 603*724ba675SRob Herring clocks = <&cpg CPG_MOD 719>, 604*724ba675SRob Herring <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 605*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 606*724ba675SRob Herring dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 607*724ba675SRob Herring <&dmac1 0x2b>, <&dmac1 0x2c>; 608*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 609*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 610*724ba675SRob Herring resets = <&cpg 719>; 611*724ba675SRob Herring status = "disabled"; 612*724ba675SRob Herring }; 613*724ba675SRob Herring 614*724ba675SRob Herring scif3: serial@e6ea8000 { 615*724ba675SRob Herring compatible = "renesas,scif-r8a7792", 616*724ba675SRob Herring "renesas,rcar-gen2-scif", "renesas,scif"; 617*724ba675SRob Herring reg = <0 0xe6ea8000 0 64>; 618*724ba675SRob Herring interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 619*724ba675SRob Herring clocks = <&cpg CPG_MOD 718>, 620*724ba675SRob Herring <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 621*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 622*724ba675SRob Herring dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 623*724ba675SRob Herring <&dmac1 0x2f>, <&dmac1 0x30>; 624*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 625*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 626*724ba675SRob Herring resets = <&cpg 718>; 627*724ba675SRob Herring status = "disabled"; 628*724ba675SRob Herring }; 629*724ba675SRob Herring 630*724ba675SRob Herring hscif0: serial@e62c0000 { 631*724ba675SRob Herring compatible = "renesas,hscif-r8a7792", 632*724ba675SRob Herring "renesas,rcar-gen2-hscif", "renesas,hscif"; 633*724ba675SRob Herring reg = <0 0xe62c0000 0 96>; 634*724ba675SRob Herring interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 635*724ba675SRob Herring clocks = <&cpg CPG_MOD 717>, 636*724ba675SRob Herring <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 637*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 638*724ba675SRob Herring dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 639*724ba675SRob Herring <&dmac1 0x39>, <&dmac1 0x3a>; 640*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 641*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 642*724ba675SRob Herring resets = <&cpg 717>; 643*724ba675SRob Herring status = "disabled"; 644*724ba675SRob Herring }; 645*724ba675SRob Herring 646*724ba675SRob Herring hscif1: serial@e62c8000 { 647*724ba675SRob Herring compatible = "renesas,hscif-r8a7792", 648*724ba675SRob Herring "renesas,rcar-gen2-hscif", "renesas,hscif"; 649*724ba675SRob Herring reg = <0 0xe62c8000 0 96>; 650*724ba675SRob Herring interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 651*724ba675SRob Herring clocks = <&cpg CPG_MOD 716>, 652*724ba675SRob Herring <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 653*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 654*724ba675SRob Herring dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 655*724ba675SRob Herring <&dmac1 0x4d>, <&dmac1 0x4e>; 656*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 657*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 658*724ba675SRob Herring resets = <&cpg 716>; 659*724ba675SRob Herring status = "disabled"; 660*724ba675SRob Herring }; 661*724ba675SRob Herring 662*724ba675SRob Herring msiof0: spi@e6e20000 { 663*724ba675SRob Herring compatible = "renesas,msiof-r8a7792", 664*724ba675SRob Herring "renesas,rcar-gen2-msiof"; 665*724ba675SRob Herring reg = <0 0xe6e20000 0 0x0064>; 666*724ba675SRob Herring interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 667*724ba675SRob Herring clocks = <&cpg CPG_MOD 000>; 668*724ba675SRob Herring dmas = <&dmac0 0x51>, <&dmac0 0x52>, 669*724ba675SRob Herring <&dmac1 0x51>, <&dmac1 0x52>; 670*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 671*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 672*724ba675SRob Herring resets = <&cpg 000>; 673*724ba675SRob Herring #address-cells = <1>; 674*724ba675SRob Herring #size-cells = <0>; 675*724ba675SRob Herring status = "disabled"; 676*724ba675SRob Herring }; 677*724ba675SRob Herring 678*724ba675SRob Herring msiof1: spi@e6e10000 { 679*724ba675SRob Herring compatible = "renesas,msiof-r8a7792", 680*724ba675SRob Herring "renesas,rcar-gen2-msiof"; 681*724ba675SRob Herring reg = <0 0xe6e10000 0 0x0064>; 682*724ba675SRob Herring interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 683*724ba675SRob Herring clocks = <&cpg CPG_MOD 208>; 684*724ba675SRob Herring dmas = <&dmac0 0x55>, <&dmac0 0x56>, 685*724ba675SRob Herring <&dmac1 0x55>, <&dmac1 0x56>; 686*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 687*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 688*724ba675SRob Herring resets = <&cpg 208>; 689*724ba675SRob Herring #address-cells = <1>; 690*724ba675SRob Herring #size-cells = <0>; 691*724ba675SRob Herring status = "disabled"; 692*724ba675SRob Herring }; 693*724ba675SRob Herring 694*724ba675SRob Herring can0: can@e6e80000 { 695*724ba675SRob Herring compatible = "renesas,can-r8a7792", 696*724ba675SRob Herring "renesas,rcar-gen2-can"; 697*724ba675SRob Herring reg = <0 0xe6e80000 0 0x1000>; 698*724ba675SRob Herring interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 699*724ba675SRob Herring clocks = <&cpg CPG_MOD 916>, 700*724ba675SRob Herring <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; 701*724ba675SRob Herring clock-names = "clkp1", "clkp2", "can_clk"; 702*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 703*724ba675SRob Herring resets = <&cpg 916>; 704*724ba675SRob Herring status = "disabled"; 705*724ba675SRob Herring }; 706*724ba675SRob Herring 707*724ba675SRob Herring can1: can@e6e88000 { 708*724ba675SRob Herring compatible = "renesas,can-r8a7792", 709*724ba675SRob Herring "renesas,rcar-gen2-can"; 710*724ba675SRob Herring reg = <0 0xe6e88000 0 0x1000>; 711*724ba675SRob Herring interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 712*724ba675SRob Herring clocks = <&cpg CPG_MOD 915>, 713*724ba675SRob Herring <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; 714*724ba675SRob Herring clock-names = "clkp1", "clkp2", "can_clk"; 715*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 716*724ba675SRob Herring resets = <&cpg 915>; 717*724ba675SRob Herring status = "disabled"; 718*724ba675SRob Herring }; 719*724ba675SRob Herring 720*724ba675SRob Herring vin0: video@e6ef0000 { 721*724ba675SRob Herring compatible = "renesas,vin-r8a7792", 722*724ba675SRob Herring "renesas,rcar-gen2-vin"; 723*724ba675SRob Herring reg = <0 0xe6ef0000 0 0x1000>; 724*724ba675SRob Herring interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 725*724ba675SRob Herring clocks = <&cpg CPG_MOD 811>; 726*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 727*724ba675SRob Herring resets = <&cpg 811>; 728*724ba675SRob Herring status = "disabled"; 729*724ba675SRob Herring }; 730*724ba675SRob Herring 731*724ba675SRob Herring vin1: video@e6ef1000 { 732*724ba675SRob Herring compatible = "renesas,vin-r8a7792", 733*724ba675SRob Herring "renesas,rcar-gen2-vin"; 734*724ba675SRob Herring reg = <0 0xe6ef1000 0 0x1000>; 735*724ba675SRob Herring interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 736*724ba675SRob Herring clocks = <&cpg CPG_MOD 810>; 737*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 738*724ba675SRob Herring resets = <&cpg 810>; 739*724ba675SRob Herring status = "disabled"; 740*724ba675SRob Herring }; 741*724ba675SRob Herring 742*724ba675SRob Herring vin2: video@e6ef2000 { 743*724ba675SRob Herring compatible = "renesas,vin-r8a7792", 744*724ba675SRob Herring "renesas,rcar-gen2-vin"; 745*724ba675SRob Herring reg = <0 0xe6ef2000 0 0x1000>; 746*724ba675SRob Herring interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 747*724ba675SRob Herring clocks = <&cpg CPG_MOD 809>; 748*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 749*724ba675SRob Herring resets = <&cpg 809>; 750*724ba675SRob Herring status = "disabled"; 751*724ba675SRob Herring }; 752*724ba675SRob Herring 753*724ba675SRob Herring vin3: video@e6ef3000 { 754*724ba675SRob Herring compatible = "renesas,vin-r8a7792", 755*724ba675SRob Herring "renesas,rcar-gen2-vin"; 756*724ba675SRob Herring reg = <0 0xe6ef3000 0 0x1000>; 757*724ba675SRob Herring interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 758*724ba675SRob Herring clocks = <&cpg CPG_MOD 808>; 759*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 760*724ba675SRob Herring resets = <&cpg 808>; 761*724ba675SRob Herring status = "disabled"; 762*724ba675SRob Herring }; 763*724ba675SRob Herring 764*724ba675SRob Herring vin4: video@e6ef4000 { 765*724ba675SRob Herring compatible = "renesas,vin-r8a7792", 766*724ba675SRob Herring "renesas,rcar-gen2-vin"; 767*724ba675SRob Herring reg = <0 0xe6ef4000 0 0x1000>; 768*724ba675SRob Herring interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 769*724ba675SRob Herring clocks = <&cpg CPG_MOD 805>; 770*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 771*724ba675SRob Herring resets = <&cpg 805>; 772*724ba675SRob Herring status = "disabled"; 773*724ba675SRob Herring }; 774*724ba675SRob Herring 775*724ba675SRob Herring vin5: video@e6ef5000 { 776*724ba675SRob Herring compatible = "renesas,vin-r8a7792", 777*724ba675SRob Herring "renesas,rcar-gen2-vin"; 778*724ba675SRob Herring reg = <0 0xe6ef5000 0 0x1000>; 779*724ba675SRob Herring interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 780*724ba675SRob Herring clocks = <&cpg CPG_MOD 804>; 781*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 782*724ba675SRob Herring resets = <&cpg 804>; 783*724ba675SRob Herring status = "disabled"; 784*724ba675SRob Herring }; 785*724ba675SRob Herring 786*724ba675SRob Herring sdhi0: mmc@ee100000 { 787*724ba675SRob Herring compatible = "renesas,sdhi-r8a7792", 788*724ba675SRob Herring "renesas,rcar-gen2-sdhi"; 789*724ba675SRob Herring reg = <0 0xee100000 0 0x328>; 790*724ba675SRob Herring interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 791*724ba675SRob Herring dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 792*724ba675SRob Herring <&dmac1 0xcd>, <&dmac1 0xce>; 793*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 794*724ba675SRob Herring clocks = <&cpg CPG_MOD 314>; 795*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 796*724ba675SRob Herring resets = <&cpg 314>; 797*724ba675SRob Herring status = "disabled"; 798*724ba675SRob Herring }; 799*724ba675SRob Herring 800*724ba675SRob Herring gic: interrupt-controller@f1001000 { 801*724ba675SRob Herring compatible = "arm,gic-400"; 802*724ba675SRob Herring #interrupt-cells = <3>; 803*724ba675SRob Herring interrupt-controller; 804*724ba675SRob Herring reg = <0 0xf1001000 0 0x1000>, 805*724ba675SRob Herring <0 0xf1002000 0 0x2000>, 806*724ba675SRob Herring <0 0xf1004000 0 0x2000>, 807*724ba675SRob Herring <0 0xf1006000 0 0x2000>; 808*724ba675SRob Herring interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 809*724ba675SRob Herring IRQ_TYPE_LEVEL_HIGH)>; 810*724ba675SRob Herring clocks = <&cpg CPG_MOD 408>; 811*724ba675SRob Herring clock-names = "clk"; 812*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 813*724ba675SRob Herring resets = <&cpg 408>; 814*724ba675SRob Herring }; 815*724ba675SRob Herring 816*724ba675SRob Herring vsp@fe928000 { 817*724ba675SRob Herring compatible = "renesas,vsp1"; 818*724ba675SRob Herring reg = <0 0xfe928000 0 0x8000>; 819*724ba675SRob Herring interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 820*724ba675SRob Herring clocks = <&cpg CPG_MOD 131>; 821*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 822*724ba675SRob Herring resets = <&cpg 131>; 823*724ba675SRob Herring }; 824*724ba675SRob Herring 825*724ba675SRob Herring vsp@fe930000 { 826*724ba675SRob Herring compatible = "renesas,vsp1"; 827*724ba675SRob Herring reg = <0 0xfe930000 0 0x8000>; 828*724ba675SRob Herring interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 829*724ba675SRob Herring clocks = <&cpg CPG_MOD 128>; 830*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 831*724ba675SRob Herring resets = <&cpg 128>; 832*724ba675SRob Herring }; 833*724ba675SRob Herring 834*724ba675SRob Herring vsp@fe938000 { 835*724ba675SRob Herring compatible = "renesas,vsp1"; 836*724ba675SRob Herring reg = <0 0xfe938000 0 0x8000>; 837*724ba675SRob Herring interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 838*724ba675SRob Herring clocks = <&cpg CPG_MOD 127>; 839*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 840*724ba675SRob Herring resets = <&cpg 127>; 841*724ba675SRob Herring }; 842*724ba675SRob Herring 843*724ba675SRob Herring jpu: jpeg-codec@fe980000 { 844*724ba675SRob Herring compatible = "renesas,jpu-r8a7792", 845*724ba675SRob Herring "renesas,rcar-gen2-jpu"; 846*724ba675SRob Herring reg = <0 0xfe980000 0 0x10300>; 847*724ba675SRob Herring interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 848*724ba675SRob Herring clocks = <&cpg CPG_MOD 106>; 849*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 850*724ba675SRob Herring resets = <&cpg 106>; 851*724ba675SRob Herring }; 852*724ba675SRob Herring 853*724ba675SRob Herring du: display@feb00000 { 854*724ba675SRob Herring compatible = "renesas,du-r8a7792"; 855*724ba675SRob Herring reg = <0 0xfeb00000 0 0x40000>; 856*724ba675SRob Herring interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 857*724ba675SRob Herring <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 858*724ba675SRob Herring clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 859*724ba675SRob Herring clock-names = "du.0", "du.1"; 860*724ba675SRob Herring resets = <&cpg 724>; 861*724ba675SRob Herring reset-names = "du.0"; 862*724ba675SRob Herring status = "disabled"; 863*724ba675SRob Herring 864*724ba675SRob Herring ports { 865*724ba675SRob Herring #address-cells = <1>; 866*724ba675SRob Herring #size-cells = <0>; 867*724ba675SRob Herring 868*724ba675SRob Herring port@0 { 869*724ba675SRob Herring reg = <0>; 870*724ba675SRob Herring du_out_rgb0: endpoint { 871*724ba675SRob Herring }; 872*724ba675SRob Herring }; 873*724ba675SRob Herring port@1 { 874*724ba675SRob Herring reg = <1>; 875*724ba675SRob Herring du_out_rgb1: endpoint { 876*724ba675SRob Herring }; 877*724ba675SRob Herring }; 878*724ba675SRob Herring }; 879*724ba675SRob Herring }; 880*724ba675SRob Herring 881*724ba675SRob Herring prr: chipid@ff000044 { 882*724ba675SRob Herring compatible = "renesas,prr"; 883*724ba675SRob Herring reg = <0 0xff000044 0 4>; 884*724ba675SRob Herring }; 885*724ba675SRob Herring 886*724ba675SRob Herring cmt0: timer@ffca0000 { 887*724ba675SRob Herring compatible = "renesas,r8a7792-cmt0", 888*724ba675SRob Herring "renesas,rcar-gen2-cmt0"; 889*724ba675SRob Herring reg = <0 0xffca0000 0 0x1004>; 890*724ba675SRob Herring interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 891*724ba675SRob Herring <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 892*724ba675SRob Herring clocks = <&cpg CPG_MOD 124>; 893*724ba675SRob Herring clock-names = "fck"; 894*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 895*724ba675SRob Herring resets = <&cpg 124>; 896*724ba675SRob Herring 897*724ba675SRob Herring status = "disabled"; 898*724ba675SRob Herring }; 899*724ba675SRob Herring 900*724ba675SRob Herring cmt1: timer@e6130000 { 901*724ba675SRob Herring compatible = "renesas,r8a7792-cmt1", 902*724ba675SRob Herring "renesas,rcar-gen2-cmt1"; 903*724ba675SRob Herring reg = <0 0xe6130000 0 0x1004>; 904*724ba675SRob Herring interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 905*724ba675SRob Herring <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 906*724ba675SRob Herring <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 907*724ba675SRob Herring <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 908*724ba675SRob Herring <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 909*724ba675SRob Herring <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 910*724ba675SRob Herring <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 911*724ba675SRob Herring <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 912*724ba675SRob Herring clocks = <&cpg CPG_MOD 329>; 913*724ba675SRob Herring clock-names = "fck"; 914*724ba675SRob Herring power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 915*724ba675SRob Herring resets = <&cpg 329>; 916*724ba675SRob Herring 917*724ba675SRob Herring status = "disabled"; 918*724ba675SRob Herring }; 919*724ba675SRob Herring }; 920*724ba675SRob Herring 921*724ba675SRob Herring timer { 922*724ba675SRob Herring compatible = "arm,armv7-timer"; 923*724ba675SRob Herring interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 924*724ba675SRob Herring <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 925*724ba675SRob Herring <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 926*724ba675SRob Herring <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 927*724ba675SRob Herring }; 928*724ba675SRob Herring}; 929