1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree Source for the R-Car M1A (R8A77781) SoC 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2013 Renesas Solutions Corp. 6*724ba675SRob Herring * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 7*724ba675SRob Herring * 8*724ba675SRob Herring * based on r8a7779 9*724ba675SRob Herring * 10*724ba675SRob Herring * Copyright (C) 2013 Renesas Solutions Corp. 11*724ba675SRob Herring * Copyright (C) 2013 Simon Horman 12*724ba675SRob Herring */ 13*724ba675SRob Herring 14*724ba675SRob Herring#include <dt-bindings/clock/r8a7778-clock.h> 15*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 16*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 17*724ba675SRob Herring 18*724ba675SRob Herring/ { 19*724ba675SRob Herring compatible = "renesas,r8a7778"; 20*724ba675SRob Herring interrupt-parent = <&gic>; 21*724ba675SRob Herring #address-cells = <1>; 22*724ba675SRob Herring #size-cells = <1>; 23*724ba675SRob Herring 24*724ba675SRob Herring cpus { 25*724ba675SRob Herring #address-cells = <1>; 26*724ba675SRob Herring #size-cells = <0>; 27*724ba675SRob Herring 28*724ba675SRob Herring cpu@0 { 29*724ba675SRob Herring device_type = "cpu"; 30*724ba675SRob Herring compatible = "arm,cortex-a9"; 31*724ba675SRob Herring reg = <0>; 32*724ba675SRob Herring clock-frequency = <800000000>; 33*724ba675SRob Herring clocks = <&z_clk>; 34*724ba675SRob Herring }; 35*724ba675SRob Herring }; 36*724ba675SRob Herring 37*724ba675SRob Herring aliases { 38*724ba675SRob Herring spi0 = &hspi0; 39*724ba675SRob Herring spi1 = &hspi1; 40*724ba675SRob Herring spi2 = &hspi2; 41*724ba675SRob Herring }; 42*724ba675SRob Herring 43*724ba675SRob Herring bsc: bus@1c000000 { 44*724ba675SRob Herring compatible = "simple-bus"; 45*724ba675SRob Herring #address-cells = <1>; 46*724ba675SRob Herring #size-cells = <1>; 47*724ba675SRob Herring ranges = <0 0 0x1c000000>; 48*724ba675SRob Herring }; 49*724ba675SRob Herring 50*724ba675SRob Herring ether: ethernet@fde00000 { 51*724ba675SRob Herring compatible = "renesas,ether-r8a7778", 52*724ba675SRob Herring "renesas,rcar-gen1-ether"; 53*724ba675SRob Herring reg = <0xfde00000 0x400>; 54*724ba675SRob Herring interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 55*724ba675SRob Herring clocks = <&mstp1_clks R8A7778_CLK_ETHER>; 56*724ba675SRob Herring power-domains = <&cpg_clocks>; 57*724ba675SRob Herring phy-mode = "rmii"; 58*724ba675SRob Herring #address-cells = <1>; 59*724ba675SRob Herring #size-cells = <0>; 60*724ba675SRob Herring status = "disabled"; 61*724ba675SRob Herring }; 62*724ba675SRob Herring 63*724ba675SRob Herring gic: interrupt-controller@fe438000 { 64*724ba675SRob Herring compatible = "arm,pl390"; 65*724ba675SRob Herring #interrupt-cells = <3>; 66*724ba675SRob Herring interrupt-controller; 67*724ba675SRob Herring reg = <0xfe438000 0x1000>, 68*724ba675SRob Herring <0xfe430000 0x100>; 69*724ba675SRob Herring }; 70*724ba675SRob Herring 71*724ba675SRob Herring /* irqpin: IRQ0 - IRQ3 */ 72*724ba675SRob Herring irqpin: interrupt-controller@fe78001c { 73*724ba675SRob Herring compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin"; 74*724ba675SRob Herring #interrupt-cells = <2>; 75*724ba675SRob Herring interrupt-controller; 76*724ba675SRob Herring status = "disabled"; /* default off */ 77*724ba675SRob Herring reg = <0xfe78001c 4>, 78*724ba675SRob Herring <0xfe780010 4>, 79*724ba675SRob Herring <0xfe780024 4>, 80*724ba675SRob Herring <0xfe780044 4>, 81*724ba675SRob Herring <0xfe780064 4>, 82*724ba675SRob Herring <0xfe780000 4>; 83*724ba675SRob Herring interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 84*724ba675SRob Herring <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 85*724ba675SRob Herring <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 86*724ba675SRob Herring <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 87*724ba675SRob Herring sense-bitfield-width = <2>; 88*724ba675SRob Herring }; 89*724ba675SRob Herring 90*724ba675SRob Herring gpio0: gpio@ffc40000 { 91*724ba675SRob Herring compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; 92*724ba675SRob Herring reg = <0xffc40000 0x2c>; 93*724ba675SRob Herring interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 94*724ba675SRob Herring #gpio-cells = <2>; 95*724ba675SRob Herring gpio-controller; 96*724ba675SRob Herring gpio-ranges = <&pfc 0 0 32>; 97*724ba675SRob Herring #interrupt-cells = <2>; 98*724ba675SRob Herring interrupt-controller; 99*724ba675SRob Herring }; 100*724ba675SRob Herring 101*724ba675SRob Herring gpio1: gpio@ffc41000 { 102*724ba675SRob Herring compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; 103*724ba675SRob Herring reg = <0xffc41000 0x2c>; 104*724ba675SRob Herring interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 105*724ba675SRob Herring #gpio-cells = <2>; 106*724ba675SRob Herring gpio-controller; 107*724ba675SRob Herring gpio-ranges = <&pfc 0 32 32>; 108*724ba675SRob Herring #interrupt-cells = <2>; 109*724ba675SRob Herring interrupt-controller; 110*724ba675SRob Herring }; 111*724ba675SRob Herring 112*724ba675SRob Herring gpio2: gpio@ffc42000 { 113*724ba675SRob Herring compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; 114*724ba675SRob Herring reg = <0xffc42000 0x2c>; 115*724ba675SRob Herring interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 116*724ba675SRob Herring #gpio-cells = <2>; 117*724ba675SRob Herring gpio-controller; 118*724ba675SRob Herring gpio-ranges = <&pfc 0 64 32>; 119*724ba675SRob Herring #interrupt-cells = <2>; 120*724ba675SRob Herring interrupt-controller; 121*724ba675SRob Herring }; 122*724ba675SRob Herring 123*724ba675SRob Herring gpio3: gpio@ffc43000 { 124*724ba675SRob Herring compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; 125*724ba675SRob Herring reg = <0xffc43000 0x2c>; 126*724ba675SRob Herring interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 127*724ba675SRob Herring #gpio-cells = <2>; 128*724ba675SRob Herring gpio-controller; 129*724ba675SRob Herring gpio-ranges = <&pfc 0 96 32>; 130*724ba675SRob Herring #interrupt-cells = <2>; 131*724ba675SRob Herring interrupt-controller; 132*724ba675SRob Herring }; 133*724ba675SRob Herring 134*724ba675SRob Herring gpio4: gpio@ffc44000 { 135*724ba675SRob Herring compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; 136*724ba675SRob Herring reg = <0xffc44000 0x2c>; 137*724ba675SRob Herring interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 138*724ba675SRob Herring #gpio-cells = <2>; 139*724ba675SRob Herring gpio-controller; 140*724ba675SRob Herring gpio-ranges = <&pfc 0 128 27>; 141*724ba675SRob Herring #interrupt-cells = <2>; 142*724ba675SRob Herring interrupt-controller; 143*724ba675SRob Herring }; 144*724ba675SRob Herring 145*724ba675SRob Herring pfc: pinctrl@fffc0000 { 146*724ba675SRob Herring compatible = "renesas,pfc-r8a7778"; 147*724ba675SRob Herring reg = <0xfffc0000 0x118>; 148*724ba675SRob Herring }; 149*724ba675SRob Herring 150*724ba675SRob Herring i2c0: i2c@ffc70000 { 151*724ba675SRob Herring #address-cells = <1>; 152*724ba675SRob Herring #size-cells = <0>; 153*724ba675SRob Herring compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; 154*724ba675SRob Herring reg = <0xffc70000 0x1000>; 155*724ba675SRob Herring interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 156*724ba675SRob Herring clocks = <&mstp0_clks R8A7778_CLK_I2C0>; 157*724ba675SRob Herring power-domains = <&cpg_clocks>; 158*724ba675SRob Herring status = "disabled"; 159*724ba675SRob Herring }; 160*724ba675SRob Herring 161*724ba675SRob Herring i2c1: i2c@ffc71000 { 162*724ba675SRob Herring #address-cells = <1>; 163*724ba675SRob Herring #size-cells = <0>; 164*724ba675SRob Herring compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; 165*724ba675SRob Herring reg = <0xffc71000 0x1000>; 166*724ba675SRob Herring interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 167*724ba675SRob Herring clocks = <&mstp0_clks R8A7778_CLK_I2C1>; 168*724ba675SRob Herring power-domains = <&cpg_clocks>; 169*724ba675SRob Herring i2c-scl-internal-delay-ns = <5>; 170*724ba675SRob Herring status = "disabled"; 171*724ba675SRob Herring }; 172*724ba675SRob Herring 173*724ba675SRob Herring i2c2: i2c@ffc72000 { 174*724ba675SRob Herring #address-cells = <1>; 175*724ba675SRob Herring #size-cells = <0>; 176*724ba675SRob Herring compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; 177*724ba675SRob Herring reg = <0xffc72000 0x1000>; 178*724ba675SRob Herring interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 179*724ba675SRob Herring clocks = <&mstp0_clks R8A7778_CLK_I2C2>; 180*724ba675SRob Herring power-domains = <&cpg_clocks>; 181*724ba675SRob Herring i2c-scl-internal-delay-ns = <5>; 182*724ba675SRob Herring status = "disabled"; 183*724ba675SRob Herring }; 184*724ba675SRob Herring 185*724ba675SRob Herring i2c3: i2c@ffc73000 { 186*724ba675SRob Herring #address-cells = <1>; 187*724ba675SRob Herring #size-cells = <0>; 188*724ba675SRob Herring compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; 189*724ba675SRob Herring reg = <0xffc73000 0x1000>; 190*724ba675SRob Herring interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 191*724ba675SRob Herring clocks = <&mstp0_clks R8A7778_CLK_I2C3>; 192*724ba675SRob Herring power-domains = <&cpg_clocks>; 193*724ba675SRob Herring i2c-scl-internal-delay-ns = <5>; 194*724ba675SRob Herring status = "disabled"; 195*724ba675SRob Herring }; 196*724ba675SRob Herring 197*724ba675SRob Herring tmu0: timer@ffd80000 { 198*724ba675SRob Herring compatible = "renesas,tmu-r8a7778", "renesas,tmu"; 199*724ba675SRob Herring reg = <0xffd80000 0x30>; 200*724ba675SRob Herring interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 201*724ba675SRob Herring <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 202*724ba675SRob Herring <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 203*724ba675SRob Herring clocks = <&mstp0_clks R8A7778_CLK_TMU0>; 204*724ba675SRob Herring clock-names = "fck"; 205*724ba675SRob Herring power-domains = <&cpg_clocks>; 206*724ba675SRob Herring 207*724ba675SRob Herring #renesas,channels = <3>; 208*724ba675SRob Herring 209*724ba675SRob Herring status = "disabled"; 210*724ba675SRob Herring }; 211*724ba675SRob Herring 212*724ba675SRob Herring tmu1: timer@ffd81000 { 213*724ba675SRob Herring compatible = "renesas,tmu-r8a7778", "renesas,tmu"; 214*724ba675SRob Herring reg = <0xffd81000 0x30>; 215*724ba675SRob Herring interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 216*724ba675SRob Herring <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 217*724ba675SRob Herring <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 218*724ba675SRob Herring clocks = <&mstp0_clks R8A7778_CLK_TMU1>; 219*724ba675SRob Herring clock-names = "fck"; 220*724ba675SRob Herring power-domains = <&cpg_clocks>; 221*724ba675SRob Herring 222*724ba675SRob Herring #renesas,channels = <3>; 223*724ba675SRob Herring 224*724ba675SRob Herring status = "disabled"; 225*724ba675SRob Herring }; 226*724ba675SRob Herring 227*724ba675SRob Herring tmu2: timer@ffd82000 { 228*724ba675SRob Herring compatible = "renesas,tmu-r8a7778", "renesas,tmu"; 229*724ba675SRob Herring reg = <0xffd82000 0x30>; 230*724ba675SRob Herring interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 231*724ba675SRob Herring <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 232*724ba675SRob Herring <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 233*724ba675SRob Herring clocks = <&mstp0_clks R8A7778_CLK_TMU2>; 234*724ba675SRob Herring clock-names = "fck"; 235*724ba675SRob Herring power-domains = <&cpg_clocks>; 236*724ba675SRob Herring 237*724ba675SRob Herring #renesas,channels = <3>; 238*724ba675SRob Herring 239*724ba675SRob Herring status = "disabled"; 240*724ba675SRob Herring }; 241*724ba675SRob Herring 242*724ba675SRob Herring rcar_sound: sound@ffd90000 { 243*724ba675SRob Herring /* 244*724ba675SRob Herring * #sound-dai-cells is required if simple-card 245*724ba675SRob Herring * 246*724ba675SRob Herring * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 247*724ba675SRob Herring * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 248*724ba675SRob Herring */ 249*724ba675SRob Herring compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1"; 250*724ba675SRob Herring reg = <0xffd90000 0x1000>, /* SRU */ 251*724ba675SRob Herring <0xffd91000 0x240>, /* SSI */ 252*724ba675SRob Herring <0xfffe0000 0x24>; /* ADG */ 253*724ba675SRob Herring clocks = <&mstp3_clks R8A7778_CLK_SSI8>, 254*724ba675SRob Herring <&mstp3_clks R8A7778_CLK_SSI7>, 255*724ba675SRob Herring <&mstp3_clks R8A7778_CLK_SSI6>, 256*724ba675SRob Herring <&mstp3_clks R8A7778_CLK_SSI5>, 257*724ba675SRob Herring <&mstp3_clks R8A7778_CLK_SSI4>, 258*724ba675SRob Herring <&mstp0_clks R8A7778_CLK_SSI3>, 259*724ba675SRob Herring <&mstp0_clks R8A7778_CLK_SSI2>, 260*724ba675SRob Herring <&mstp0_clks R8A7778_CLK_SSI1>, 261*724ba675SRob Herring <&mstp0_clks R8A7778_CLK_SSI0>, 262*724ba675SRob Herring <&mstp5_clks R8A7778_CLK_SRU_SRC8>, 263*724ba675SRob Herring <&mstp5_clks R8A7778_CLK_SRU_SRC7>, 264*724ba675SRob Herring <&mstp5_clks R8A7778_CLK_SRU_SRC6>, 265*724ba675SRob Herring <&mstp5_clks R8A7778_CLK_SRU_SRC5>, 266*724ba675SRob Herring <&mstp5_clks R8A7778_CLK_SRU_SRC4>, 267*724ba675SRob Herring <&mstp5_clks R8A7778_CLK_SRU_SRC3>, 268*724ba675SRob Herring <&mstp5_clks R8A7778_CLK_SRU_SRC2>, 269*724ba675SRob Herring <&mstp5_clks R8A7778_CLK_SRU_SRC1>, 270*724ba675SRob Herring <&mstp5_clks R8A7778_CLK_SRU_SRC0>, 271*724ba675SRob Herring <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, 272*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_S1>; 273*724ba675SRob Herring clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", 274*724ba675SRob Herring "ssi.3", "ssi.2", "ssi.1", "ssi.0", 275*724ba675SRob Herring "src.8", "src.7", "src.6", "src.5", "src.4", 276*724ba675SRob Herring "src.3", "src.2", "src.1", "src.0", 277*724ba675SRob Herring "clk_a", "clk_b", "clk_c", "clk_i"; 278*724ba675SRob Herring 279*724ba675SRob Herring status = "disabled"; 280*724ba675SRob Herring 281*724ba675SRob Herring rcar_sound,src { 282*724ba675SRob Herring src3: src-3 { }; 283*724ba675SRob Herring src4: src-4 { }; 284*724ba675SRob Herring src5: src-5 { }; 285*724ba675SRob Herring src6: src-6 { }; 286*724ba675SRob Herring src7: src-7 { }; 287*724ba675SRob Herring src8: src-8 { }; 288*724ba675SRob Herring src9: src-9 { }; 289*724ba675SRob Herring }; 290*724ba675SRob Herring 291*724ba675SRob Herring rcar_sound,ssi { 292*724ba675SRob Herring ssi3: ssi-3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; }; 293*724ba675SRob Herring ssi4: ssi-4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; }; 294*724ba675SRob Herring ssi5: ssi-5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; }; 295*724ba675SRob Herring ssi6: ssi-6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; }; 296*724ba675SRob Herring ssi7: ssi-7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; }; 297*724ba675SRob Herring ssi8: ssi-8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; }; 298*724ba675SRob Herring ssi9: ssi-9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; }; 299*724ba675SRob Herring }; 300*724ba675SRob Herring }; 301*724ba675SRob Herring 302*724ba675SRob Herring scif0: serial@ffe40000 { 303*724ba675SRob Herring compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", 304*724ba675SRob Herring "renesas,scif"; 305*724ba675SRob Herring reg = <0xffe40000 0x100>; 306*724ba675SRob Herring interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 307*724ba675SRob Herring clocks = <&mstp0_clks R8A7778_CLK_SCIF0>, 308*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; 309*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 310*724ba675SRob Herring power-domains = <&cpg_clocks>; 311*724ba675SRob Herring status = "disabled"; 312*724ba675SRob Herring }; 313*724ba675SRob Herring 314*724ba675SRob Herring scif1: serial@ffe41000 { 315*724ba675SRob Herring compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", 316*724ba675SRob Herring "renesas,scif"; 317*724ba675SRob Herring reg = <0xffe41000 0x100>; 318*724ba675SRob Herring interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 319*724ba675SRob Herring clocks = <&mstp0_clks R8A7778_CLK_SCIF1>, 320*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; 321*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 322*724ba675SRob Herring power-domains = <&cpg_clocks>; 323*724ba675SRob Herring status = "disabled"; 324*724ba675SRob Herring }; 325*724ba675SRob Herring 326*724ba675SRob Herring scif2: serial@ffe42000 { 327*724ba675SRob Herring compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", 328*724ba675SRob Herring "renesas,scif"; 329*724ba675SRob Herring reg = <0xffe42000 0x100>; 330*724ba675SRob Herring interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 331*724ba675SRob Herring clocks = <&mstp0_clks R8A7778_CLK_SCIF2>, 332*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; 333*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 334*724ba675SRob Herring power-domains = <&cpg_clocks>; 335*724ba675SRob Herring status = "disabled"; 336*724ba675SRob Herring }; 337*724ba675SRob Herring 338*724ba675SRob Herring scif3: serial@ffe43000 { 339*724ba675SRob Herring compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", 340*724ba675SRob Herring "renesas,scif"; 341*724ba675SRob Herring reg = <0xffe43000 0x100>; 342*724ba675SRob Herring interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 343*724ba675SRob Herring clocks = <&mstp0_clks R8A7778_CLK_SCIF3>, 344*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; 345*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 346*724ba675SRob Herring power-domains = <&cpg_clocks>; 347*724ba675SRob Herring status = "disabled"; 348*724ba675SRob Herring }; 349*724ba675SRob Herring 350*724ba675SRob Herring scif4: serial@ffe44000 { 351*724ba675SRob Herring compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", 352*724ba675SRob Herring "renesas,scif"; 353*724ba675SRob Herring reg = <0xffe44000 0x100>; 354*724ba675SRob Herring interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 355*724ba675SRob Herring clocks = <&mstp0_clks R8A7778_CLK_SCIF4>, 356*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; 357*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 358*724ba675SRob Herring power-domains = <&cpg_clocks>; 359*724ba675SRob Herring status = "disabled"; 360*724ba675SRob Herring }; 361*724ba675SRob Herring 362*724ba675SRob Herring scif5: serial@ffe45000 { 363*724ba675SRob Herring compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", 364*724ba675SRob Herring "renesas,scif"; 365*724ba675SRob Herring reg = <0xffe45000 0x100>; 366*724ba675SRob Herring interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 367*724ba675SRob Herring clocks = <&mstp0_clks R8A7778_CLK_SCIF5>, 368*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; 369*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 370*724ba675SRob Herring power-domains = <&cpg_clocks>; 371*724ba675SRob Herring status = "disabled"; 372*724ba675SRob Herring }; 373*724ba675SRob Herring 374*724ba675SRob Herring hscif0: serial@ffe48000 { 375*724ba675SRob Herring compatible = "renesas,hscif-r8a7778", 376*724ba675SRob Herring "renesas,rcar-gen1-hscif", "renesas,hscif"; 377*724ba675SRob Herring reg = <0xffe48000 96>; 378*724ba675SRob Herring interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 379*724ba675SRob Herring clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>, 380*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>; 381*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 382*724ba675SRob Herring power-domains = <&cpg_clocks>; 383*724ba675SRob Herring status = "disabled"; 384*724ba675SRob Herring }; 385*724ba675SRob Herring 386*724ba675SRob Herring hscif1: serial@ffe49000 { 387*724ba675SRob Herring compatible = "renesas,hscif-r8a7778", 388*724ba675SRob Herring "renesas,rcar-gen1-hscif", "renesas,hscif"; 389*724ba675SRob Herring reg = <0xffe49000 96>; 390*724ba675SRob Herring interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 391*724ba675SRob Herring clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>, 392*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>; 393*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 394*724ba675SRob Herring power-domains = <&cpg_clocks>; 395*724ba675SRob Herring status = "disabled"; 396*724ba675SRob Herring }; 397*724ba675SRob Herring 398*724ba675SRob Herring mmcif: mmc@ffe4e000 { 399*724ba675SRob Herring compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif"; 400*724ba675SRob Herring reg = <0xffe4e000 0x100>; 401*724ba675SRob Herring interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 402*724ba675SRob Herring clocks = <&mstp3_clks R8A7778_CLK_MMC>; 403*724ba675SRob Herring power-domains = <&cpg_clocks>; 404*724ba675SRob Herring status = "disabled"; 405*724ba675SRob Herring }; 406*724ba675SRob Herring 407*724ba675SRob Herring sdhi0: mmc@ffe4c000 { 408*724ba675SRob Herring compatible = "renesas,sdhi-r8a7778", 409*724ba675SRob Herring "renesas,rcar-gen1-sdhi"; 410*724ba675SRob Herring reg = <0xffe4c000 0x100>; 411*724ba675SRob Herring interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 412*724ba675SRob Herring clocks = <&mstp3_clks R8A7778_CLK_SDHI0>; 413*724ba675SRob Herring power-domains = <&cpg_clocks>; 414*724ba675SRob Herring status = "disabled"; 415*724ba675SRob Herring }; 416*724ba675SRob Herring 417*724ba675SRob Herring sdhi1: mmc@ffe4d000 { 418*724ba675SRob Herring compatible = "renesas,sdhi-r8a7778", 419*724ba675SRob Herring "renesas,rcar-gen1-sdhi"; 420*724ba675SRob Herring reg = <0xffe4d000 0x100>; 421*724ba675SRob Herring interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 422*724ba675SRob Herring clocks = <&mstp3_clks R8A7778_CLK_SDHI1>; 423*724ba675SRob Herring power-domains = <&cpg_clocks>; 424*724ba675SRob Herring status = "disabled"; 425*724ba675SRob Herring }; 426*724ba675SRob Herring 427*724ba675SRob Herring sdhi2: mmc@ffe4f000 { 428*724ba675SRob Herring compatible = "renesas,sdhi-r8a7778", 429*724ba675SRob Herring "renesas,rcar-gen1-sdhi"; 430*724ba675SRob Herring reg = <0xffe4f000 0x100>; 431*724ba675SRob Herring interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 432*724ba675SRob Herring clocks = <&mstp3_clks R8A7778_CLK_SDHI2>; 433*724ba675SRob Herring power-domains = <&cpg_clocks>; 434*724ba675SRob Herring status = "disabled"; 435*724ba675SRob Herring }; 436*724ba675SRob Herring 437*724ba675SRob Herring hspi0: spi@fffc7000 { 438*724ba675SRob Herring compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 439*724ba675SRob Herring reg = <0xfffc7000 0x18>; 440*724ba675SRob Herring interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 441*724ba675SRob Herring clocks = <&mstp0_clks R8A7778_CLK_HSPI>; 442*724ba675SRob Herring power-domains = <&cpg_clocks>; 443*724ba675SRob Herring #address-cells = <1>; 444*724ba675SRob Herring #size-cells = <0>; 445*724ba675SRob Herring status = "disabled"; 446*724ba675SRob Herring }; 447*724ba675SRob Herring 448*724ba675SRob Herring hspi1: spi@fffc8000 { 449*724ba675SRob Herring compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 450*724ba675SRob Herring reg = <0xfffc8000 0x18>; 451*724ba675SRob Herring interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 452*724ba675SRob Herring clocks = <&mstp0_clks R8A7778_CLK_HSPI>; 453*724ba675SRob Herring power-domains = <&cpg_clocks>; 454*724ba675SRob Herring #address-cells = <1>; 455*724ba675SRob Herring #size-cells = <0>; 456*724ba675SRob Herring status = "disabled"; 457*724ba675SRob Herring }; 458*724ba675SRob Herring 459*724ba675SRob Herring hspi2: spi@fffc6000 { 460*724ba675SRob Herring compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 461*724ba675SRob Herring reg = <0xfffc6000 0x18>; 462*724ba675SRob Herring interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 463*724ba675SRob Herring clocks = <&mstp0_clks R8A7778_CLK_HSPI>; 464*724ba675SRob Herring power-domains = <&cpg_clocks>; 465*724ba675SRob Herring #address-cells = <1>; 466*724ba675SRob Herring #size-cells = <0>; 467*724ba675SRob Herring status = "disabled"; 468*724ba675SRob Herring }; 469*724ba675SRob Herring 470*724ba675SRob Herring clocks { 471*724ba675SRob Herring #address-cells = <1>; 472*724ba675SRob Herring #size-cells = <1>; 473*724ba675SRob Herring ranges; 474*724ba675SRob Herring 475*724ba675SRob Herring /* External input clock */ 476*724ba675SRob Herring extal_clk: extal { 477*724ba675SRob Herring compatible = "fixed-clock"; 478*724ba675SRob Herring #clock-cells = <0>; 479*724ba675SRob Herring clock-frequency = <0>; 480*724ba675SRob Herring }; 481*724ba675SRob Herring 482*724ba675SRob Herring /* External SCIF clock */ 483*724ba675SRob Herring scif_clk: scif { 484*724ba675SRob Herring compatible = "fixed-clock"; 485*724ba675SRob Herring #clock-cells = <0>; 486*724ba675SRob Herring /* This value must be overridden by the board. */ 487*724ba675SRob Herring clock-frequency = <0>; 488*724ba675SRob Herring }; 489*724ba675SRob Herring 490*724ba675SRob Herring /* Special CPG clocks */ 491*724ba675SRob Herring cpg_clocks: cpg_clocks@ffc80000 { 492*724ba675SRob Herring compatible = "renesas,r8a7778-cpg-clocks"; 493*724ba675SRob Herring reg = <0xffc80000 0x80>; 494*724ba675SRob Herring #clock-cells = <1>; 495*724ba675SRob Herring clocks = <&extal_clk>; 496*724ba675SRob Herring clock-output-names = "plla", "pllb", "b", 497*724ba675SRob Herring "out", "p", "s", "s1"; 498*724ba675SRob Herring #power-domain-cells = <0>; 499*724ba675SRob Herring }; 500*724ba675SRob Herring 501*724ba675SRob Herring /* Audio clocks; frequencies are set by boards if applicable. */ 502*724ba675SRob Herring audio_clk_a: audio_clk_a { 503*724ba675SRob Herring compatible = "fixed-clock"; 504*724ba675SRob Herring #clock-cells = <0>; 505*724ba675SRob Herring clock-frequency = <0>; 506*724ba675SRob Herring }; 507*724ba675SRob Herring audio_clk_b: audio_clk_b { 508*724ba675SRob Herring compatible = "fixed-clock"; 509*724ba675SRob Herring #clock-cells = <0>; 510*724ba675SRob Herring clock-frequency = <0>; 511*724ba675SRob Herring }; 512*724ba675SRob Herring audio_clk_c: audio_clk_c { 513*724ba675SRob Herring compatible = "fixed-clock"; 514*724ba675SRob Herring #clock-cells = <0>; 515*724ba675SRob Herring clock-frequency = <0>; 516*724ba675SRob Herring }; 517*724ba675SRob Herring 518*724ba675SRob Herring /* Fixed ratio clocks */ 519*724ba675SRob Herring g_clk: g { 520*724ba675SRob Herring compatible = "fixed-factor-clock"; 521*724ba675SRob Herring clocks = <&cpg_clocks R8A7778_CLK_PLLA>; 522*724ba675SRob Herring #clock-cells = <0>; 523*724ba675SRob Herring clock-div = <12>; 524*724ba675SRob Herring clock-mult = <1>; 525*724ba675SRob Herring }; 526*724ba675SRob Herring i_clk: i { 527*724ba675SRob Herring compatible = "fixed-factor-clock"; 528*724ba675SRob Herring clocks = <&cpg_clocks R8A7778_CLK_PLLA>; 529*724ba675SRob Herring #clock-cells = <0>; 530*724ba675SRob Herring clock-div = <1>; 531*724ba675SRob Herring clock-mult = <1>; 532*724ba675SRob Herring }; 533*724ba675SRob Herring s3_clk: s3 { 534*724ba675SRob Herring compatible = "fixed-factor-clock"; 535*724ba675SRob Herring clocks = <&cpg_clocks R8A7778_CLK_PLLA>; 536*724ba675SRob Herring #clock-cells = <0>; 537*724ba675SRob Herring clock-div = <4>; 538*724ba675SRob Herring clock-mult = <1>; 539*724ba675SRob Herring }; 540*724ba675SRob Herring s4_clk: s4 { 541*724ba675SRob Herring compatible = "fixed-factor-clock"; 542*724ba675SRob Herring clocks = <&cpg_clocks R8A7778_CLK_PLLA>; 543*724ba675SRob Herring #clock-cells = <0>; 544*724ba675SRob Herring clock-div = <8>; 545*724ba675SRob Herring clock-mult = <1>; 546*724ba675SRob Herring }; 547*724ba675SRob Herring z_clk: z { 548*724ba675SRob Herring compatible = "fixed-factor-clock"; 549*724ba675SRob Herring clocks = <&cpg_clocks R8A7778_CLK_PLLB>; 550*724ba675SRob Herring #clock-cells = <0>; 551*724ba675SRob Herring clock-div = <1>; 552*724ba675SRob Herring clock-mult = <1>; 553*724ba675SRob Herring }; 554*724ba675SRob Herring 555*724ba675SRob Herring /* Gate clocks */ 556*724ba675SRob Herring mstp0_clks: mstp0_clks@ffc80030 { 557*724ba675SRob Herring compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; 558*724ba675SRob Herring reg = <0xffc80030 4>; 559*724ba675SRob Herring clocks = <&cpg_clocks R8A7778_CLK_P>, 560*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 561*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 562*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 563*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 564*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 565*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 566*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 567*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 568*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 569*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_S>, 570*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_S>, 571*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 572*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 573*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 574*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 575*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 576*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 577*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 578*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 579*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_S>; 580*724ba675SRob Herring #clock-cells = <1>; 581*724ba675SRob Herring clock-indices = < 582*724ba675SRob Herring R8A7778_CLK_I2C0 R8A7778_CLK_I2C1 583*724ba675SRob Herring R8A7778_CLK_I2C2 R8A7778_CLK_I2C3 584*724ba675SRob Herring R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1 585*724ba675SRob Herring R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3 586*724ba675SRob Herring R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5 587*724ba675SRob Herring R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1 588*724ba675SRob Herring R8A7778_CLK_TMU0 R8A7778_CLK_TMU1 589*724ba675SRob Herring R8A7778_CLK_TMU2 R8A7778_CLK_SSI0 590*724ba675SRob Herring R8A7778_CLK_SSI1 R8A7778_CLK_SSI2 591*724ba675SRob Herring R8A7778_CLK_SSI3 R8A7778_CLK_SRU 592*724ba675SRob Herring R8A7778_CLK_HSPI 593*724ba675SRob Herring >; 594*724ba675SRob Herring clock-output-names = 595*724ba675SRob Herring "i2c0", "i2c1", "i2c2", "i2c3", "scif0", 596*724ba675SRob Herring "scif1", "scif2", "scif3", "scif4", "scif5", 597*724ba675SRob Herring "hscif0", "hscif1", 598*724ba675SRob Herring "tmu0", "tmu1", "tmu2", "ssi0", "ssi1", 599*724ba675SRob Herring "ssi2", "ssi3", "sru", "hspi"; 600*724ba675SRob Herring }; 601*724ba675SRob Herring mstp1_clks: mstp1_clks@ffc80034 { 602*724ba675SRob Herring compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; 603*724ba675SRob Herring reg = <0xffc80034 4>, <0xffc80044 4>; 604*724ba675SRob Herring clocks = <&cpg_clocks R8A7778_CLK_P>, 605*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_S>, 606*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_S>, 607*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>; 608*724ba675SRob Herring #clock-cells = <1>; 609*724ba675SRob Herring clock-indices = < 610*724ba675SRob Herring R8A7778_CLK_ETHER R8A7778_CLK_VIN0 611*724ba675SRob Herring R8A7778_CLK_VIN1 R8A7778_CLK_USB 612*724ba675SRob Herring >; 613*724ba675SRob Herring clock-output-names = 614*724ba675SRob Herring "ether", "vin0", "vin1", "usb"; 615*724ba675SRob Herring }; 616*724ba675SRob Herring mstp3_clks: mstp3_clks@ffc8003c { 617*724ba675SRob Herring compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; 618*724ba675SRob Herring reg = <0xffc8003c 4>; 619*724ba675SRob Herring clocks = <&s4_clk>, 620*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 621*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 622*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 623*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 624*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 625*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 626*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 627*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>; 628*724ba675SRob Herring #clock-cells = <1>; 629*724ba675SRob Herring clock-indices = < 630*724ba675SRob Herring R8A7778_CLK_MMC R8A7778_CLK_SDHI0 631*724ba675SRob Herring R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2 632*724ba675SRob Herring R8A7778_CLK_SSI4 R8A7778_CLK_SSI5 633*724ba675SRob Herring R8A7778_CLK_SSI6 R8A7778_CLK_SSI7 634*724ba675SRob Herring R8A7778_CLK_SSI8 635*724ba675SRob Herring >; 636*724ba675SRob Herring clock-output-names = 637*724ba675SRob Herring "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4", 638*724ba675SRob Herring "ssi5", "ssi6", "ssi7", "ssi8"; 639*724ba675SRob Herring }; 640*724ba675SRob Herring mstp5_clks: mstp5_clks@ffc80054 { 641*724ba675SRob Herring compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; 642*724ba675SRob Herring reg = <0xffc80054 4>; 643*724ba675SRob Herring clocks = <&cpg_clocks R8A7778_CLK_P>, 644*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 645*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 646*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 647*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 648*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 649*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 650*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>, 651*724ba675SRob Herring <&cpg_clocks R8A7778_CLK_P>; 652*724ba675SRob Herring #clock-cells = <1>; 653*724ba675SRob Herring clock-indices = < 654*724ba675SRob Herring R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1 655*724ba675SRob Herring R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3 656*724ba675SRob Herring R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5 657*724ba675SRob Herring R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7 658*724ba675SRob Herring R8A7778_CLK_SRU_SRC8 659*724ba675SRob Herring >; 660*724ba675SRob Herring clock-output-names = 661*724ba675SRob Herring "sru-src0", "sru-src1", "sru-src2", 662*724ba675SRob Herring "sru-src3", "sru-src4", "sru-src5", 663*724ba675SRob Herring "sru-src6", "sru-src7", "sru-src8"; 664*724ba675SRob Herring }; 665*724ba675SRob Herring }; 666*724ba675SRob Herring 667*724ba675SRob Herring rst: reset-controller@ffcc0000 { 668*724ba675SRob Herring compatible = "renesas,r8a7778-reset-wdt"; 669*724ba675SRob Herring reg = <0xffcc0000 0x40>; 670*724ba675SRob Herring }; 671*724ba675SRob Herring}; 672