1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree Source for the r8a77470 SoC 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2018 Renesas Electronics Corp. 6*724ba675SRob Herring */ 7*724ba675SRob Herring 8*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 9*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 10*724ba675SRob Herring#include <dt-bindings/clock/r8a77470-cpg-mssr.h> 11*724ba675SRob Herring#include <dt-bindings/power/r8a77470-sysc.h> 12*724ba675SRob Herring/ { 13*724ba675SRob Herring compatible = "renesas,r8a77470"; 14*724ba675SRob Herring #address-cells = <2>; 15*724ba675SRob Herring #size-cells = <2>; 16*724ba675SRob Herring 17*724ba675SRob Herring aliases { 18*724ba675SRob Herring i2c0 = &i2c0; 19*724ba675SRob Herring i2c1 = &i2c1; 20*724ba675SRob Herring i2c2 = &i2c2; 21*724ba675SRob Herring i2c3 = &i2c3; 22*724ba675SRob Herring i2c4 = &i2c4; 23*724ba675SRob Herring }; 24*724ba675SRob Herring 25*724ba675SRob Herring cpus { 26*724ba675SRob Herring #address-cells = <1>; 27*724ba675SRob Herring #size-cells = <0>; 28*724ba675SRob Herring 29*724ba675SRob Herring cpu0: cpu@0 { 30*724ba675SRob Herring device_type = "cpu"; 31*724ba675SRob Herring compatible = "arm,cortex-a7"; 32*724ba675SRob Herring reg = <0>; 33*724ba675SRob Herring clock-frequency = <1000000000>; 34*724ba675SRob Herring clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; 35*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_CA7_CPU0>; 36*724ba675SRob Herring enable-method = "renesas,apmu"; 37*724ba675SRob Herring next-level-cache = <&L2_CA7>; 38*724ba675SRob Herring }; 39*724ba675SRob Herring 40*724ba675SRob Herring cpu1: cpu@1 { 41*724ba675SRob Herring device_type = "cpu"; 42*724ba675SRob Herring compatible = "arm,cortex-a7"; 43*724ba675SRob Herring reg = <1>; 44*724ba675SRob Herring clock-frequency = <1000000000>; 45*724ba675SRob Herring clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; 46*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_CA7_CPU1>; 47*724ba675SRob Herring enable-method = "renesas,apmu"; 48*724ba675SRob Herring next-level-cache = <&L2_CA7>; 49*724ba675SRob Herring }; 50*724ba675SRob Herring 51*724ba675SRob Herring L2_CA7: cache-controller-0 { 52*724ba675SRob Herring compatible = "cache"; 53*724ba675SRob Herring cache-unified; 54*724ba675SRob Herring cache-level = <2>; 55*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_CA7_SCU>; 56*724ba675SRob Herring }; 57*724ba675SRob Herring }; 58*724ba675SRob Herring 59*724ba675SRob Herring /* External root clock */ 60*724ba675SRob Herring extal_clk: extal { 61*724ba675SRob Herring compatible = "fixed-clock"; 62*724ba675SRob Herring #clock-cells = <0>; 63*724ba675SRob Herring /* This value must be overridden by the board. */ 64*724ba675SRob Herring clock-frequency = <0>; 65*724ba675SRob Herring }; 66*724ba675SRob Herring 67*724ba675SRob Herring pmu { 68*724ba675SRob Herring compatible = "arm,cortex-a7-pmu"; 69*724ba675SRob Herring interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 70*724ba675SRob Herring <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 71*724ba675SRob Herring interrupt-affinity = <&cpu0>, <&cpu1>; 72*724ba675SRob Herring }; 73*724ba675SRob Herring 74*724ba675SRob Herring /* External SCIF clock */ 75*724ba675SRob Herring scif_clk: scif { 76*724ba675SRob Herring compatible = "fixed-clock"; 77*724ba675SRob Herring #clock-cells = <0>; 78*724ba675SRob Herring /* This value must be overridden by the board. */ 79*724ba675SRob Herring clock-frequency = <0>; 80*724ba675SRob Herring }; 81*724ba675SRob Herring 82*724ba675SRob Herring soc { 83*724ba675SRob Herring compatible = "simple-bus"; 84*724ba675SRob Herring interrupt-parent = <&gic>; 85*724ba675SRob Herring 86*724ba675SRob Herring #address-cells = <2>; 87*724ba675SRob Herring #size-cells = <2>; 88*724ba675SRob Herring ranges; 89*724ba675SRob Herring 90*724ba675SRob Herring rwdt: watchdog@e6020000 { 91*724ba675SRob Herring compatible = "renesas,r8a77470-wdt", 92*724ba675SRob Herring "renesas,rcar-gen2-wdt"; 93*724ba675SRob Herring reg = <0 0xe6020000 0 0x0c>; 94*724ba675SRob Herring interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 95*724ba675SRob Herring clocks = <&cpg CPG_MOD 402>; 96*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 97*724ba675SRob Herring resets = <&cpg 402>; 98*724ba675SRob Herring status = "disabled"; 99*724ba675SRob Herring }; 100*724ba675SRob Herring 101*724ba675SRob Herring gpio0: gpio@e6050000 { 102*724ba675SRob Herring compatible = "renesas,gpio-r8a77470", 103*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 104*724ba675SRob Herring reg = <0 0xe6050000 0 0x50>; 105*724ba675SRob Herring interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 106*724ba675SRob Herring #gpio-cells = <2>; 107*724ba675SRob Herring gpio-controller; 108*724ba675SRob Herring gpio-ranges = <&pfc 0 0 23>; 109*724ba675SRob Herring #interrupt-cells = <2>; 110*724ba675SRob Herring interrupt-controller; 111*724ba675SRob Herring clocks = <&cpg CPG_MOD 912>; 112*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 113*724ba675SRob Herring resets = <&cpg 912>; 114*724ba675SRob Herring }; 115*724ba675SRob Herring 116*724ba675SRob Herring gpio1: gpio@e6051000 { 117*724ba675SRob Herring compatible = "renesas,gpio-r8a77470", 118*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 119*724ba675SRob Herring reg = <0 0xe6051000 0 0x50>; 120*724ba675SRob Herring interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 121*724ba675SRob Herring #gpio-cells = <2>; 122*724ba675SRob Herring gpio-controller; 123*724ba675SRob Herring gpio-ranges = <&pfc 0 32 23>; 124*724ba675SRob Herring #interrupt-cells = <2>; 125*724ba675SRob Herring interrupt-controller; 126*724ba675SRob Herring clocks = <&cpg CPG_MOD 911>; 127*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 128*724ba675SRob Herring resets = <&cpg 911>; 129*724ba675SRob Herring }; 130*724ba675SRob Herring 131*724ba675SRob Herring gpio2: gpio@e6052000 { 132*724ba675SRob Herring compatible = "renesas,gpio-r8a77470", 133*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 134*724ba675SRob Herring reg = <0 0xe6052000 0 0x50>; 135*724ba675SRob Herring interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 136*724ba675SRob Herring #gpio-cells = <2>; 137*724ba675SRob Herring gpio-controller; 138*724ba675SRob Herring gpio-ranges = <&pfc 0 64 32>; 139*724ba675SRob Herring #interrupt-cells = <2>; 140*724ba675SRob Herring interrupt-controller; 141*724ba675SRob Herring clocks = <&cpg CPG_MOD 910>; 142*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 143*724ba675SRob Herring resets = <&cpg 910>; 144*724ba675SRob Herring }; 145*724ba675SRob Herring 146*724ba675SRob Herring gpio3: gpio@e6053000 { 147*724ba675SRob Herring compatible = "renesas,gpio-r8a77470", 148*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 149*724ba675SRob Herring reg = <0 0xe6053000 0 0x50>; 150*724ba675SRob Herring interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 151*724ba675SRob Herring #gpio-cells = <2>; 152*724ba675SRob Herring gpio-controller; 153*724ba675SRob Herring gpio-ranges = <&pfc 0 96 30>; 154*724ba675SRob Herring gpio-reserved-ranges = <17 10>; 155*724ba675SRob Herring #interrupt-cells = <2>; 156*724ba675SRob Herring interrupt-controller; 157*724ba675SRob Herring clocks = <&cpg CPG_MOD 909>; 158*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 159*724ba675SRob Herring resets = <&cpg 909>; 160*724ba675SRob Herring }; 161*724ba675SRob Herring 162*724ba675SRob Herring gpio4: gpio@e6054000 { 163*724ba675SRob Herring compatible = "renesas,gpio-r8a77470", 164*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 165*724ba675SRob Herring reg = <0 0xe6054000 0 0x50>; 166*724ba675SRob Herring interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 167*724ba675SRob Herring #gpio-cells = <2>; 168*724ba675SRob Herring gpio-controller; 169*724ba675SRob Herring gpio-ranges = <&pfc 0 128 26>; 170*724ba675SRob Herring #interrupt-cells = <2>; 171*724ba675SRob Herring interrupt-controller; 172*724ba675SRob Herring clocks = <&cpg CPG_MOD 908>; 173*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 174*724ba675SRob Herring resets = <&cpg 908>; 175*724ba675SRob Herring }; 176*724ba675SRob Herring 177*724ba675SRob Herring gpio5: gpio@e6055000 { 178*724ba675SRob Herring compatible = "renesas,gpio-r8a77470", 179*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 180*724ba675SRob Herring reg = <0 0xe6055000 0 0x50>; 181*724ba675SRob Herring interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 182*724ba675SRob Herring #gpio-cells = <2>; 183*724ba675SRob Herring gpio-controller; 184*724ba675SRob Herring gpio-ranges = <&pfc 0 160 32>; 185*724ba675SRob Herring #interrupt-cells = <2>; 186*724ba675SRob Herring interrupt-controller; 187*724ba675SRob Herring clocks = <&cpg CPG_MOD 907>; 188*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 189*724ba675SRob Herring resets = <&cpg 907>; 190*724ba675SRob Herring }; 191*724ba675SRob Herring 192*724ba675SRob Herring pfc: pinctrl@e6060000 { 193*724ba675SRob Herring compatible = "renesas,pfc-r8a77470"; 194*724ba675SRob Herring reg = <0 0xe6060000 0 0x118>; 195*724ba675SRob Herring }; 196*724ba675SRob Herring 197*724ba675SRob Herring cpg: clock-controller@e6150000 { 198*724ba675SRob Herring compatible = "renesas,r8a77470-cpg-mssr"; 199*724ba675SRob Herring reg = <0 0xe6150000 0 0x1000>; 200*724ba675SRob Herring clocks = <&extal_clk>, <&usb_extal_clk>; 201*724ba675SRob Herring clock-names = "extal", "usb_extal"; 202*724ba675SRob Herring #clock-cells = <2>; 203*724ba675SRob Herring #power-domain-cells = <0>; 204*724ba675SRob Herring #reset-cells = <1>; 205*724ba675SRob Herring }; 206*724ba675SRob Herring 207*724ba675SRob Herring apmu@e6151000 { 208*724ba675SRob Herring compatible = "renesas,r8a77470-apmu", "renesas,apmu"; 209*724ba675SRob Herring reg = <0 0xe6151000 0 0x188>; 210*724ba675SRob Herring cpus = <&cpu0>, <&cpu1>; 211*724ba675SRob Herring }; 212*724ba675SRob Herring 213*724ba675SRob Herring rst: reset-controller@e6160000 { 214*724ba675SRob Herring compatible = "renesas,r8a77470-rst"; 215*724ba675SRob Herring reg = <0 0xe6160000 0 0x100>; 216*724ba675SRob Herring }; 217*724ba675SRob Herring 218*724ba675SRob Herring sysc: system-controller@e6180000 { 219*724ba675SRob Herring compatible = "renesas,r8a77470-sysc"; 220*724ba675SRob Herring reg = <0 0xe6180000 0 0x200>; 221*724ba675SRob Herring #power-domain-cells = <1>; 222*724ba675SRob Herring }; 223*724ba675SRob Herring 224*724ba675SRob Herring irqc: interrupt-controller@e61c0000 { 225*724ba675SRob Herring compatible = "renesas,irqc-r8a77470", "renesas,irqc"; 226*724ba675SRob Herring #interrupt-cells = <2>; 227*724ba675SRob Herring interrupt-controller; 228*724ba675SRob Herring reg = <0 0xe61c0000 0 0x200>; 229*724ba675SRob Herring interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 230*724ba675SRob Herring <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 231*724ba675SRob Herring <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 232*724ba675SRob Herring <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 233*724ba675SRob Herring <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 234*724ba675SRob Herring <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 235*724ba675SRob Herring <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 236*724ba675SRob Herring <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 237*724ba675SRob Herring <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 238*724ba675SRob Herring <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 239*724ba675SRob Herring clocks = <&cpg CPG_MOD 407>; 240*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 241*724ba675SRob Herring resets = <&cpg 407>; 242*724ba675SRob Herring }; 243*724ba675SRob Herring 244*724ba675SRob Herring icram0: sram@e63a0000 { 245*724ba675SRob Herring compatible = "mmio-sram"; 246*724ba675SRob Herring reg = <0 0xe63a0000 0 0x12000>; 247*724ba675SRob Herring #address-cells = <1>; 248*724ba675SRob Herring #size-cells = <1>; 249*724ba675SRob Herring ranges = <0 0 0xe63a0000 0x12000>; 250*724ba675SRob Herring }; 251*724ba675SRob Herring 252*724ba675SRob Herring icram1: sram@e63c0000 { 253*724ba675SRob Herring compatible = "mmio-sram"; 254*724ba675SRob Herring reg = <0 0xe63c0000 0 0x1000>; 255*724ba675SRob Herring #address-cells = <1>; 256*724ba675SRob Herring #size-cells = <1>; 257*724ba675SRob Herring ranges = <0 0 0xe63c0000 0x1000>; 258*724ba675SRob Herring 259*724ba675SRob Herring smp-sram@0 { 260*724ba675SRob Herring compatible = "renesas,smp-sram"; 261*724ba675SRob Herring reg = <0 0x100>; 262*724ba675SRob Herring }; 263*724ba675SRob Herring }; 264*724ba675SRob Herring 265*724ba675SRob Herring icram2: sram@e6300000 { 266*724ba675SRob Herring compatible = "mmio-sram"; 267*724ba675SRob Herring reg = <0 0xe6300000 0 0x20000>; 268*724ba675SRob Herring #address-cells = <1>; 269*724ba675SRob Herring #size-cells = <1>; 270*724ba675SRob Herring ranges = <0 0 0xe6300000 0x20000>; 271*724ba675SRob Herring }; 272*724ba675SRob Herring 273*724ba675SRob Herring i2c0: i2c@e6508000 { 274*724ba675SRob Herring #address-cells = <1>; 275*724ba675SRob Herring #size-cells = <0>; 276*724ba675SRob Herring compatible = "renesas,i2c-r8a77470", 277*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 278*724ba675SRob Herring reg = <0 0xe6508000 0 0x40>; 279*724ba675SRob Herring interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 280*724ba675SRob Herring clocks = <&cpg CPG_MOD 931>; 281*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 282*724ba675SRob Herring resets = <&cpg 931>; 283*724ba675SRob Herring i2c-scl-internal-delay-ns = <6>; 284*724ba675SRob Herring status = "disabled"; 285*724ba675SRob Herring }; 286*724ba675SRob Herring 287*724ba675SRob Herring i2c1: i2c@e6518000 { 288*724ba675SRob Herring #address-cells = <1>; 289*724ba675SRob Herring #size-cells = <0>; 290*724ba675SRob Herring compatible = "renesas,i2c-r8a77470", 291*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 292*724ba675SRob Herring reg = <0 0xe6518000 0 0x40>; 293*724ba675SRob Herring interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 294*724ba675SRob Herring clocks = <&cpg CPG_MOD 930>; 295*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 296*724ba675SRob Herring resets = <&cpg 930>; 297*724ba675SRob Herring i2c-scl-internal-delay-ns = <6>; 298*724ba675SRob Herring status = "disabled"; 299*724ba675SRob Herring }; 300*724ba675SRob Herring 301*724ba675SRob Herring i2c2: i2c@e6530000 { 302*724ba675SRob Herring #address-cells = <1>; 303*724ba675SRob Herring #size-cells = <0>; 304*724ba675SRob Herring compatible = "renesas,i2c-r8a77470", 305*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 306*724ba675SRob Herring reg = <0 0xe6530000 0 0x40>; 307*724ba675SRob Herring interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 308*724ba675SRob Herring clocks = <&cpg CPG_MOD 929>; 309*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 310*724ba675SRob Herring resets = <&cpg 929>; 311*724ba675SRob Herring i2c-scl-internal-delay-ns = <6>; 312*724ba675SRob Herring status = "disabled"; 313*724ba675SRob Herring }; 314*724ba675SRob Herring 315*724ba675SRob Herring i2c3: i2c@e6540000 { 316*724ba675SRob Herring #address-cells = <1>; 317*724ba675SRob Herring #size-cells = <0>; 318*724ba675SRob Herring compatible = "renesas,i2c-r8a77470", 319*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 320*724ba675SRob Herring reg = <0 0xe6540000 0 0x40>; 321*724ba675SRob Herring interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 322*724ba675SRob Herring clocks = <&cpg CPG_MOD 928>; 323*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 324*724ba675SRob Herring resets = <&cpg 928>; 325*724ba675SRob Herring i2c-scl-internal-delay-ns = <6>; 326*724ba675SRob Herring status = "disabled"; 327*724ba675SRob Herring }; 328*724ba675SRob Herring 329*724ba675SRob Herring i2c4: i2c@e6520000 { 330*724ba675SRob Herring #address-cells = <1>; 331*724ba675SRob Herring #size-cells = <0>; 332*724ba675SRob Herring compatible = "renesas,i2c-r8a77470", 333*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 334*724ba675SRob Herring reg = <0 0xe6520000 0 0x40>; 335*724ba675SRob Herring interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 336*724ba675SRob Herring clocks = <&cpg CPG_MOD 927>; 337*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 338*724ba675SRob Herring resets = <&cpg 927>; 339*724ba675SRob Herring i2c-scl-internal-delay-ns = <6>; 340*724ba675SRob Herring status = "disabled"; 341*724ba675SRob Herring }; 342*724ba675SRob Herring 343*724ba675SRob Herring hsusb0: hsusb@e6590000 { 344*724ba675SRob Herring compatible = "renesas,usbhs-r8a77470", 345*724ba675SRob Herring "renesas,rcar-gen2-usbhs"; 346*724ba675SRob Herring reg = <0 0xe6590000 0 0x100>; 347*724ba675SRob Herring interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 348*724ba675SRob Herring clocks = <&cpg CPG_MOD 704>; 349*724ba675SRob Herring dmas = <&usb_dmac00 0>, <&usb_dmac00 1>, 350*724ba675SRob Herring <&usb_dmac10 0>, <&usb_dmac10 1>; 351*724ba675SRob Herring dma-names = "ch0", "ch1", "ch2", "ch3"; 352*724ba675SRob Herring renesas,buswait = <4>; 353*724ba675SRob Herring phys = <&usb0 1>; 354*724ba675SRob Herring phy-names = "usb"; 355*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 356*724ba675SRob Herring resets = <&cpg 704>; 357*724ba675SRob Herring status = "disabled"; 358*724ba675SRob Herring }; 359*724ba675SRob Herring 360*724ba675SRob Herring usbphy0: usb-phy-controller@e6590100 { 361*724ba675SRob Herring compatible = "renesas,usb-phy-r8a77470", 362*724ba675SRob Herring "renesas,rcar-gen2-usb-phy"; 363*724ba675SRob Herring reg = <0 0xe6590100 0 0x100>; 364*724ba675SRob Herring #address-cells = <1>; 365*724ba675SRob Herring #size-cells = <0>; 366*724ba675SRob Herring clocks = <&cpg CPG_MOD 704>; 367*724ba675SRob Herring clock-names = "usbhs"; 368*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 369*724ba675SRob Herring resets = <&cpg 704>; 370*724ba675SRob Herring status = "disabled"; 371*724ba675SRob Herring 372*724ba675SRob Herring usb0: usb-phy@0 { 373*724ba675SRob Herring reg = <0>; 374*724ba675SRob Herring #phy-cells = <1>; 375*724ba675SRob Herring }; 376*724ba675SRob Herring }; 377*724ba675SRob Herring 378*724ba675SRob Herring hsusb1: hsusb@e6598000 { 379*724ba675SRob Herring compatible = "renesas,usbhs-r8a77470", 380*724ba675SRob Herring "renesas,rcar-gen2-usbhs"; 381*724ba675SRob Herring reg = <0 0xe6598000 0 0x100>; 382*724ba675SRob Herring interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>; 383*724ba675SRob Herring clocks = <&cpg CPG_MOD 706>; 384*724ba675SRob Herring dmas = <&usb_dmac01 0>, <&usb_dmac01 1>, 385*724ba675SRob Herring <&usb_dmac11 0>, <&usb_dmac11 1>; 386*724ba675SRob Herring dma-names = "ch0", "ch1", "ch2", "ch3"; 387*724ba675SRob Herring renesas,buswait = <4>; 388*724ba675SRob Herring /* We need to turn on usbphy0 to make usbphy1 to work */ 389*724ba675SRob Herring phys = <&usb1 1>; 390*724ba675SRob Herring phy-names = "usb"; 391*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 392*724ba675SRob Herring resets = <&cpg 706>; 393*724ba675SRob Herring status = "disabled"; 394*724ba675SRob Herring }; 395*724ba675SRob Herring 396*724ba675SRob Herring usbphy1: usb-phy-controller@e6598100 { 397*724ba675SRob Herring compatible = "renesas,usb-phy-r8a77470", 398*724ba675SRob Herring "renesas,rcar-gen2-usb-phy"; 399*724ba675SRob Herring reg = <0 0xe6598100 0 0x100>; 400*724ba675SRob Herring #address-cells = <1>; 401*724ba675SRob Herring #size-cells = <0>; 402*724ba675SRob Herring clocks = <&cpg CPG_MOD 706>; 403*724ba675SRob Herring clock-names = "usbhs"; 404*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 405*724ba675SRob Herring resets = <&cpg 706>; 406*724ba675SRob Herring status = "disabled"; 407*724ba675SRob Herring 408*724ba675SRob Herring usb1: usb-phy@0 { 409*724ba675SRob Herring reg = <0>; 410*724ba675SRob Herring #phy-cells = <1>; 411*724ba675SRob Herring }; 412*724ba675SRob Herring }; 413*724ba675SRob Herring 414*724ba675SRob Herring usb_dmac00: dma-controller@e65a0000 { 415*724ba675SRob Herring compatible = "renesas,r8a77470-usb-dmac", 416*724ba675SRob Herring "renesas,usb-dmac"; 417*724ba675SRob Herring reg = <0 0xe65a0000 0 0x100>; 418*724ba675SRob Herring interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 419*724ba675SRob Herring <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 420*724ba675SRob Herring interrupt-names = "ch0", "ch1"; 421*724ba675SRob Herring clocks = <&cpg CPG_MOD 330>; 422*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 423*724ba675SRob Herring resets = <&cpg 330>; 424*724ba675SRob Herring #dma-cells = <1>; 425*724ba675SRob Herring dma-channels = <2>; 426*724ba675SRob Herring }; 427*724ba675SRob Herring 428*724ba675SRob Herring usb_dmac10: dma-controller@e65b0000 { 429*724ba675SRob Herring compatible = "renesas,r8a77470-usb-dmac", 430*724ba675SRob Herring "renesas,usb-dmac"; 431*724ba675SRob Herring reg = <0 0xe65b0000 0 0x100>; 432*724ba675SRob Herring interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 433*724ba675SRob Herring <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 434*724ba675SRob Herring interrupt-names = "ch0", "ch1"; 435*724ba675SRob Herring clocks = <&cpg CPG_MOD 331>; 436*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 437*724ba675SRob Herring resets = <&cpg 331>; 438*724ba675SRob Herring #dma-cells = <1>; 439*724ba675SRob Herring dma-channels = <2>; 440*724ba675SRob Herring }; 441*724ba675SRob Herring 442*724ba675SRob Herring usb_dmac01: dma-controller@e65a8000 { 443*724ba675SRob Herring compatible = "renesas,r8a77470-usb-dmac", 444*724ba675SRob Herring "renesas,usb-dmac"; 445*724ba675SRob Herring reg = <0 0xe65a8000 0 0x100>; 446*724ba675SRob Herring interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 447*724ba675SRob Herring <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>; 448*724ba675SRob Herring interrupt-names = "ch0", "ch1"; 449*724ba675SRob Herring clocks = <&cpg CPG_MOD 326>; 450*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 451*724ba675SRob Herring resets = <&cpg 326>; 452*724ba675SRob Herring #dma-cells = <1>; 453*724ba675SRob Herring dma-channels = <2>; 454*724ba675SRob Herring }; 455*724ba675SRob Herring 456*724ba675SRob Herring usb_dmac11: dma-controller@e65b8000 { 457*724ba675SRob Herring compatible = "renesas,r8a77470-usb-dmac", 458*724ba675SRob Herring "renesas,usb-dmac"; 459*724ba675SRob Herring reg = <0 0xe65b8000 0 0x100>; 460*724ba675SRob Herring interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 461*724ba675SRob Herring <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 462*724ba675SRob Herring interrupt-names = "ch0", "ch1"; 463*724ba675SRob Herring clocks = <&cpg CPG_MOD 327>; 464*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 465*724ba675SRob Herring resets = <&cpg 327>; 466*724ba675SRob Herring #dma-cells = <1>; 467*724ba675SRob Herring dma-channels = <2>; 468*724ba675SRob Herring }; 469*724ba675SRob Herring 470*724ba675SRob Herring dmac0: dma-controller@e6700000 { 471*724ba675SRob Herring compatible = "renesas,dmac-r8a77470", 472*724ba675SRob Herring "renesas,rcar-dmac"; 473*724ba675SRob Herring reg = <0 0xe6700000 0 0x20000>; 474*724ba675SRob Herring interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 475*724ba675SRob Herring <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 476*724ba675SRob Herring <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 477*724ba675SRob Herring <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 478*724ba675SRob Herring <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 479*724ba675SRob Herring <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 480*724ba675SRob Herring <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 481*724ba675SRob Herring <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 482*724ba675SRob Herring <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 483*724ba675SRob Herring <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 484*724ba675SRob Herring <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 485*724ba675SRob Herring <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 486*724ba675SRob Herring <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 487*724ba675SRob Herring <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 488*724ba675SRob Herring <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 489*724ba675SRob Herring <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 490*724ba675SRob Herring interrupt-names = "error", 491*724ba675SRob Herring "ch0", "ch1", "ch2", "ch3", 492*724ba675SRob Herring "ch4", "ch5", "ch6", "ch7", 493*724ba675SRob Herring "ch8", "ch9", "ch10", "ch11", 494*724ba675SRob Herring "ch12", "ch13", "ch14"; 495*724ba675SRob Herring clocks = <&cpg CPG_MOD 219>; 496*724ba675SRob Herring clock-names = "fck"; 497*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 498*724ba675SRob Herring resets = <&cpg 219>; 499*724ba675SRob Herring #dma-cells = <1>; 500*724ba675SRob Herring dma-channels = <15>; 501*724ba675SRob Herring }; 502*724ba675SRob Herring 503*724ba675SRob Herring dmac1: dma-controller@e6720000 { 504*724ba675SRob Herring compatible = "renesas,dmac-r8a77470", 505*724ba675SRob Herring "renesas,rcar-dmac"; 506*724ba675SRob Herring reg = <0 0xe6720000 0 0x20000>; 507*724ba675SRob Herring interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 508*724ba675SRob Herring <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 509*724ba675SRob Herring <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 510*724ba675SRob Herring <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 511*724ba675SRob Herring <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 512*724ba675SRob Herring <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 513*724ba675SRob Herring <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 514*724ba675SRob Herring <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 515*724ba675SRob Herring <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 516*724ba675SRob Herring <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 517*724ba675SRob Herring <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 518*724ba675SRob Herring <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 519*724ba675SRob Herring <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 520*724ba675SRob Herring <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 521*724ba675SRob Herring <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 522*724ba675SRob Herring <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 523*724ba675SRob Herring interrupt-names = "error", 524*724ba675SRob Herring "ch0", "ch1", "ch2", "ch3", 525*724ba675SRob Herring "ch4", "ch5", "ch6", "ch7", 526*724ba675SRob Herring "ch8", "ch9", "ch10", "ch11", 527*724ba675SRob Herring "ch12", "ch13", "ch14"; 528*724ba675SRob Herring clocks = <&cpg CPG_MOD 218>; 529*724ba675SRob Herring clock-names = "fck"; 530*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 531*724ba675SRob Herring resets = <&cpg 218>; 532*724ba675SRob Herring #dma-cells = <1>; 533*724ba675SRob Herring dma-channels = <15>; 534*724ba675SRob Herring }; 535*724ba675SRob Herring 536*724ba675SRob Herring avb: ethernet@e6800000 { 537*724ba675SRob Herring compatible = "renesas,etheravb-r8a77470", 538*724ba675SRob Herring "renesas,etheravb-rcar-gen2"; 539*724ba675SRob Herring reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 540*724ba675SRob Herring interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 541*724ba675SRob Herring clocks = <&cpg CPG_MOD 812>; 542*724ba675SRob Herring clock-names = "fck"; 543*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 544*724ba675SRob Herring resets = <&cpg 812>; 545*724ba675SRob Herring #address-cells = <1>; 546*724ba675SRob Herring #size-cells = <0>; 547*724ba675SRob Herring status = "disabled"; 548*724ba675SRob Herring }; 549*724ba675SRob Herring 550*724ba675SRob Herring qspi0: spi@e6b10000 { 551*724ba675SRob Herring compatible = "renesas,qspi-r8a77470", "renesas,qspi"; 552*724ba675SRob Herring reg = <0 0xe6b10000 0 0x2c>; 553*724ba675SRob Herring interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 554*724ba675SRob Herring clocks = <&cpg CPG_MOD 918>; 555*724ba675SRob Herring dmas = <&dmac0 0x17>, <&dmac0 0x18>, 556*724ba675SRob Herring <&dmac1 0x17>, <&dmac1 0x18>; 557*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 558*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 559*724ba675SRob Herring num-cs = <1>; 560*724ba675SRob Herring #address-cells = <1>; 561*724ba675SRob Herring #size-cells = <0>; 562*724ba675SRob Herring resets = <&cpg 918>; 563*724ba675SRob Herring status = "disabled"; 564*724ba675SRob Herring }; 565*724ba675SRob Herring 566*724ba675SRob Herring qspi1: spi@ee200000 { 567*724ba675SRob Herring compatible = "renesas,qspi-r8a77470", "renesas,qspi"; 568*724ba675SRob Herring reg = <0 0xee200000 0 0x2c>; 569*724ba675SRob Herring interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 570*724ba675SRob Herring clocks = <&cpg CPG_MOD 917>; 571*724ba675SRob Herring dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, 572*724ba675SRob Herring <&dmac1 0xd1>, <&dmac1 0xd2>; 573*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 574*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 575*724ba675SRob Herring num-cs = <1>; 576*724ba675SRob Herring #address-cells = <1>; 577*724ba675SRob Herring #size-cells = <0>; 578*724ba675SRob Herring resets = <&cpg 917>; 579*724ba675SRob Herring status = "disabled"; 580*724ba675SRob Herring }; 581*724ba675SRob Herring 582*724ba675SRob Herring scif0: serial@e6e60000 { 583*724ba675SRob Herring compatible = "renesas,scif-r8a77470", 584*724ba675SRob Herring "renesas,rcar-gen2-scif", "renesas,scif"; 585*724ba675SRob Herring reg = <0 0xe6e60000 0 0x40>; 586*724ba675SRob Herring interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 587*724ba675SRob Herring clocks = <&cpg CPG_MOD 721>, 588*724ba675SRob Herring <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; 589*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 590*724ba675SRob Herring dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 591*724ba675SRob Herring <&dmac1 0x29>, <&dmac1 0x2a>; 592*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 593*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 594*724ba675SRob Herring resets = <&cpg 721>; 595*724ba675SRob Herring status = "disabled"; 596*724ba675SRob Herring }; 597*724ba675SRob Herring 598*724ba675SRob Herring scif1: serial@e6e68000 { 599*724ba675SRob Herring compatible = "renesas,scif-r8a77470", 600*724ba675SRob Herring "renesas,rcar-gen2-scif", "renesas,scif"; 601*724ba675SRob Herring reg = <0 0xe6e68000 0 0x40>; 602*724ba675SRob Herring interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 603*724ba675SRob Herring clocks = <&cpg CPG_MOD 720>, 604*724ba675SRob Herring <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; 605*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 606*724ba675SRob Herring dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 607*724ba675SRob Herring <&dmac1 0x2d>, <&dmac1 0x2e>; 608*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 609*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 610*724ba675SRob Herring resets = <&cpg 720>; 611*724ba675SRob Herring status = "disabled"; 612*724ba675SRob Herring }; 613*724ba675SRob Herring 614*724ba675SRob Herring scif2: serial@e6e58000 { 615*724ba675SRob Herring compatible = "renesas,scif-r8a77470", 616*724ba675SRob Herring "renesas,rcar-gen2-scif", "renesas,scif"; 617*724ba675SRob Herring reg = <0 0xe6e58000 0 0x40>; 618*724ba675SRob Herring interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 619*724ba675SRob Herring clocks = <&cpg CPG_MOD 719>, 620*724ba675SRob Herring <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; 621*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 622*724ba675SRob Herring dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 623*724ba675SRob Herring <&dmac1 0x2b>, <&dmac1 0x2c>; 624*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 625*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 626*724ba675SRob Herring resets = <&cpg 719>; 627*724ba675SRob Herring status = "disabled"; 628*724ba675SRob Herring }; 629*724ba675SRob Herring 630*724ba675SRob Herring scif3: serial@e6ea8000 { 631*724ba675SRob Herring compatible = "renesas,scif-r8a77470", 632*724ba675SRob Herring "renesas,rcar-gen2-scif", "renesas,scif"; 633*724ba675SRob Herring reg = <0 0xe6ea8000 0 0x40>; 634*724ba675SRob Herring interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 635*724ba675SRob Herring clocks = <&cpg CPG_MOD 718>, 636*724ba675SRob Herring <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; 637*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 638*724ba675SRob Herring dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 639*724ba675SRob Herring <&dmac1 0x2f>, <&dmac1 0x30>; 640*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 641*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 642*724ba675SRob Herring resets = <&cpg 718>; 643*724ba675SRob Herring status = "disabled"; 644*724ba675SRob Herring }; 645*724ba675SRob Herring 646*724ba675SRob Herring scif4: serial@e6ee0000 { 647*724ba675SRob Herring compatible = "renesas,scif-r8a77470", 648*724ba675SRob Herring "renesas,rcar-gen2-scif", "renesas,scif"; 649*724ba675SRob Herring reg = <0 0xe6ee0000 0 0x40>; 650*724ba675SRob Herring interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 651*724ba675SRob Herring clocks = <&cpg CPG_MOD 715>, 652*724ba675SRob Herring <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; 653*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 654*724ba675SRob Herring dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, 655*724ba675SRob Herring <&dmac1 0xfb>, <&dmac1 0xfc>; 656*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 657*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 658*724ba675SRob Herring resets = <&cpg 715>; 659*724ba675SRob Herring status = "disabled"; 660*724ba675SRob Herring }; 661*724ba675SRob Herring 662*724ba675SRob Herring scif5: serial@e6ee8000 { 663*724ba675SRob Herring compatible = "renesas,scif-r8a77470", 664*724ba675SRob Herring "renesas,rcar-gen2-scif", "renesas,scif"; 665*724ba675SRob Herring reg = <0 0xe6ee8000 0 0x40>; 666*724ba675SRob Herring interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 667*724ba675SRob Herring clocks = <&cpg CPG_MOD 714>, 668*724ba675SRob Herring <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; 669*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 670*724ba675SRob Herring dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, 671*724ba675SRob Herring <&dmac1 0xfd>, <&dmac1 0xfe>; 672*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 673*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 674*724ba675SRob Herring resets = <&cpg 714>; 675*724ba675SRob Herring status = "disabled"; 676*724ba675SRob Herring }; 677*724ba675SRob Herring 678*724ba675SRob Herring hscif0: serial@e62c0000 { 679*724ba675SRob Herring compatible = "renesas,hscif-r8a77470", 680*724ba675SRob Herring "renesas,rcar-gen2-hscif", "renesas,hscif"; 681*724ba675SRob Herring reg = <0 0xe62c0000 0 0x60>; 682*724ba675SRob Herring interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 683*724ba675SRob Herring clocks = <&cpg CPG_MOD 717>, 684*724ba675SRob Herring <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; 685*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 686*724ba675SRob Herring dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 687*724ba675SRob Herring <&dmac1 0x39>, <&dmac1 0x3a>; 688*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 689*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 690*724ba675SRob Herring resets = <&cpg 717>; 691*724ba675SRob Herring status = "disabled"; 692*724ba675SRob Herring }; 693*724ba675SRob Herring 694*724ba675SRob Herring hscif1: serial@e62c8000 { 695*724ba675SRob Herring compatible = "renesas,hscif-r8a77470", 696*724ba675SRob Herring "renesas,rcar-gen2-hscif", "renesas,hscif"; 697*724ba675SRob Herring reg = <0 0xe62c8000 0 0x60>; 698*724ba675SRob Herring interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 699*724ba675SRob Herring clocks = <&cpg CPG_MOD 716>, 700*724ba675SRob Herring <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; 701*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 702*724ba675SRob Herring dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 703*724ba675SRob Herring <&dmac1 0x4d>, <&dmac1 0x4e>; 704*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 705*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 706*724ba675SRob Herring resets = <&cpg 716>; 707*724ba675SRob Herring status = "disabled"; 708*724ba675SRob Herring }; 709*724ba675SRob Herring 710*724ba675SRob Herring hscif2: serial@e62d0000 { 711*724ba675SRob Herring compatible = "renesas,hscif-r8a77470", 712*724ba675SRob Herring "renesas,rcar-gen2-hscif", "renesas,hscif"; 713*724ba675SRob Herring reg = <0 0xe62d0000 0 0x60>; 714*724ba675SRob Herring interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 715*724ba675SRob Herring clocks = <&cpg CPG_MOD 713>, 716*724ba675SRob Herring <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; 717*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 718*724ba675SRob Herring dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, 719*724ba675SRob Herring <&dmac1 0x3b>, <&dmac1 0x3c>; 720*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 721*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 722*724ba675SRob Herring resets = <&cpg 713>; 723*724ba675SRob Herring status = "disabled"; 724*724ba675SRob Herring }; 725*724ba675SRob Herring 726*724ba675SRob Herring pwm0: pwm@e6e30000 { 727*724ba675SRob Herring compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; 728*724ba675SRob Herring reg = <0 0xe6e30000 0 0x8>; 729*724ba675SRob Herring clocks = <&cpg CPG_MOD 523>; 730*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 731*724ba675SRob Herring resets = <&cpg 523>; 732*724ba675SRob Herring #pwm-cells = <2>; 733*724ba675SRob Herring status = "disabled"; 734*724ba675SRob Herring }; 735*724ba675SRob Herring 736*724ba675SRob Herring pwm1: pwm@e6e31000 { 737*724ba675SRob Herring compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; 738*724ba675SRob Herring reg = <0 0xe6e31000 0 0x8>; 739*724ba675SRob Herring clocks = <&cpg CPG_MOD 523>; 740*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 741*724ba675SRob Herring resets = <&cpg 523>; 742*724ba675SRob Herring #pwm-cells = <2>; 743*724ba675SRob Herring status = "disabled"; 744*724ba675SRob Herring }; 745*724ba675SRob Herring 746*724ba675SRob Herring pwm2: pwm@e6e32000 { 747*724ba675SRob Herring compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; 748*724ba675SRob Herring reg = <0 0xe6e32000 0 0x8>; 749*724ba675SRob Herring clocks = <&cpg CPG_MOD 523>; 750*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 751*724ba675SRob Herring resets = <&cpg 523>; 752*724ba675SRob Herring #pwm-cells = <2>; 753*724ba675SRob Herring status = "disabled"; 754*724ba675SRob Herring }; 755*724ba675SRob Herring 756*724ba675SRob Herring pwm3: pwm@e6e33000 { 757*724ba675SRob Herring compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; 758*724ba675SRob Herring reg = <0 0xe6e33000 0 0x8>; 759*724ba675SRob Herring clocks = <&cpg CPG_MOD 523>; 760*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 761*724ba675SRob Herring resets = <&cpg 523>; 762*724ba675SRob Herring #pwm-cells = <2>; 763*724ba675SRob Herring status = "disabled"; 764*724ba675SRob Herring }; 765*724ba675SRob Herring 766*724ba675SRob Herring pwm4: pwm@e6e34000 { 767*724ba675SRob Herring compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; 768*724ba675SRob Herring reg = <0 0xe6e34000 0 0x8>; 769*724ba675SRob Herring clocks = <&cpg CPG_MOD 523>; 770*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 771*724ba675SRob Herring resets = <&cpg 523>; 772*724ba675SRob Herring #pwm-cells = <2>; 773*724ba675SRob Herring status = "disabled"; 774*724ba675SRob Herring }; 775*724ba675SRob Herring 776*724ba675SRob Herring pwm5: pwm@e6e35000 { 777*724ba675SRob Herring compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; 778*724ba675SRob Herring reg = <0 0xe6e35000 0 0x8>; 779*724ba675SRob Herring clocks = <&cpg CPG_MOD 523>; 780*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 781*724ba675SRob Herring resets = <&cpg 523>; 782*724ba675SRob Herring #pwm-cells = <2>; 783*724ba675SRob Herring status = "disabled"; 784*724ba675SRob Herring }; 785*724ba675SRob Herring 786*724ba675SRob Herring pwm6: pwm@e6e36000 { 787*724ba675SRob Herring compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; 788*724ba675SRob Herring reg = <0 0xe6e36000 0 0x8>; 789*724ba675SRob Herring clocks = <&cpg CPG_MOD 523>; 790*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 791*724ba675SRob Herring resets = <&cpg 523>; 792*724ba675SRob Herring #pwm-cells = <2>; 793*724ba675SRob Herring status = "disabled"; 794*724ba675SRob Herring }; 795*724ba675SRob Herring 796*724ba675SRob Herring vin0: video@e6ef0000 { 797*724ba675SRob Herring compatible = "renesas,vin-r8a77470", 798*724ba675SRob Herring "renesas,rcar-gen2-vin"; 799*724ba675SRob Herring reg = <0 0xe6ef0000 0 0x1000>; 800*724ba675SRob Herring interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 801*724ba675SRob Herring clocks = <&cpg CPG_MOD 811>; 802*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 803*724ba675SRob Herring resets = <&cpg 811>; 804*724ba675SRob Herring status = "disabled"; 805*724ba675SRob Herring }; 806*724ba675SRob Herring 807*724ba675SRob Herring vin1: video@e6ef1000 { 808*724ba675SRob Herring compatible = "renesas,vin-r8a77470", 809*724ba675SRob Herring "renesas,rcar-gen2-vin"; 810*724ba675SRob Herring reg = <0 0xe6ef1000 0 0x1000>; 811*724ba675SRob Herring interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 812*724ba675SRob Herring clocks = <&cpg CPG_MOD 810>; 813*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 814*724ba675SRob Herring resets = <&cpg 810>; 815*724ba675SRob Herring status = "disabled"; 816*724ba675SRob Herring }; 817*724ba675SRob Herring 818*724ba675SRob Herring ohci0: usb@ee080000 { 819*724ba675SRob Herring compatible = "generic-ohci"; 820*724ba675SRob Herring reg = <0 0xee080000 0 0x100>; 821*724ba675SRob Herring interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 822*724ba675SRob Herring clocks = <&cpg CPG_MOD 703>; 823*724ba675SRob Herring phys = <&usb0 0>, <&usb2_phy0>; 824*724ba675SRob Herring phy-names = "usb"; 825*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 826*724ba675SRob Herring resets = <&cpg 703>; 827*724ba675SRob Herring status = "disabled"; 828*724ba675SRob Herring }; 829*724ba675SRob Herring 830*724ba675SRob Herring ehci0: usb@ee080100 { 831*724ba675SRob Herring compatible = "generic-ehci"; 832*724ba675SRob Herring reg = <0 0xee080100 0 0x100>; 833*724ba675SRob Herring interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 834*724ba675SRob Herring clocks = <&cpg CPG_MOD 703>; 835*724ba675SRob Herring phys = <&usb0 0>, <&usb2_phy0>; 836*724ba675SRob Herring phy-names = "usb"; 837*724ba675SRob Herring companion = <&ohci0>; 838*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 839*724ba675SRob Herring resets = <&cpg 703>; 840*724ba675SRob Herring status = "disabled"; 841*724ba675SRob Herring }; 842*724ba675SRob Herring 843*724ba675SRob Herring usb2_phy0: usb-phy@ee080200 { 844*724ba675SRob Herring compatible = "renesas,usb2-phy-r8a77470"; 845*724ba675SRob Herring reg = <0 0xee080200 0 0x700>; 846*724ba675SRob Herring clocks = <&cpg CPG_MOD 703>; 847*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 848*724ba675SRob Herring resets = <&cpg 703>; 849*724ba675SRob Herring #phy-cells = <0>; 850*724ba675SRob Herring status = "disabled"; 851*724ba675SRob Herring }; 852*724ba675SRob Herring 853*724ba675SRob Herring ohci1: usb@ee0c0000 { 854*724ba675SRob Herring compatible = "generic-ohci"; 855*724ba675SRob Herring reg = <0 0xee0c0000 0 0x100>; 856*724ba675SRob Herring interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 857*724ba675SRob Herring clocks = <&cpg CPG_MOD 705>; 858*724ba675SRob Herring phys = <&usb0 1>, <&usb2_phy1>, <&usb1 0>; 859*724ba675SRob Herring phy-names = "usb"; 860*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 861*724ba675SRob Herring resets = <&cpg 705>; 862*724ba675SRob Herring status = "disabled"; 863*724ba675SRob Herring }; 864*724ba675SRob Herring 865*724ba675SRob Herring ehci1: usb@ee0c0100 { 866*724ba675SRob Herring compatible = "generic-ehci"; 867*724ba675SRob Herring reg = <0 0xee0c0100 0 0x100>; 868*724ba675SRob Herring interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 869*724ba675SRob Herring clocks = <&cpg CPG_MOD 705>; 870*724ba675SRob Herring phys = <&usb0 1>, <&usb2_phy1>, <&usb1 0>; 871*724ba675SRob Herring phy-names = "usb"; 872*724ba675SRob Herring companion = <&ohci1>; 873*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 874*724ba675SRob Herring resets = <&cpg 705>; 875*724ba675SRob Herring status = "disabled"; 876*724ba675SRob Herring }; 877*724ba675SRob Herring 878*724ba675SRob Herring usb2_phy1: usb-phy@ee0c0200 { 879*724ba675SRob Herring compatible = "renesas,usb2-phy-r8a77470"; 880*724ba675SRob Herring reg = <0 0xee0c0200 0 0x700>; 881*724ba675SRob Herring clocks = <&cpg CPG_MOD 705>; 882*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 883*724ba675SRob Herring resets = <&cpg 705>; 884*724ba675SRob Herring #phy-cells = <0>; 885*724ba675SRob Herring status = "disabled"; 886*724ba675SRob Herring }; 887*724ba675SRob Herring 888*724ba675SRob Herring sdhi0: mmc@ee100000 { 889*724ba675SRob Herring compatible = "renesas,sdhi-r8a77470", 890*724ba675SRob Herring "renesas,rcar-gen2-sdhi"; 891*724ba675SRob Herring reg = <0 0xee100000 0 0x328>; 892*724ba675SRob Herring interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 893*724ba675SRob Herring clocks = <&cpg CPG_MOD 314>; 894*724ba675SRob Herring dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 895*724ba675SRob Herring <&dmac1 0xcd>, <&dmac1 0xce>; 896*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 897*724ba675SRob Herring max-frequency = <156000000>; 898*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 899*724ba675SRob Herring resets = <&cpg 314>; 900*724ba675SRob Herring status = "disabled"; 901*724ba675SRob Herring }; 902*724ba675SRob Herring 903*724ba675SRob Herring sdhi1: mmc@ee300000 { 904*724ba675SRob Herring compatible = "renesas,sdhi-mmc-r8a77470"; 905*724ba675SRob Herring reg = <0 0xee300000 0 0x2000>; 906*724ba675SRob Herring interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 907*724ba675SRob Herring clocks = <&cpg CPG_MOD 313>; 908*724ba675SRob Herring max-frequency = <156000000>; 909*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 910*724ba675SRob Herring resets = <&cpg 313>; 911*724ba675SRob Herring status = "disabled"; 912*724ba675SRob Herring }; 913*724ba675SRob Herring 914*724ba675SRob Herring sdhi2: mmc@ee160000 { 915*724ba675SRob Herring compatible = "renesas,sdhi-r8a77470", 916*724ba675SRob Herring "renesas,rcar-gen2-sdhi"; 917*724ba675SRob Herring reg = <0 0xee160000 0 0x328>; 918*724ba675SRob Herring interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 919*724ba675SRob Herring clocks = <&cpg CPG_MOD 312>; 920*724ba675SRob Herring dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, 921*724ba675SRob Herring <&dmac1 0xd3>, <&dmac1 0xd4>; 922*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 923*724ba675SRob Herring max-frequency = <78000000>; 924*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 925*724ba675SRob Herring resets = <&cpg 312>; 926*724ba675SRob Herring status = "disabled"; 927*724ba675SRob Herring }; 928*724ba675SRob Herring 929*724ba675SRob Herring gic: interrupt-controller@f1001000 { 930*724ba675SRob Herring compatible = "arm,gic-400"; 931*724ba675SRob Herring #interrupt-cells = <3>; 932*724ba675SRob Herring #address-cells = <0>; 933*724ba675SRob Herring interrupt-controller; 934*724ba675SRob Herring reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, 935*724ba675SRob Herring <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; 936*724ba675SRob Herring interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 937*724ba675SRob Herring clocks = <&cpg CPG_MOD 408>; 938*724ba675SRob Herring clock-names = "clk"; 939*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 940*724ba675SRob Herring resets = <&cpg 408>; 941*724ba675SRob Herring }; 942*724ba675SRob Herring 943*724ba675SRob Herring du: display@feb00000 { 944*724ba675SRob Herring compatible = "renesas,du-r8a77470"; 945*724ba675SRob Herring reg = <0 0xfeb00000 0 0x40000>; 946*724ba675SRob Herring interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 947*724ba675SRob Herring <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 948*724ba675SRob Herring clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 949*724ba675SRob Herring clock-names = "du.0", "du.1"; 950*724ba675SRob Herring resets = <&cpg 724>; 951*724ba675SRob Herring reset-names = "du.0"; 952*724ba675SRob Herring status = "disabled"; 953*724ba675SRob Herring 954*724ba675SRob Herring ports { 955*724ba675SRob Herring #address-cells = <1>; 956*724ba675SRob Herring #size-cells = <0>; 957*724ba675SRob Herring 958*724ba675SRob Herring port@0 { 959*724ba675SRob Herring reg = <0>; 960*724ba675SRob Herring du_out_rgb0: endpoint { 961*724ba675SRob Herring }; 962*724ba675SRob Herring }; 963*724ba675SRob Herring port@1 { 964*724ba675SRob Herring reg = <1>; 965*724ba675SRob Herring du_out_rgb1: endpoint { 966*724ba675SRob Herring }; 967*724ba675SRob Herring }; 968*724ba675SRob Herring port@2 { 969*724ba675SRob Herring reg = <2>; 970*724ba675SRob Herring du_out_lvds0: endpoint { 971*724ba675SRob Herring }; 972*724ba675SRob Herring }; 973*724ba675SRob Herring }; 974*724ba675SRob Herring }; 975*724ba675SRob Herring 976*724ba675SRob Herring prr: chipid@ff000044 { 977*724ba675SRob Herring compatible = "renesas,prr"; 978*724ba675SRob Herring reg = <0 0xff000044 0 4>; 979*724ba675SRob Herring }; 980*724ba675SRob Herring 981*724ba675SRob Herring cmt0: timer@ffca0000 { 982*724ba675SRob Herring compatible = "renesas,r8a77470-cmt0", 983*724ba675SRob Herring "renesas,rcar-gen2-cmt0"; 984*724ba675SRob Herring reg = <0 0xffca0000 0 0x1004>; 985*724ba675SRob Herring interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 986*724ba675SRob Herring <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 987*724ba675SRob Herring clocks = <&cpg CPG_MOD 124>; 988*724ba675SRob Herring clock-names = "fck"; 989*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 990*724ba675SRob Herring resets = <&cpg 124>; 991*724ba675SRob Herring status = "disabled"; 992*724ba675SRob Herring }; 993*724ba675SRob Herring 994*724ba675SRob Herring cmt1: timer@e6130000 { 995*724ba675SRob Herring compatible = "renesas,r8a77470-cmt1", 996*724ba675SRob Herring "renesas,rcar-gen2-cmt1"; 997*724ba675SRob Herring reg = <0 0xe6130000 0 0x1004>; 998*724ba675SRob Herring interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 999*724ba675SRob Herring <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1000*724ba675SRob Herring <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1001*724ba675SRob Herring <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1002*724ba675SRob Herring <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1003*724ba675SRob Herring <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1004*724ba675SRob Herring <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1005*724ba675SRob Herring <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1006*724ba675SRob Herring clocks = <&cpg CPG_MOD 329>; 1007*724ba675SRob Herring clock-names = "fck"; 1008*724ba675SRob Herring power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 1009*724ba675SRob Herring resets = <&cpg 329>; 1010*724ba675SRob Herring status = "disabled"; 1011*724ba675SRob Herring }; 1012*724ba675SRob Herring }; 1013*724ba675SRob Herring 1014*724ba675SRob Herring timer { 1015*724ba675SRob Herring compatible = "arm,armv7-timer"; 1016*724ba675SRob Herring interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1017*724ba675SRob Herring <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1018*724ba675SRob Herring <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1019*724ba675SRob Herring <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1020*724ba675SRob Herring }; 1021*724ba675SRob Herring 1022*724ba675SRob Herring /* External USB clock - can be overridden by the board */ 1023*724ba675SRob Herring usb_extal_clk: usb_extal { 1024*724ba675SRob Herring compatible = "fixed-clock"; 1025*724ba675SRob Herring #clock-cells = <0>; 1026*724ba675SRob Herring clock-frequency = <48000000>; 1027*724ba675SRob Herring }; 1028*724ba675SRob Herring}; 1029