1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0
2*724ba675SRob Herring/*
3*724ba675SRob Herring * Device Tree Source for the SK-RZG1M board
4*724ba675SRob Herring *
5*724ba675SRob Herring * Copyright (C) 2016-2017 Cogent Embedded, Inc.
6*724ba675SRob Herring */
7*724ba675SRob Herring
8*724ba675SRob Herring/dts-v1/;
9*724ba675SRob Herring#include "r8a7743.dtsi"
10*724ba675SRob Herring#include <dt-bindings/gpio/gpio.h>
11*724ba675SRob Herring
12*724ba675SRob Herring/ {
13*724ba675SRob Herring	model = "SK-RZG1M";
14*724ba675SRob Herring	compatible = "renesas,sk-rzg1m", "renesas,r8a7743";
15*724ba675SRob Herring
16*724ba675SRob Herring	aliases {
17*724ba675SRob Herring		serial0 = &scif0;
18*724ba675SRob Herring	};
19*724ba675SRob Herring
20*724ba675SRob Herring	chosen {
21*724ba675SRob Herring		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
22*724ba675SRob Herring		stdout-path = "serial0:115200n8";
23*724ba675SRob Herring	};
24*724ba675SRob Herring
25*724ba675SRob Herring	memory@40000000 {
26*724ba675SRob Herring		device_type = "memory";
27*724ba675SRob Herring		reg = <0 0x40000000 0 0x40000000>;
28*724ba675SRob Herring	};
29*724ba675SRob Herring
30*724ba675SRob Herring	memory@200000000 {
31*724ba675SRob Herring		device_type = "memory";
32*724ba675SRob Herring		reg = <2 0x00000000 0 0x40000000>;
33*724ba675SRob Herring	};
34*724ba675SRob Herring};
35*724ba675SRob Herring
36*724ba675SRob Herring&extal_clk {
37*724ba675SRob Herring	clock-frequency = <20000000>;
38*724ba675SRob Herring};
39*724ba675SRob Herring
40*724ba675SRob Herring&pfc {
41*724ba675SRob Herring	scif0_pins: scif0 {
42*724ba675SRob Herring		groups = "scif0_data_d";
43*724ba675SRob Herring		function = "scif0";
44*724ba675SRob Herring	};
45*724ba675SRob Herring
46*724ba675SRob Herring	ether_pins: ether {
47*724ba675SRob Herring		groups = "eth_link", "eth_mdio", "eth_rmii";
48*724ba675SRob Herring		function = "eth";
49*724ba675SRob Herring	};
50*724ba675SRob Herring
51*724ba675SRob Herring	phy1_pins: phy1 {
52*724ba675SRob Herring		groups = "intc_irq0";
53*724ba675SRob Herring		function = "intc";
54*724ba675SRob Herring	};
55*724ba675SRob Herring};
56*724ba675SRob Herring
57*724ba675SRob Herring&scif0 {
58*724ba675SRob Herring	pinctrl-0 = <&scif0_pins>;
59*724ba675SRob Herring	pinctrl-names = "default";
60*724ba675SRob Herring
61*724ba675SRob Herring	status = "okay";
62*724ba675SRob Herring};
63*724ba675SRob Herring
64*724ba675SRob Herring&ether {
65*724ba675SRob Herring	pinctrl-0 = <&ether_pins>, <&phy1_pins>;
66*724ba675SRob Herring	pinctrl-names = "default";
67*724ba675SRob Herring
68*724ba675SRob Herring	phy-handle = <&phy1>;
69*724ba675SRob Herring	renesas,ether-link-active-low;
70*724ba675SRob Herring	status = "okay";
71*724ba675SRob Herring
72*724ba675SRob Herring	phy1: ethernet-phy@1 {
73*724ba675SRob Herring		compatible = "ethernet-phy-id0022.1537",
74*724ba675SRob Herring			     "ethernet-phy-ieee802.3-c22";
75*724ba675SRob Herring		reg = <1>;
76*724ba675SRob Herring		interrupt-parent = <&irqc>;
77*724ba675SRob Herring		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
78*724ba675SRob Herring		micrel,led-mode = <1>;
79*724ba675SRob Herring		reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
80*724ba675SRob Herring	};
81*724ba675SRob Herring};
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