1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree Source for the r8a7742 SoC 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2020 Renesas Electronics Corp. 6*724ba675SRob Herring */ 7*724ba675SRob Herring 8*724ba675SRob Herring#include <dt-bindings/clock/r8a7742-cpg-mssr.h> 9*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 10*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 11*724ba675SRob Herring#include <dt-bindings/power/r8a7742-sysc.h> 12*724ba675SRob Herring 13*724ba675SRob Herring/ { 14*724ba675SRob Herring compatible = "renesas,r8a7742"; 15*724ba675SRob Herring #address-cells = <2>; 16*724ba675SRob Herring #size-cells = <2>; 17*724ba675SRob Herring 18*724ba675SRob Herring /* 19*724ba675SRob Herring * The external audio clocks are configured as 0 Hz fixed frequency 20*724ba675SRob Herring * clocks by default. 21*724ba675SRob Herring * Boards that provide audio clocks should override them. 22*724ba675SRob Herring */ 23*724ba675SRob Herring audio_clk_a: audio_clk_a { 24*724ba675SRob Herring compatible = "fixed-clock"; 25*724ba675SRob Herring #clock-cells = <0>; 26*724ba675SRob Herring clock-frequency = <0>; 27*724ba675SRob Herring }; 28*724ba675SRob Herring audio_clk_b: audio_clk_b { 29*724ba675SRob Herring compatible = "fixed-clock"; 30*724ba675SRob Herring #clock-cells = <0>; 31*724ba675SRob Herring clock-frequency = <0>; 32*724ba675SRob Herring }; 33*724ba675SRob Herring audio_clk_c: audio_clk_c { 34*724ba675SRob Herring compatible = "fixed-clock"; 35*724ba675SRob Herring #clock-cells = <0>; 36*724ba675SRob Herring clock-frequency = <0>; 37*724ba675SRob Herring }; 38*724ba675SRob Herring 39*724ba675SRob Herring /* External CAN clock */ 40*724ba675SRob Herring can_clk: can { 41*724ba675SRob Herring compatible = "fixed-clock"; 42*724ba675SRob Herring #clock-cells = <0>; 43*724ba675SRob Herring /* This value must be overridden by the board. */ 44*724ba675SRob Herring clock-frequency = <0>; 45*724ba675SRob Herring }; 46*724ba675SRob Herring 47*724ba675SRob Herring cpus { 48*724ba675SRob Herring #address-cells = <1>; 49*724ba675SRob Herring #size-cells = <0>; 50*724ba675SRob Herring 51*724ba675SRob Herring cpu0: cpu@0 { 52*724ba675SRob Herring device_type = "cpu"; 53*724ba675SRob Herring compatible = "arm,cortex-a15"; 54*724ba675SRob Herring reg = <0>; 55*724ba675SRob Herring clock-frequency = <1400000000>; 56*724ba675SRob Herring clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; 57*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_CA15_CPU0>; 58*724ba675SRob Herring enable-method = "renesas,apmu"; 59*724ba675SRob Herring next-level-cache = <&L2_CA15>; 60*724ba675SRob Herring capacity-dmips-mhz = <1024>; 61*724ba675SRob Herring voltage-tolerance = <1>; /* 1% */ 62*724ba675SRob Herring clock-latency = <300000>; /* 300 us */ 63*724ba675SRob Herring 64*724ba675SRob Herring /* kHz - uV - OPPs unknown yet */ 65*724ba675SRob Herring operating-points = <1400000 1000000>, 66*724ba675SRob Herring <1225000 1000000>, 67*724ba675SRob Herring <1050000 1000000>, 68*724ba675SRob Herring < 875000 1000000>, 69*724ba675SRob Herring < 700000 1000000>, 70*724ba675SRob Herring < 350000 1000000>; 71*724ba675SRob Herring }; 72*724ba675SRob Herring 73*724ba675SRob Herring cpu1: cpu@1 { 74*724ba675SRob Herring device_type = "cpu"; 75*724ba675SRob Herring compatible = "arm,cortex-a15"; 76*724ba675SRob Herring reg = <1>; 77*724ba675SRob Herring clock-frequency = <1400000000>; 78*724ba675SRob Herring clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; 79*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_CA15_CPU1>; 80*724ba675SRob Herring enable-method = "renesas,apmu"; 81*724ba675SRob Herring next-level-cache = <&L2_CA15>; 82*724ba675SRob Herring capacity-dmips-mhz = <1024>; 83*724ba675SRob Herring voltage-tolerance = <1>; /* 1% */ 84*724ba675SRob Herring clock-latency = <300000>; /* 300 us */ 85*724ba675SRob Herring 86*724ba675SRob Herring /* kHz - uV - OPPs unknown yet */ 87*724ba675SRob Herring operating-points = <1400000 1000000>, 88*724ba675SRob Herring <1225000 1000000>, 89*724ba675SRob Herring <1050000 1000000>, 90*724ba675SRob Herring < 875000 1000000>, 91*724ba675SRob Herring < 700000 1000000>, 92*724ba675SRob Herring < 350000 1000000>; 93*724ba675SRob Herring }; 94*724ba675SRob Herring 95*724ba675SRob Herring cpu2: cpu@2 { 96*724ba675SRob Herring device_type = "cpu"; 97*724ba675SRob Herring compatible = "arm,cortex-a15"; 98*724ba675SRob Herring reg = <2>; 99*724ba675SRob Herring clock-frequency = <1400000000>; 100*724ba675SRob Herring clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; 101*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_CA15_CPU2>; 102*724ba675SRob Herring enable-method = "renesas,apmu"; 103*724ba675SRob Herring next-level-cache = <&L2_CA15>; 104*724ba675SRob Herring capacity-dmips-mhz = <1024>; 105*724ba675SRob Herring voltage-tolerance = <1>; /* 1% */ 106*724ba675SRob Herring clock-latency = <300000>; /* 300 us */ 107*724ba675SRob Herring 108*724ba675SRob Herring /* kHz - uV - OPPs unknown yet */ 109*724ba675SRob Herring operating-points = <1400000 1000000>, 110*724ba675SRob Herring <1225000 1000000>, 111*724ba675SRob Herring <1050000 1000000>, 112*724ba675SRob Herring < 875000 1000000>, 113*724ba675SRob Herring < 700000 1000000>, 114*724ba675SRob Herring < 350000 1000000>; 115*724ba675SRob Herring }; 116*724ba675SRob Herring 117*724ba675SRob Herring cpu3: cpu@3 { 118*724ba675SRob Herring device_type = "cpu"; 119*724ba675SRob Herring compatible = "arm,cortex-a15"; 120*724ba675SRob Herring reg = <3>; 121*724ba675SRob Herring clock-frequency = <1400000000>; 122*724ba675SRob Herring clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; 123*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_CA15_CPU3>; 124*724ba675SRob Herring enable-method = "renesas,apmu"; 125*724ba675SRob Herring next-level-cache = <&L2_CA15>; 126*724ba675SRob Herring capacity-dmips-mhz = <1024>; 127*724ba675SRob Herring voltage-tolerance = <1>; /* 1% */ 128*724ba675SRob Herring clock-latency = <300000>; /* 300 us */ 129*724ba675SRob Herring 130*724ba675SRob Herring /* kHz - uV - OPPs unknown yet */ 131*724ba675SRob Herring operating-points = <1400000 1000000>, 132*724ba675SRob Herring <1225000 1000000>, 133*724ba675SRob Herring <1050000 1000000>, 134*724ba675SRob Herring < 875000 1000000>, 135*724ba675SRob Herring < 700000 1000000>, 136*724ba675SRob Herring < 350000 1000000>; 137*724ba675SRob Herring }; 138*724ba675SRob Herring 139*724ba675SRob Herring cpu4: cpu@100 { 140*724ba675SRob Herring device_type = "cpu"; 141*724ba675SRob Herring compatible = "arm,cortex-a7"; 142*724ba675SRob Herring reg = <0x100>; 143*724ba675SRob Herring clock-frequency = <780000000>; 144*724ba675SRob Herring clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; 145*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_CA7_CPU0>; 146*724ba675SRob Herring next-level-cache = <&L2_CA7>; 147*724ba675SRob Herring }; 148*724ba675SRob Herring 149*724ba675SRob Herring cpu5: cpu@101 { 150*724ba675SRob Herring device_type = "cpu"; 151*724ba675SRob Herring compatible = "arm,cortex-a7"; 152*724ba675SRob Herring reg = <0x101>; 153*724ba675SRob Herring clock-frequency = <780000000>; 154*724ba675SRob Herring clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; 155*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_CA7_CPU1>; 156*724ba675SRob Herring next-level-cache = <&L2_CA7>; 157*724ba675SRob Herring }; 158*724ba675SRob Herring 159*724ba675SRob Herring cpu6: cpu@102 { 160*724ba675SRob Herring device_type = "cpu"; 161*724ba675SRob Herring compatible = "arm,cortex-a7"; 162*724ba675SRob Herring reg = <0x102>; 163*724ba675SRob Herring clock-frequency = <780000000>; 164*724ba675SRob Herring clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; 165*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_CA7_CPU2>; 166*724ba675SRob Herring next-level-cache = <&L2_CA7>; 167*724ba675SRob Herring }; 168*724ba675SRob Herring 169*724ba675SRob Herring cpu7: cpu@103 { 170*724ba675SRob Herring device_type = "cpu"; 171*724ba675SRob Herring compatible = "arm,cortex-a7"; 172*724ba675SRob Herring reg = <0x103>; 173*724ba675SRob Herring clock-frequency = <780000000>; 174*724ba675SRob Herring clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; 175*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_CA7_CPU3>; 176*724ba675SRob Herring next-level-cache = <&L2_CA7>; 177*724ba675SRob Herring }; 178*724ba675SRob Herring 179*724ba675SRob Herring L2_CA15: cache-controller-0 { 180*724ba675SRob Herring compatible = "cache"; 181*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_CA15_SCU>; 182*724ba675SRob Herring cache-unified; 183*724ba675SRob Herring cache-level = <2>; 184*724ba675SRob Herring }; 185*724ba675SRob Herring 186*724ba675SRob Herring L2_CA7: cache-controller-1 { 187*724ba675SRob Herring compatible = "cache"; 188*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_CA7_SCU>; 189*724ba675SRob Herring cache-unified; 190*724ba675SRob Herring cache-level = <2>; 191*724ba675SRob Herring }; 192*724ba675SRob Herring }; 193*724ba675SRob Herring 194*724ba675SRob Herring /* External root clock */ 195*724ba675SRob Herring extal_clk: extal { 196*724ba675SRob Herring compatible = "fixed-clock"; 197*724ba675SRob Herring #clock-cells = <0>; 198*724ba675SRob Herring /* This value must be overridden by the board. */ 199*724ba675SRob Herring clock-frequency = <0>; 200*724ba675SRob Herring }; 201*724ba675SRob Herring 202*724ba675SRob Herring /* External PCIe clock - can be overridden by the board */ 203*724ba675SRob Herring pcie_bus_clk: pcie_bus { 204*724ba675SRob Herring compatible = "fixed-clock"; 205*724ba675SRob Herring #clock-cells = <0>; 206*724ba675SRob Herring clock-frequency = <0>; 207*724ba675SRob Herring }; 208*724ba675SRob Herring 209*724ba675SRob Herring pmu-0 { 210*724ba675SRob Herring compatible = "arm,cortex-a15-pmu"; 211*724ba675SRob Herring interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 212*724ba675SRob Herring <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 213*724ba675SRob Herring <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 214*724ba675SRob Herring <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 215*724ba675SRob Herring interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 216*724ba675SRob Herring }; 217*724ba675SRob Herring 218*724ba675SRob Herring pmu-1 { 219*724ba675SRob Herring compatible = "arm,cortex-a7-pmu"; 220*724ba675SRob Herring interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 221*724ba675SRob Herring <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 222*724ba675SRob Herring <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 223*724ba675SRob Herring <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 224*724ba675SRob Herring interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 225*724ba675SRob Herring }; 226*724ba675SRob Herring 227*724ba675SRob Herring /* External SCIF clock */ 228*724ba675SRob Herring scif_clk: scif { 229*724ba675SRob Herring compatible = "fixed-clock"; 230*724ba675SRob Herring #clock-cells = <0>; 231*724ba675SRob Herring /* This value must be overridden by the board. */ 232*724ba675SRob Herring clock-frequency = <0>; 233*724ba675SRob Herring }; 234*724ba675SRob Herring 235*724ba675SRob Herring soc { 236*724ba675SRob Herring compatible = "simple-bus"; 237*724ba675SRob Herring interrupt-parent = <&gic>; 238*724ba675SRob Herring 239*724ba675SRob Herring #address-cells = <2>; 240*724ba675SRob Herring #size-cells = <2>; 241*724ba675SRob Herring ranges; 242*724ba675SRob Herring 243*724ba675SRob Herring rwdt: watchdog@e6020000 { 244*724ba675SRob Herring compatible = "renesas,r8a7742-wdt", 245*724ba675SRob Herring "renesas,rcar-gen2-wdt"; 246*724ba675SRob Herring reg = <0 0xe6020000 0 0x0c>; 247*724ba675SRob Herring interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 248*724ba675SRob Herring clocks = <&cpg CPG_MOD 402>; 249*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 250*724ba675SRob Herring resets = <&cpg 402>; 251*724ba675SRob Herring status = "disabled"; 252*724ba675SRob Herring }; 253*724ba675SRob Herring 254*724ba675SRob Herring gpio0: gpio@e6050000 { 255*724ba675SRob Herring compatible = "renesas,gpio-r8a7742", 256*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 257*724ba675SRob Herring reg = <0 0xe6050000 0 0x50>; 258*724ba675SRob Herring interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 259*724ba675SRob Herring #gpio-cells = <2>; 260*724ba675SRob Herring gpio-controller; 261*724ba675SRob Herring gpio-ranges = <&pfc 0 0 32>; 262*724ba675SRob Herring #interrupt-cells = <2>; 263*724ba675SRob Herring interrupt-controller; 264*724ba675SRob Herring clocks = <&cpg CPG_MOD 912>; 265*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 266*724ba675SRob Herring resets = <&cpg 912>; 267*724ba675SRob Herring }; 268*724ba675SRob Herring 269*724ba675SRob Herring gpio1: gpio@e6051000 { 270*724ba675SRob Herring compatible = "renesas,gpio-r8a7742", 271*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 272*724ba675SRob Herring reg = <0 0xe6051000 0 0x50>; 273*724ba675SRob Herring interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 274*724ba675SRob Herring #gpio-cells = <2>; 275*724ba675SRob Herring gpio-controller; 276*724ba675SRob Herring gpio-ranges = <&pfc 0 32 30>; 277*724ba675SRob Herring #interrupt-cells = <2>; 278*724ba675SRob Herring interrupt-controller; 279*724ba675SRob Herring clocks = <&cpg CPG_MOD 911>; 280*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 281*724ba675SRob Herring resets = <&cpg 911>; 282*724ba675SRob Herring }; 283*724ba675SRob Herring 284*724ba675SRob Herring gpio2: gpio@e6052000 { 285*724ba675SRob Herring compatible = "renesas,gpio-r8a7742", 286*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 287*724ba675SRob Herring reg = <0 0xe6052000 0 0x50>; 288*724ba675SRob Herring interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 289*724ba675SRob Herring #gpio-cells = <2>; 290*724ba675SRob Herring gpio-controller; 291*724ba675SRob Herring gpio-ranges = <&pfc 0 64 30>; 292*724ba675SRob Herring #interrupt-cells = <2>; 293*724ba675SRob Herring interrupt-controller; 294*724ba675SRob Herring clocks = <&cpg CPG_MOD 910>; 295*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 296*724ba675SRob Herring resets = <&cpg 910>; 297*724ba675SRob Herring }; 298*724ba675SRob Herring 299*724ba675SRob Herring gpio3: gpio@e6053000 { 300*724ba675SRob Herring compatible = "renesas,gpio-r8a7742", 301*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 302*724ba675SRob Herring reg = <0 0xe6053000 0 0x50>; 303*724ba675SRob Herring interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 304*724ba675SRob Herring #gpio-cells = <2>; 305*724ba675SRob Herring gpio-controller; 306*724ba675SRob Herring gpio-ranges = <&pfc 0 96 32>; 307*724ba675SRob Herring #interrupt-cells = <2>; 308*724ba675SRob Herring interrupt-controller; 309*724ba675SRob Herring clocks = <&cpg CPG_MOD 909>; 310*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 311*724ba675SRob Herring resets = <&cpg 909>; 312*724ba675SRob Herring }; 313*724ba675SRob Herring 314*724ba675SRob Herring gpio4: gpio@e6054000 { 315*724ba675SRob Herring compatible = "renesas,gpio-r8a7742", 316*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 317*724ba675SRob Herring reg = <0 0xe6054000 0 0x50>; 318*724ba675SRob Herring interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 319*724ba675SRob Herring #gpio-cells = <2>; 320*724ba675SRob Herring gpio-controller; 321*724ba675SRob Herring gpio-ranges = <&pfc 0 128 32>; 322*724ba675SRob Herring #interrupt-cells = <2>; 323*724ba675SRob Herring interrupt-controller; 324*724ba675SRob Herring clocks = <&cpg CPG_MOD 908>; 325*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 326*724ba675SRob Herring resets = <&cpg 908>; 327*724ba675SRob Herring }; 328*724ba675SRob Herring 329*724ba675SRob Herring gpio5: gpio@e6055000 { 330*724ba675SRob Herring compatible = "renesas,gpio-r8a7742", 331*724ba675SRob Herring "renesas,rcar-gen2-gpio"; 332*724ba675SRob Herring reg = <0 0xe6055000 0 0x50>; 333*724ba675SRob Herring interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 334*724ba675SRob Herring #gpio-cells = <2>; 335*724ba675SRob Herring gpio-controller; 336*724ba675SRob Herring gpio-ranges = <&pfc 0 160 32>; 337*724ba675SRob Herring #interrupt-cells = <2>; 338*724ba675SRob Herring interrupt-controller; 339*724ba675SRob Herring clocks = <&cpg CPG_MOD 907>; 340*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 341*724ba675SRob Herring resets = <&cpg 907>; 342*724ba675SRob Herring }; 343*724ba675SRob Herring 344*724ba675SRob Herring pfc: pinctrl@e6060000 { 345*724ba675SRob Herring compatible = "renesas,pfc-r8a7742"; 346*724ba675SRob Herring reg = <0 0xe6060000 0 0x250>; 347*724ba675SRob Herring }; 348*724ba675SRob Herring 349*724ba675SRob Herring tpu: pwm@e60f0000 { 350*724ba675SRob Herring compatible = "renesas,tpu-r8a7742", "renesas,tpu"; 351*724ba675SRob Herring reg = <0 0xe60f0000 0 0x148>; 352*724ba675SRob Herring interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 353*724ba675SRob Herring clocks = <&cpg CPG_MOD 304>; 354*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 355*724ba675SRob Herring resets = <&cpg 304>; 356*724ba675SRob Herring #pwm-cells = <3>; 357*724ba675SRob Herring status = "disabled"; 358*724ba675SRob Herring }; 359*724ba675SRob Herring 360*724ba675SRob Herring cpg: clock-controller@e6150000 { 361*724ba675SRob Herring compatible = "renesas,r8a7742-cpg-mssr"; 362*724ba675SRob Herring reg = <0 0xe6150000 0 0x1000>; 363*724ba675SRob Herring clocks = <&extal_clk>, <&usb_extal_clk>; 364*724ba675SRob Herring clock-names = "extal", "usb_extal"; 365*724ba675SRob Herring #clock-cells = <2>; 366*724ba675SRob Herring #power-domain-cells = <0>; 367*724ba675SRob Herring #reset-cells = <1>; 368*724ba675SRob Herring }; 369*724ba675SRob Herring 370*724ba675SRob Herring apmu@e6151000 { 371*724ba675SRob Herring compatible = "renesas,r8a7742-apmu", "renesas,apmu"; 372*724ba675SRob Herring reg = <0 0xe6151000 0 0x188>; 373*724ba675SRob Herring cpus = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 374*724ba675SRob Herring }; 375*724ba675SRob Herring 376*724ba675SRob Herring apmu@e6152000 { 377*724ba675SRob Herring compatible = "renesas,r8a7742-apmu", "renesas,apmu"; 378*724ba675SRob Herring reg = <0 0xe6152000 0 0x188>; 379*724ba675SRob Herring cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 380*724ba675SRob Herring }; 381*724ba675SRob Herring 382*724ba675SRob Herring rst: reset-controller@e6160000 { 383*724ba675SRob Herring compatible = "renesas,r8a7742-rst"; 384*724ba675SRob Herring reg = <0 0xe6160000 0 0x0100>; 385*724ba675SRob Herring }; 386*724ba675SRob Herring 387*724ba675SRob Herring sysc: system-controller@e6180000 { 388*724ba675SRob Herring compatible = "renesas,r8a7742-sysc"; 389*724ba675SRob Herring reg = <0 0xe6180000 0 0x0200>; 390*724ba675SRob Herring #power-domain-cells = <1>; 391*724ba675SRob Herring }; 392*724ba675SRob Herring 393*724ba675SRob Herring irqc: interrupt-controller@e61c0000 { 394*724ba675SRob Herring compatible = "renesas,irqc-r8a7742", "renesas,irqc"; 395*724ba675SRob Herring #interrupt-cells = <2>; 396*724ba675SRob Herring interrupt-controller; 397*724ba675SRob Herring reg = <0 0xe61c0000 0 0x200>; 398*724ba675SRob Herring interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 399*724ba675SRob Herring <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 400*724ba675SRob Herring <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 401*724ba675SRob Herring <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 402*724ba675SRob Herring clocks = <&cpg CPG_MOD 407>; 403*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 404*724ba675SRob Herring resets = <&cpg 407>; 405*724ba675SRob Herring }; 406*724ba675SRob Herring 407*724ba675SRob Herring thermal: thermal@e61f0000 { 408*724ba675SRob Herring compatible = "renesas,thermal-r8a7742", 409*724ba675SRob Herring "renesas,rcar-gen2-thermal"; 410*724ba675SRob Herring reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; 411*724ba675SRob Herring interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 412*724ba675SRob Herring clocks = <&cpg CPG_MOD 522>; 413*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 414*724ba675SRob Herring resets = <&cpg 522>; 415*724ba675SRob Herring #thermal-sensor-cells = <0>; 416*724ba675SRob Herring }; 417*724ba675SRob Herring 418*724ba675SRob Herring ipmmu_sy0: iommu@e6280000 { 419*724ba675SRob Herring compatible = "renesas,ipmmu-r8a7742", 420*724ba675SRob Herring "renesas,ipmmu-vmsa"; 421*724ba675SRob Herring reg = <0 0xe6280000 0 0x1000>; 422*724ba675SRob Herring interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 423*724ba675SRob Herring <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 424*724ba675SRob Herring #iommu-cells = <1>; 425*724ba675SRob Herring status = "disabled"; 426*724ba675SRob Herring }; 427*724ba675SRob Herring 428*724ba675SRob Herring ipmmu_sy1: iommu@e6290000 { 429*724ba675SRob Herring compatible = "renesas,ipmmu-r8a7742", 430*724ba675SRob Herring "renesas,ipmmu-vmsa"; 431*724ba675SRob Herring reg = <0 0xe6290000 0 0x1000>; 432*724ba675SRob Herring interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 433*724ba675SRob Herring #iommu-cells = <1>; 434*724ba675SRob Herring status = "disabled"; 435*724ba675SRob Herring }; 436*724ba675SRob Herring 437*724ba675SRob Herring ipmmu_ds: iommu@e6740000 { 438*724ba675SRob Herring compatible = "renesas,ipmmu-r8a7742", 439*724ba675SRob Herring "renesas,ipmmu-vmsa"; 440*724ba675SRob Herring reg = <0 0xe6740000 0 0x1000>; 441*724ba675SRob Herring interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 442*724ba675SRob Herring <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 443*724ba675SRob Herring #iommu-cells = <1>; 444*724ba675SRob Herring status = "disabled"; 445*724ba675SRob Herring }; 446*724ba675SRob Herring 447*724ba675SRob Herring ipmmu_mp: iommu@ec680000 { 448*724ba675SRob Herring compatible = "renesas,ipmmu-r8a7742", 449*724ba675SRob Herring "renesas,ipmmu-vmsa"; 450*724ba675SRob Herring reg = <0 0xec680000 0 0x1000>; 451*724ba675SRob Herring interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 452*724ba675SRob Herring #iommu-cells = <1>; 453*724ba675SRob Herring status = "disabled"; 454*724ba675SRob Herring }; 455*724ba675SRob Herring 456*724ba675SRob Herring ipmmu_mx: iommu@fe951000 { 457*724ba675SRob Herring compatible = "renesas,ipmmu-r8a7742", 458*724ba675SRob Herring "renesas,ipmmu-vmsa"; 459*724ba675SRob Herring reg = <0 0xfe951000 0 0x1000>; 460*724ba675SRob Herring interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 461*724ba675SRob Herring <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 462*724ba675SRob Herring #iommu-cells = <1>; 463*724ba675SRob Herring status = "disabled"; 464*724ba675SRob Herring }; 465*724ba675SRob Herring 466*724ba675SRob Herring icram0: sram@e63a0000 { 467*724ba675SRob Herring compatible = "mmio-sram"; 468*724ba675SRob Herring reg = <0 0xe63a0000 0 0x12000>; 469*724ba675SRob Herring #address-cells = <1>; 470*724ba675SRob Herring #size-cells = <1>; 471*724ba675SRob Herring ranges = <0 0 0xe63a0000 0x12000>; 472*724ba675SRob Herring }; 473*724ba675SRob Herring 474*724ba675SRob Herring icram1: sram@e63c0000 { 475*724ba675SRob Herring compatible = "mmio-sram"; 476*724ba675SRob Herring reg = <0 0xe63c0000 0 0x1000>; 477*724ba675SRob Herring #address-cells = <1>; 478*724ba675SRob Herring #size-cells = <1>; 479*724ba675SRob Herring ranges = <0 0 0xe63c0000 0x1000>; 480*724ba675SRob Herring 481*724ba675SRob Herring smp-sram@0 { 482*724ba675SRob Herring compatible = "renesas,smp-sram"; 483*724ba675SRob Herring reg = <0 0x100>; 484*724ba675SRob Herring }; 485*724ba675SRob Herring }; 486*724ba675SRob Herring 487*724ba675SRob Herring icram2: sram@e6300000 { 488*724ba675SRob Herring compatible = "mmio-sram"; 489*724ba675SRob Herring reg = <0 0xe6300000 0 0x40000>; 490*724ba675SRob Herring #address-cells = <1>; 491*724ba675SRob Herring #size-cells = <1>; 492*724ba675SRob Herring ranges = <0 0 0xe6300000 0x40000>; 493*724ba675SRob Herring }; 494*724ba675SRob Herring 495*724ba675SRob Herring i2c0: i2c@e6508000 { 496*724ba675SRob Herring #address-cells = <1>; 497*724ba675SRob Herring #size-cells = <0>; 498*724ba675SRob Herring compatible = "renesas,i2c-r8a7742", 499*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 500*724ba675SRob Herring reg = <0 0xe6508000 0 0x40>; 501*724ba675SRob Herring interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 502*724ba675SRob Herring clocks = <&cpg CPG_MOD 931>; 503*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 504*724ba675SRob Herring resets = <&cpg 931>; 505*724ba675SRob Herring i2c-scl-internal-delay-ns = <110>; 506*724ba675SRob Herring status = "disabled"; 507*724ba675SRob Herring }; 508*724ba675SRob Herring 509*724ba675SRob Herring i2c1: i2c@e6518000 { 510*724ba675SRob Herring #address-cells = <1>; 511*724ba675SRob Herring #size-cells = <0>; 512*724ba675SRob Herring compatible = "renesas,i2c-r8a7742", 513*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 514*724ba675SRob Herring reg = <0 0xe6518000 0 0x40>; 515*724ba675SRob Herring interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 516*724ba675SRob Herring clocks = <&cpg CPG_MOD 930>; 517*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 518*724ba675SRob Herring resets = <&cpg 930>; 519*724ba675SRob Herring i2c-scl-internal-delay-ns = <6>; 520*724ba675SRob Herring status = "disabled"; 521*724ba675SRob Herring }; 522*724ba675SRob Herring 523*724ba675SRob Herring i2c2: i2c@e6530000 { 524*724ba675SRob Herring #address-cells = <1>; 525*724ba675SRob Herring #size-cells = <0>; 526*724ba675SRob Herring compatible = "renesas,i2c-r8a7742", 527*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 528*724ba675SRob Herring reg = <0 0xe6530000 0 0x40>; 529*724ba675SRob Herring interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 530*724ba675SRob Herring clocks = <&cpg CPG_MOD 929>; 531*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 532*724ba675SRob Herring resets = <&cpg 929>; 533*724ba675SRob Herring i2c-scl-internal-delay-ns = <6>; 534*724ba675SRob Herring status = "disabled"; 535*724ba675SRob Herring }; 536*724ba675SRob Herring 537*724ba675SRob Herring i2c3: i2c@e6540000 { 538*724ba675SRob Herring #address-cells = <1>; 539*724ba675SRob Herring #size-cells = <0>; 540*724ba675SRob Herring compatible = "renesas,i2c-r8a7742", 541*724ba675SRob Herring "renesas,rcar-gen2-i2c"; 542*724ba675SRob Herring reg = <0 0xe6540000 0 0x40>; 543*724ba675SRob Herring interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 544*724ba675SRob Herring clocks = <&cpg CPG_MOD 928>; 545*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 546*724ba675SRob Herring resets = <&cpg 928>; 547*724ba675SRob Herring i2c-scl-internal-delay-ns = <110>; 548*724ba675SRob Herring status = "disabled"; 549*724ba675SRob Herring }; 550*724ba675SRob Herring 551*724ba675SRob Herring iic0: i2c@e6500000 { 552*724ba675SRob Herring #address-cells = <1>; 553*724ba675SRob Herring #size-cells = <0>; 554*724ba675SRob Herring compatible = "renesas,iic-r8a7742", 555*724ba675SRob Herring "renesas,rcar-gen2-iic", 556*724ba675SRob Herring "renesas,rmobile-iic"; 557*724ba675SRob Herring reg = <0 0xe6500000 0 0x425>; 558*724ba675SRob Herring interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 559*724ba675SRob Herring clocks = <&cpg CPG_MOD 318>; 560*724ba675SRob Herring dmas = <&dmac0 0x61>, <&dmac0 0x62>, 561*724ba675SRob Herring <&dmac1 0x61>, <&dmac1 0x62>; 562*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 563*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 564*724ba675SRob Herring resets = <&cpg 318>; 565*724ba675SRob Herring status = "disabled"; 566*724ba675SRob Herring }; 567*724ba675SRob Herring 568*724ba675SRob Herring iic1: i2c@e6510000 { 569*724ba675SRob Herring #address-cells = <1>; 570*724ba675SRob Herring #size-cells = <0>; 571*724ba675SRob Herring compatible = "renesas,iic-r8a7742", 572*724ba675SRob Herring "renesas,rcar-gen2-iic", 573*724ba675SRob Herring "renesas,rmobile-iic"; 574*724ba675SRob Herring reg = <0 0xe6510000 0 0x425>; 575*724ba675SRob Herring interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 576*724ba675SRob Herring clocks = <&cpg CPG_MOD 323>; 577*724ba675SRob Herring dmas = <&dmac0 0x65>, <&dmac0 0x66>, 578*724ba675SRob Herring <&dmac1 0x65>, <&dmac1 0x66>; 579*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 580*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 581*724ba675SRob Herring resets = <&cpg 323>; 582*724ba675SRob Herring status = "disabled"; 583*724ba675SRob Herring }; 584*724ba675SRob Herring 585*724ba675SRob Herring iic2: i2c@e6520000 { 586*724ba675SRob Herring #address-cells = <1>; 587*724ba675SRob Herring #size-cells = <0>; 588*724ba675SRob Herring compatible = "renesas,iic-r8a7742", 589*724ba675SRob Herring "renesas,rcar-gen2-iic", 590*724ba675SRob Herring "renesas,rmobile-iic"; 591*724ba675SRob Herring reg = <0 0xe6520000 0 0x425>; 592*724ba675SRob Herring interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 593*724ba675SRob Herring clocks = <&cpg CPG_MOD 300>; 594*724ba675SRob Herring dmas = <&dmac0 0x69>, <&dmac0 0x6a>, 595*724ba675SRob Herring <&dmac1 0x69>, <&dmac1 0x6a>; 596*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 597*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 598*724ba675SRob Herring resets = <&cpg 300>; 599*724ba675SRob Herring status = "disabled"; 600*724ba675SRob Herring }; 601*724ba675SRob Herring 602*724ba675SRob Herring iic3: i2c@e60b0000 { 603*724ba675SRob Herring #address-cells = <1>; 604*724ba675SRob Herring #size-cells = <0>; 605*724ba675SRob Herring compatible = "renesas,iic-r8a7742", 606*724ba675SRob Herring "renesas,rcar-gen2-iic", 607*724ba675SRob Herring "renesas,rmobile-iic"; 608*724ba675SRob Herring reg = <0 0xe60b0000 0 0x425>; 609*724ba675SRob Herring interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 610*724ba675SRob Herring clocks = <&cpg CPG_MOD 926>; 611*724ba675SRob Herring dmas = <&dmac0 0x77>, <&dmac0 0x78>, 612*724ba675SRob Herring <&dmac1 0x77>, <&dmac1 0x78>; 613*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 614*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 615*724ba675SRob Herring resets = <&cpg 926>; 616*724ba675SRob Herring status = "disabled"; 617*724ba675SRob Herring }; 618*724ba675SRob Herring 619*724ba675SRob Herring hsusb: usb@e6590000 { 620*724ba675SRob Herring compatible = "renesas,usbhs-r8a7742", 621*724ba675SRob Herring "renesas,rcar-gen2-usbhs"; 622*724ba675SRob Herring reg = <0 0xe6590000 0 0x100>; 623*724ba675SRob Herring interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 624*724ba675SRob Herring clocks = <&cpg CPG_MOD 704>; 625*724ba675SRob Herring dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 626*724ba675SRob Herring <&usb_dmac1 0>, <&usb_dmac1 1>; 627*724ba675SRob Herring dma-names = "ch0", "ch1", "ch2", "ch3"; 628*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 629*724ba675SRob Herring resets = <&cpg 704>; 630*724ba675SRob Herring renesas,buswait = <4>; 631*724ba675SRob Herring phys = <&usb0 1>; 632*724ba675SRob Herring phy-names = "usb"; 633*724ba675SRob Herring status = "disabled"; 634*724ba675SRob Herring }; 635*724ba675SRob Herring 636*724ba675SRob Herring usbphy: usb-phy-controller@e6590100 { 637*724ba675SRob Herring compatible = "renesas,usb-phy-r8a7742", 638*724ba675SRob Herring "renesas,rcar-gen2-usb-phy"; 639*724ba675SRob Herring reg = <0 0xe6590100 0 0x100>; 640*724ba675SRob Herring #address-cells = <1>; 641*724ba675SRob Herring #size-cells = <0>; 642*724ba675SRob Herring clocks = <&cpg CPG_MOD 704>; 643*724ba675SRob Herring clock-names = "usbhs"; 644*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 645*724ba675SRob Herring resets = <&cpg 704>; 646*724ba675SRob Herring status = "disabled"; 647*724ba675SRob Herring 648*724ba675SRob Herring usb0: usb-phy@0 { 649*724ba675SRob Herring reg = <0>; 650*724ba675SRob Herring #phy-cells = <1>; 651*724ba675SRob Herring }; 652*724ba675SRob Herring usb2: usb-phy@2 { 653*724ba675SRob Herring reg = <2>; 654*724ba675SRob Herring #phy-cells = <1>; 655*724ba675SRob Herring }; 656*724ba675SRob Herring }; 657*724ba675SRob Herring 658*724ba675SRob Herring usb_dmac0: dma-controller@e65a0000 { 659*724ba675SRob Herring compatible = "renesas,r8a7742-usb-dmac", 660*724ba675SRob Herring "renesas,usb-dmac"; 661*724ba675SRob Herring reg = <0 0xe65a0000 0 0x100>; 662*724ba675SRob Herring interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 663*724ba675SRob Herring <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 664*724ba675SRob Herring interrupt-names = "ch0", "ch1"; 665*724ba675SRob Herring clocks = <&cpg CPG_MOD 330>; 666*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 667*724ba675SRob Herring resets = <&cpg 330>; 668*724ba675SRob Herring #dma-cells = <1>; 669*724ba675SRob Herring dma-channels = <2>; 670*724ba675SRob Herring }; 671*724ba675SRob Herring 672*724ba675SRob Herring usb_dmac1: dma-controller@e65b0000 { 673*724ba675SRob Herring compatible = "renesas,r8a7742-usb-dmac", 674*724ba675SRob Herring "renesas,usb-dmac"; 675*724ba675SRob Herring reg = <0 0xe65b0000 0 0x100>; 676*724ba675SRob Herring interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 677*724ba675SRob Herring <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 678*724ba675SRob Herring interrupt-names = "ch0", "ch1"; 679*724ba675SRob Herring clocks = <&cpg CPG_MOD 331>; 680*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 681*724ba675SRob Herring resets = <&cpg 331>; 682*724ba675SRob Herring #dma-cells = <1>; 683*724ba675SRob Herring dma-channels = <2>; 684*724ba675SRob Herring }; 685*724ba675SRob Herring 686*724ba675SRob Herring dmac0: dma-controller@e6700000 { 687*724ba675SRob Herring compatible = "renesas,dmac-r8a7742", 688*724ba675SRob Herring "renesas,rcar-dmac"; 689*724ba675SRob Herring reg = <0 0xe6700000 0 0x20000>; 690*724ba675SRob Herring interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 691*724ba675SRob Herring <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 692*724ba675SRob Herring <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 693*724ba675SRob Herring <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 694*724ba675SRob Herring <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 695*724ba675SRob Herring <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 696*724ba675SRob Herring <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 697*724ba675SRob Herring <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 698*724ba675SRob Herring <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 699*724ba675SRob Herring <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 700*724ba675SRob Herring <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 701*724ba675SRob Herring <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 702*724ba675SRob Herring <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 703*724ba675SRob Herring <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 704*724ba675SRob Herring <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 705*724ba675SRob Herring <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 706*724ba675SRob Herring interrupt-names = "error", 707*724ba675SRob Herring "ch0", "ch1", "ch2", "ch3", 708*724ba675SRob Herring "ch4", "ch5", "ch6", "ch7", 709*724ba675SRob Herring "ch8", "ch9", "ch10", "ch11", 710*724ba675SRob Herring "ch12", "ch13", "ch14"; 711*724ba675SRob Herring clocks = <&cpg CPG_MOD 219>; 712*724ba675SRob Herring clock-names = "fck"; 713*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 714*724ba675SRob Herring resets = <&cpg 219>; 715*724ba675SRob Herring #dma-cells = <1>; 716*724ba675SRob Herring dma-channels = <15>; 717*724ba675SRob Herring }; 718*724ba675SRob Herring 719*724ba675SRob Herring dmac1: dma-controller@e6720000 { 720*724ba675SRob Herring compatible = "renesas,dmac-r8a7742", 721*724ba675SRob Herring "renesas,rcar-dmac"; 722*724ba675SRob Herring reg = <0 0xe6720000 0 0x20000>; 723*724ba675SRob Herring interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 724*724ba675SRob Herring <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 725*724ba675SRob Herring <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 726*724ba675SRob Herring <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 727*724ba675SRob Herring <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 728*724ba675SRob Herring <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 729*724ba675SRob Herring <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 730*724ba675SRob Herring <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 731*724ba675SRob Herring <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 732*724ba675SRob Herring <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 733*724ba675SRob Herring <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 734*724ba675SRob Herring <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 735*724ba675SRob Herring <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 736*724ba675SRob Herring <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 737*724ba675SRob Herring <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 738*724ba675SRob Herring <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 739*724ba675SRob Herring interrupt-names = "error", 740*724ba675SRob Herring "ch0", "ch1", "ch2", "ch3", 741*724ba675SRob Herring "ch4", "ch5", "ch6", "ch7", 742*724ba675SRob Herring "ch8", "ch9", "ch10", "ch11", 743*724ba675SRob Herring "ch12", "ch13", "ch14"; 744*724ba675SRob Herring clocks = <&cpg CPG_MOD 218>; 745*724ba675SRob Herring clock-names = "fck"; 746*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 747*724ba675SRob Herring resets = <&cpg 218>; 748*724ba675SRob Herring #dma-cells = <1>; 749*724ba675SRob Herring dma-channels = <15>; 750*724ba675SRob Herring }; 751*724ba675SRob Herring 752*724ba675SRob Herring avb: ethernet@e6800000 { 753*724ba675SRob Herring compatible = "renesas,etheravb-r8a7742", 754*724ba675SRob Herring "renesas,etheravb-rcar-gen2"; 755*724ba675SRob Herring reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 756*724ba675SRob Herring interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 757*724ba675SRob Herring clocks = <&cpg CPG_MOD 812>; 758*724ba675SRob Herring clock-names = "fck"; 759*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 760*724ba675SRob Herring resets = <&cpg 812>; 761*724ba675SRob Herring #address-cells = <1>; 762*724ba675SRob Herring #size-cells = <0>; 763*724ba675SRob Herring status = "disabled"; 764*724ba675SRob Herring }; 765*724ba675SRob Herring 766*724ba675SRob Herring qspi: spi@e6b10000 { 767*724ba675SRob Herring compatible = "renesas,qspi-r8a7742", "renesas,qspi"; 768*724ba675SRob Herring reg = <0 0xe6b10000 0 0x2c>; 769*724ba675SRob Herring interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 770*724ba675SRob Herring clocks = <&cpg CPG_MOD 917>; 771*724ba675SRob Herring dmas = <&dmac0 0x17>, <&dmac0 0x18>, 772*724ba675SRob Herring <&dmac1 0x17>, <&dmac1 0x18>; 773*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 774*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 775*724ba675SRob Herring resets = <&cpg 917>; 776*724ba675SRob Herring num-cs = <1>; 777*724ba675SRob Herring #address-cells = <1>; 778*724ba675SRob Herring #size-cells = <0>; 779*724ba675SRob Herring status = "disabled"; 780*724ba675SRob Herring }; 781*724ba675SRob Herring 782*724ba675SRob Herring scifa0: serial@e6c40000 { 783*724ba675SRob Herring compatible = "renesas,scifa-r8a7742", 784*724ba675SRob Herring "renesas,rcar-gen2-scifa", "renesas,scifa"; 785*724ba675SRob Herring reg = <0 0xe6c40000 0 0x40>; 786*724ba675SRob Herring interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 787*724ba675SRob Herring clocks = <&cpg CPG_MOD 204>; 788*724ba675SRob Herring clock-names = "fck"; 789*724ba675SRob Herring dmas = <&dmac0 0x21>, <&dmac0 0x22>, 790*724ba675SRob Herring <&dmac1 0x21>, <&dmac1 0x22>; 791*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 792*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 793*724ba675SRob Herring resets = <&cpg 204>; 794*724ba675SRob Herring status = "disabled"; 795*724ba675SRob Herring }; 796*724ba675SRob Herring 797*724ba675SRob Herring scifa1: serial@e6c50000 { 798*724ba675SRob Herring compatible = "renesas,scifa-r8a7742", 799*724ba675SRob Herring "renesas,rcar-gen2-scifa", "renesas,scifa"; 800*724ba675SRob Herring reg = <0 0xe6c50000 0 0x40>; 801*724ba675SRob Herring interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 802*724ba675SRob Herring clocks = <&cpg CPG_MOD 203>; 803*724ba675SRob Herring clock-names = "fck"; 804*724ba675SRob Herring dmas = <&dmac0 0x25>, <&dmac0 0x26>, 805*724ba675SRob Herring <&dmac1 0x25>, <&dmac1 0x26>; 806*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 807*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 808*724ba675SRob Herring resets = <&cpg 203>; 809*724ba675SRob Herring status = "disabled"; 810*724ba675SRob Herring }; 811*724ba675SRob Herring 812*724ba675SRob Herring scifa2: serial@e6c60000 { 813*724ba675SRob Herring compatible = "renesas,scifa-r8a7742", 814*724ba675SRob Herring "renesas,rcar-gen2-scifa", "renesas,scifa"; 815*724ba675SRob Herring reg = <0 0xe6c60000 0 0x40>; 816*724ba675SRob Herring interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 817*724ba675SRob Herring clocks = <&cpg CPG_MOD 202>; 818*724ba675SRob Herring clock-names = "fck"; 819*724ba675SRob Herring dmas = <&dmac0 0x27>, <&dmac0 0x28>, 820*724ba675SRob Herring <&dmac1 0x27>, <&dmac1 0x28>; 821*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 822*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 823*724ba675SRob Herring resets = <&cpg 202>; 824*724ba675SRob Herring status = "disabled"; 825*724ba675SRob Herring }; 826*724ba675SRob Herring 827*724ba675SRob Herring scifb0: serial@e6c20000 { 828*724ba675SRob Herring compatible = "renesas,scifb-r8a7742", 829*724ba675SRob Herring "renesas,rcar-gen2-scifb", "renesas,scifb"; 830*724ba675SRob Herring reg = <0 0xe6c20000 0 0x100>; 831*724ba675SRob Herring interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 832*724ba675SRob Herring clocks = <&cpg CPG_MOD 206>; 833*724ba675SRob Herring clock-names = "fck"; 834*724ba675SRob Herring dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, 835*724ba675SRob Herring <&dmac1 0x3d>, <&dmac1 0x3e>; 836*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 837*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 838*724ba675SRob Herring resets = <&cpg 206>; 839*724ba675SRob Herring status = "disabled"; 840*724ba675SRob Herring }; 841*724ba675SRob Herring 842*724ba675SRob Herring scifb1: serial@e6c30000 { 843*724ba675SRob Herring compatible = "renesas,scifb-r8a7742", 844*724ba675SRob Herring "renesas,rcar-gen2-scifb", "renesas,scifb"; 845*724ba675SRob Herring reg = <0 0xe6c30000 0 0x100>; 846*724ba675SRob Herring interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 847*724ba675SRob Herring clocks = <&cpg CPG_MOD 207>; 848*724ba675SRob Herring clock-names = "fck"; 849*724ba675SRob Herring dmas = <&dmac0 0x19>, <&dmac0 0x1a>, 850*724ba675SRob Herring <&dmac1 0x19>, <&dmac1 0x1a>; 851*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 852*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 853*724ba675SRob Herring resets = <&cpg 207>; 854*724ba675SRob Herring status = "disabled"; 855*724ba675SRob Herring }; 856*724ba675SRob Herring 857*724ba675SRob Herring scifb2: serial@e6ce0000 { 858*724ba675SRob Herring compatible = "renesas,scifb-r8a7742", 859*724ba675SRob Herring "renesas,rcar-gen2-scifb", "renesas,scifb"; 860*724ba675SRob Herring reg = <0 0xe6ce0000 0 0x100>; 861*724ba675SRob Herring interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 862*724ba675SRob Herring clocks = <&cpg CPG_MOD 216>; 863*724ba675SRob Herring clock-names = "fck"; 864*724ba675SRob Herring dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, 865*724ba675SRob Herring <&dmac1 0x1d>, <&dmac1 0x1e>; 866*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 867*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 868*724ba675SRob Herring resets = <&cpg 216>; 869*724ba675SRob Herring status = "disabled"; 870*724ba675SRob Herring }; 871*724ba675SRob Herring 872*724ba675SRob Herring scif0: serial@e6e60000 { 873*724ba675SRob Herring compatible = "renesas,scif-r8a7742", 874*724ba675SRob Herring "renesas,rcar-gen2-scif", "renesas,scif"; 875*724ba675SRob Herring reg = <0 0xe6e60000 0 0x40>; 876*724ba675SRob Herring interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 877*724ba675SRob Herring clocks = <&cpg CPG_MOD 721>, 878*724ba675SRob Herring <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; 879*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 880*724ba675SRob Herring dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 881*724ba675SRob Herring <&dmac1 0x29>, <&dmac1 0x2a>; 882*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 883*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 884*724ba675SRob Herring resets = <&cpg 721>; 885*724ba675SRob Herring status = "disabled"; 886*724ba675SRob Herring }; 887*724ba675SRob Herring 888*724ba675SRob Herring scif1: serial@e6e68000 { 889*724ba675SRob Herring compatible = "renesas,scif-r8a7742", 890*724ba675SRob Herring "renesas,rcar-gen2-scif", "renesas,scif"; 891*724ba675SRob Herring reg = <0 0xe6e68000 0 0x40>; 892*724ba675SRob Herring interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 893*724ba675SRob Herring clocks = <&cpg CPG_MOD 720>, 894*724ba675SRob Herring <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; 895*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 896*724ba675SRob Herring dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 897*724ba675SRob Herring <&dmac1 0x2d>, <&dmac1 0x2e>; 898*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 899*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 900*724ba675SRob Herring resets = <&cpg 720>; 901*724ba675SRob Herring status = "disabled"; 902*724ba675SRob Herring }; 903*724ba675SRob Herring 904*724ba675SRob Herring scif2: serial@e6e56000 { 905*724ba675SRob Herring compatible = "renesas,scif-r8a7742", 906*724ba675SRob Herring "renesas,rcar-gen2-scif", "renesas,scif"; 907*724ba675SRob Herring reg = <0 0xe6e56000 0 0x40>; 908*724ba675SRob Herring interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 909*724ba675SRob Herring clocks = <&cpg CPG_MOD 310>, 910*724ba675SRob Herring <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; 911*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 912*724ba675SRob Herring dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 913*724ba675SRob Herring <&dmac1 0x2b>, <&dmac1 0x2c>; 914*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 915*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 916*724ba675SRob Herring resets = <&cpg 310>; 917*724ba675SRob Herring status = "disabled"; 918*724ba675SRob Herring }; 919*724ba675SRob Herring 920*724ba675SRob Herring hscif0: serial@e62c0000 { 921*724ba675SRob Herring compatible = "renesas,hscif-r8a7742", 922*724ba675SRob Herring "renesas,rcar-gen2-hscif", "renesas,hscif"; 923*724ba675SRob Herring reg = <0 0xe62c0000 0 0x60>; 924*724ba675SRob Herring interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 925*724ba675SRob Herring clocks = <&cpg CPG_MOD 717>, 926*724ba675SRob Herring <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; 927*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 928*724ba675SRob Herring dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 929*724ba675SRob Herring <&dmac1 0x39>, <&dmac1 0x3a>; 930*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 931*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 932*724ba675SRob Herring resets = <&cpg 717>; 933*724ba675SRob Herring status = "disabled"; 934*724ba675SRob Herring }; 935*724ba675SRob Herring 936*724ba675SRob Herring hscif1: serial@e62c8000 { 937*724ba675SRob Herring compatible = "renesas,hscif-r8a7742", 938*724ba675SRob Herring "renesas,rcar-gen2-hscif", "renesas,hscif"; 939*724ba675SRob Herring reg = <0 0xe62c8000 0 0x60>; 940*724ba675SRob Herring interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 941*724ba675SRob Herring clocks = <&cpg CPG_MOD 716>, 942*724ba675SRob Herring <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; 943*724ba675SRob Herring clock-names = "fck", "brg_int", "scif_clk"; 944*724ba675SRob Herring dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 945*724ba675SRob Herring <&dmac1 0x4d>, <&dmac1 0x4e>; 946*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 947*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 948*724ba675SRob Herring resets = <&cpg 716>; 949*724ba675SRob Herring status = "disabled"; 950*724ba675SRob Herring }; 951*724ba675SRob Herring 952*724ba675SRob Herring msiof0: spi@e6e20000 { 953*724ba675SRob Herring compatible = "renesas,msiof-r8a7742", 954*724ba675SRob Herring "renesas,rcar-gen2-msiof"; 955*724ba675SRob Herring reg = <0 0xe6e20000 0 0x0064>; 956*724ba675SRob Herring interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 957*724ba675SRob Herring clocks = <&cpg CPG_MOD 0>; 958*724ba675SRob Herring dmas = <&dmac0 0x51>, <&dmac0 0x52>, 959*724ba675SRob Herring <&dmac1 0x51>, <&dmac1 0x52>; 960*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 961*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 962*724ba675SRob Herring resets = <&cpg 0>; 963*724ba675SRob Herring #address-cells = <1>; 964*724ba675SRob Herring #size-cells = <0>; 965*724ba675SRob Herring status = "disabled"; 966*724ba675SRob Herring }; 967*724ba675SRob Herring 968*724ba675SRob Herring msiof1: spi@e6e10000 { 969*724ba675SRob Herring compatible = "renesas,msiof-r8a7742", 970*724ba675SRob Herring "renesas,rcar-gen2-msiof"; 971*724ba675SRob Herring reg = <0 0xe6e10000 0 0x0064>; 972*724ba675SRob Herring interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 973*724ba675SRob Herring clocks = <&cpg CPG_MOD 208>; 974*724ba675SRob Herring dmas = <&dmac0 0x55>, <&dmac0 0x56>, 975*724ba675SRob Herring <&dmac1 0x55>, <&dmac1 0x56>; 976*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 977*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 978*724ba675SRob Herring resets = <&cpg 208>; 979*724ba675SRob Herring #address-cells = <1>; 980*724ba675SRob Herring #size-cells = <0>; 981*724ba675SRob Herring status = "disabled"; 982*724ba675SRob Herring }; 983*724ba675SRob Herring 984*724ba675SRob Herring msiof2: spi@e6e00000 { 985*724ba675SRob Herring compatible = "renesas,msiof-r8a7742", 986*724ba675SRob Herring "renesas,rcar-gen2-msiof"; 987*724ba675SRob Herring reg = <0 0xe6e00000 0 0x0064>; 988*724ba675SRob Herring interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 989*724ba675SRob Herring clocks = <&cpg CPG_MOD 205>; 990*724ba675SRob Herring dmas = <&dmac0 0x41>, <&dmac0 0x42>, 991*724ba675SRob Herring <&dmac1 0x41>, <&dmac1 0x42>; 992*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 993*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 994*724ba675SRob Herring resets = <&cpg 205>; 995*724ba675SRob Herring #address-cells = <1>; 996*724ba675SRob Herring #size-cells = <0>; 997*724ba675SRob Herring status = "disabled"; 998*724ba675SRob Herring }; 999*724ba675SRob Herring 1000*724ba675SRob Herring msiof3: spi@e6c90000 { 1001*724ba675SRob Herring compatible = "renesas,msiof-r8a7742", 1002*724ba675SRob Herring "renesas,rcar-gen2-msiof"; 1003*724ba675SRob Herring reg = <0 0xe6c90000 0 0x0064>; 1004*724ba675SRob Herring interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1005*724ba675SRob Herring clocks = <&cpg CPG_MOD 215>; 1006*724ba675SRob Herring dmas = <&dmac0 0x45>, <&dmac0 0x46>, 1007*724ba675SRob Herring <&dmac1 0x45>, <&dmac1 0x46>; 1008*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 1009*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1010*724ba675SRob Herring resets = <&cpg 215>; 1011*724ba675SRob Herring #address-cells = <1>; 1012*724ba675SRob Herring #size-cells = <0>; 1013*724ba675SRob Herring status = "disabled"; 1014*724ba675SRob Herring }; 1015*724ba675SRob Herring 1016*724ba675SRob Herring can0: can@e6e80000 { 1017*724ba675SRob Herring compatible = "renesas,can-r8a7742", 1018*724ba675SRob Herring "renesas,rcar-gen2-can"; 1019*724ba675SRob Herring reg = <0 0xe6e80000 0 0x1000>; 1020*724ba675SRob Herring interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1021*724ba675SRob Herring clocks = <&cpg CPG_MOD 916>, 1022*724ba675SRob Herring <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>; 1023*724ba675SRob Herring clock-names = "clkp1", "clkp2", "can_clk"; 1024*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1025*724ba675SRob Herring resets = <&cpg 916>; 1026*724ba675SRob Herring status = "disabled"; 1027*724ba675SRob Herring }; 1028*724ba675SRob Herring 1029*724ba675SRob Herring can1: can@e6e88000 { 1030*724ba675SRob Herring compatible = "renesas,can-r8a7742", 1031*724ba675SRob Herring "renesas,rcar-gen2-can"; 1032*724ba675SRob Herring reg = <0 0xe6e88000 0 0x1000>; 1033*724ba675SRob Herring interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1034*724ba675SRob Herring clocks = <&cpg CPG_MOD 915>, 1035*724ba675SRob Herring <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>; 1036*724ba675SRob Herring clock-names = "clkp1", "clkp2", "can_clk"; 1037*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1038*724ba675SRob Herring resets = <&cpg 915>; 1039*724ba675SRob Herring status = "disabled"; 1040*724ba675SRob Herring }; 1041*724ba675SRob Herring 1042*724ba675SRob Herring pwm0: pwm@e6e30000 { 1043*724ba675SRob Herring compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; 1044*724ba675SRob Herring reg = <0 0xe6e30000 0 0x8>; 1045*724ba675SRob Herring clocks = <&cpg CPG_MOD 523>; 1046*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1047*724ba675SRob Herring resets = <&cpg 523>; 1048*724ba675SRob Herring #pwm-cells = <2>; 1049*724ba675SRob Herring status = "disabled"; 1050*724ba675SRob Herring }; 1051*724ba675SRob Herring 1052*724ba675SRob Herring pwm1: pwm@e6e31000 { 1053*724ba675SRob Herring compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; 1054*724ba675SRob Herring reg = <0 0xe6e31000 0 0x8>; 1055*724ba675SRob Herring clocks = <&cpg CPG_MOD 523>; 1056*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1057*724ba675SRob Herring resets = <&cpg 523>; 1058*724ba675SRob Herring #pwm-cells = <2>; 1059*724ba675SRob Herring status = "disabled"; 1060*724ba675SRob Herring }; 1061*724ba675SRob Herring 1062*724ba675SRob Herring pwm2: pwm@e6e32000 { 1063*724ba675SRob Herring compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; 1064*724ba675SRob Herring reg = <0 0xe6e32000 0 0x8>; 1065*724ba675SRob Herring clocks = <&cpg CPG_MOD 523>; 1066*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1067*724ba675SRob Herring resets = <&cpg 523>; 1068*724ba675SRob Herring #pwm-cells = <2>; 1069*724ba675SRob Herring status = "disabled"; 1070*724ba675SRob Herring }; 1071*724ba675SRob Herring 1072*724ba675SRob Herring pwm3: pwm@e6e33000 { 1073*724ba675SRob Herring compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; 1074*724ba675SRob Herring reg = <0 0xe6e33000 0 0x8>; 1075*724ba675SRob Herring clocks = <&cpg CPG_MOD 523>; 1076*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1077*724ba675SRob Herring resets = <&cpg 523>; 1078*724ba675SRob Herring #pwm-cells = <2>; 1079*724ba675SRob Herring status = "disabled"; 1080*724ba675SRob Herring }; 1081*724ba675SRob Herring 1082*724ba675SRob Herring pwm4: pwm@e6e34000 { 1083*724ba675SRob Herring compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; 1084*724ba675SRob Herring reg = <0 0xe6e34000 0 0x8>; 1085*724ba675SRob Herring clocks = <&cpg CPG_MOD 523>; 1086*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1087*724ba675SRob Herring resets = <&cpg 523>; 1088*724ba675SRob Herring #pwm-cells = <2>; 1089*724ba675SRob Herring status = "disabled"; 1090*724ba675SRob Herring }; 1091*724ba675SRob Herring 1092*724ba675SRob Herring pwm5: pwm@e6e35000 { 1093*724ba675SRob Herring compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; 1094*724ba675SRob Herring reg = <0 0xe6e35000 0 0x8>; 1095*724ba675SRob Herring clocks = <&cpg CPG_MOD 523>; 1096*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1097*724ba675SRob Herring resets = <&cpg 523>; 1098*724ba675SRob Herring #pwm-cells = <2>; 1099*724ba675SRob Herring status = "disabled"; 1100*724ba675SRob Herring }; 1101*724ba675SRob Herring 1102*724ba675SRob Herring pwm6: pwm@e6e36000 { 1103*724ba675SRob Herring compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; 1104*724ba675SRob Herring reg = <0 0xe6e36000 0 0x8>; 1105*724ba675SRob Herring clocks = <&cpg CPG_MOD 523>; 1106*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1107*724ba675SRob Herring resets = <&cpg 523>; 1108*724ba675SRob Herring #pwm-cells = <2>; 1109*724ba675SRob Herring status = "disabled"; 1110*724ba675SRob Herring }; 1111*724ba675SRob Herring 1112*724ba675SRob Herring vin0: video@e6ef0000 { 1113*724ba675SRob Herring compatible = "renesas,vin-r8a7742", 1114*724ba675SRob Herring "renesas,rcar-gen2-vin"; 1115*724ba675SRob Herring reg = <0 0xe6ef0000 0 0x1000>; 1116*724ba675SRob Herring interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1117*724ba675SRob Herring clocks = <&cpg CPG_MOD 811>; 1118*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1119*724ba675SRob Herring resets = <&cpg 811>; 1120*724ba675SRob Herring status = "disabled"; 1121*724ba675SRob Herring }; 1122*724ba675SRob Herring 1123*724ba675SRob Herring vin1: video@e6ef1000 { 1124*724ba675SRob Herring compatible = "renesas,vin-r8a7742", 1125*724ba675SRob Herring "renesas,rcar-gen2-vin"; 1126*724ba675SRob Herring reg = <0 0xe6ef1000 0 0x1000>; 1127*724ba675SRob Herring interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1128*724ba675SRob Herring clocks = <&cpg CPG_MOD 810>; 1129*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1130*724ba675SRob Herring resets = <&cpg 810>; 1131*724ba675SRob Herring status = "disabled"; 1132*724ba675SRob Herring }; 1133*724ba675SRob Herring 1134*724ba675SRob Herring vin2: video@e6ef2000 { 1135*724ba675SRob Herring compatible = "renesas,vin-r8a7742", 1136*724ba675SRob Herring "renesas,rcar-gen2-vin"; 1137*724ba675SRob Herring reg = <0 0xe6ef2000 0 0x1000>; 1138*724ba675SRob Herring interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1139*724ba675SRob Herring clocks = <&cpg CPG_MOD 809>; 1140*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1141*724ba675SRob Herring resets = <&cpg 809>; 1142*724ba675SRob Herring status = "disabled"; 1143*724ba675SRob Herring }; 1144*724ba675SRob Herring 1145*724ba675SRob Herring vin3: video@e6ef3000 { 1146*724ba675SRob Herring compatible = "renesas,vin-r8a7742", 1147*724ba675SRob Herring "renesas,rcar-gen2-vin"; 1148*724ba675SRob Herring reg = <0 0xe6ef3000 0 0x1000>; 1149*724ba675SRob Herring interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1150*724ba675SRob Herring clocks = <&cpg CPG_MOD 808>; 1151*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1152*724ba675SRob Herring resets = <&cpg 808>; 1153*724ba675SRob Herring status = "disabled"; 1154*724ba675SRob Herring }; 1155*724ba675SRob Herring 1156*724ba675SRob Herring rcar_sound: sound@ec500000 { 1157*724ba675SRob Herring /* 1158*724ba675SRob Herring * #sound-dai-cells is required if simple-card 1159*724ba675SRob Herring * 1160*724ba675SRob Herring * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1161*724ba675SRob Herring * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1162*724ba675SRob Herring */ 1163*724ba675SRob Herring compatible = "renesas,rcar_sound-r8a7742", 1164*724ba675SRob Herring "renesas,rcar_sound-gen2"; 1165*724ba675SRob Herring reg = <0 0xec500000 0 0x1000>, /* SCU */ 1166*724ba675SRob Herring <0 0xec5a0000 0 0x100>, /* ADG */ 1167*724ba675SRob Herring <0 0xec540000 0 0x1000>, /* SSIU */ 1168*724ba675SRob Herring <0 0xec541000 0 0x280>, /* SSI */ 1169*724ba675SRob Herring <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1170*724ba675SRob Herring reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1171*724ba675SRob Herring 1172*724ba675SRob Herring clocks = <&cpg CPG_MOD 1005>, 1173*724ba675SRob Herring <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1174*724ba675SRob Herring <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1175*724ba675SRob Herring <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1176*724ba675SRob Herring <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1177*724ba675SRob Herring <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1178*724ba675SRob Herring <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1179*724ba675SRob Herring <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1180*724ba675SRob Herring <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1181*724ba675SRob Herring <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1182*724ba675SRob Herring <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1183*724ba675SRob Herring <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, 1184*724ba675SRob Herring <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, 1185*724ba675SRob Herring <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1186*724ba675SRob Herring <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, 1187*724ba675SRob Herring <&cpg CPG_CORE R8A7742_CLK_M2>; 1188*724ba675SRob Herring clock-names = "ssi-all", 1189*724ba675SRob Herring "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1190*724ba675SRob Herring "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1191*724ba675SRob Herring "ssi.1", "ssi.0", 1192*724ba675SRob Herring "src.9", "src.8", "src.7", "src.6", 1193*724ba675SRob Herring "src.5", "src.4", "src.3", "src.2", 1194*724ba675SRob Herring "src.1", "src.0", 1195*724ba675SRob Herring "ctu.0", "ctu.1", 1196*724ba675SRob Herring "mix.0", "mix.1", 1197*724ba675SRob Herring "dvc.0", "dvc.1", 1198*724ba675SRob Herring "clk_a", "clk_b", "clk_c", "clk_i"; 1199*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1200*724ba675SRob Herring resets = <&cpg 1005>, 1201*724ba675SRob Herring <&cpg 1006>, <&cpg 1007>, 1202*724ba675SRob Herring <&cpg 1008>, <&cpg 1009>, 1203*724ba675SRob Herring <&cpg 1010>, <&cpg 1011>, 1204*724ba675SRob Herring <&cpg 1012>, <&cpg 1013>, 1205*724ba675SRob Herring <&cpg 1014>, <&cpg 1015>; 1206*724ba675SRob Herring reset-names = "ssi-all", 1207*724ba675SRob Herring "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1208*724ba675SRob Herring "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1209*724ba675SRob Herring "ssi.1", "ssi.0"; 1210*724ba675SRob Herring 1211*724ba675SRob Herring status = "disabled"; 1212*724ba675SRob Herring 1213*724ba675SRob Herring rcar_sound,dvc { 1214*724ba675SRob Herring dvc0: dvc-0 { 1215*724ba675SRob Herring dmas = <&audma1 0xbc>; 1216*724ba675SRob Herring dma-names = "tx"; 1217*724ba675SRob Herring }; 1218*724ba675SRob Herring dvc1: dvc-1 { 1219*724ba675SRob Herring dmas = <&audma1 0xbe>; 1220*724ba675SRob Herring dma-names = "tx"; 1221*724ba675SRob Herring }; 1222*724ba675SRob Herring }; 1223*724ba675SRob Herring 1224*724ba675SRob Herring rcar_sound,mix { 1225*724ba675SRob Herring mix0: mix-0 { }; 1226*724ba675SRob Herring mix1: mix-1 { }; 1227*724ba675SRob Herring }; 1228*724ba675SRob Herring 1229*724ba675SRob Herring rcar_sound,ctu { 1230*724ba675SRob Herring ctu00: ctu-0 { }; 1231*724ba675SRob Herring ctu01: ctu-1 { }; 1232*724ba675SRob Herring ctu02: ctu-2 { }; 1233*724ba675SRob Herring ctu03: ctu-3 { }; 1234*724ba675SRob Herring ctu10: ctu-4 { }; 1235*724ba675SRob Herring ctu11: ctu-5 { }; 1236*724ba675SRob Herring ctu12: ctu-6 { }; 1237*724ba675SRob Herring ctu13: ctu-7 { }; 1238*724ba675SRob Herring }; 1239*724ba675SRob Herring 1240*724ba675SRob Herring rcar_sound,src { 1241*724ba675SRob Herring src0: src-0 { 1242*724ba675SRob Herring interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1243*724ba675SRob Herring dmas = <&audma0 0x85>, <&audma1 0x9a>; 1244*724ba675SRob Herring dma-names = "rx", "tx"; 1245*724ba675SRob Herring }; 1246*724ba675SRob Herring src1: src-1 { 1247*724ba675SRob Herring interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1248*724ba675SRob Herring dmas = <&audma0 0x87>, <&audma1 0x9c>; 1249*724ba675SRob Herring dma-names = "rx", "tx"; 1250*724ba675SRob Herring }; 1251*724ba675SRob Herring src2: src-2 { 1252*724ba675SRob Herring interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1253*724ba675SRob Herring dmas = <&audma0 0x89>, <&audma1 0x9e>; 1254*724ba675SRob Herring dma-names = "rx", "tx"; 1255*724ba675SRob Herring }; 1256*724ba675SRob Herring src3: src-3 { 1257*724ba675SRob Herring interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1258*724ba675SRob Herring dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1259*724ba675SRob Herring dma-names = "rx", "tx"; 1260*724ba675SRob Herring }; 1261*724ba675SRob Herring src4: src-4 { 1262*724ba675SRob Herring interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1263*724ba675SRob Herring dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1264*724ba675SRob Herring dma-names = "rx", "tx"; 1265*724ba675SRob Herring }; 1266*724ba675SRob Herring src5: src-5 { 1267*724ba675SRob Herring interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1268*724ba675SRob Herring dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1269*724ba675SRob Herring dma-names = "rx", "tx"; 1270*724ba675SRob Herring }; 1271*724ba675SRob Herring src6: src-6 { 1272*724ba675SRob Herring interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1273*724ba675SRob Herring dmas = <&audma0 0x91>, <&audma1 0xb4>; 1274*724ba675SRob Herring dma-names = "rx", "tx"; 1275*724ba675SRob Herring }; 1276*724ba675SRob Herring src7: src-7 { 1277*724ba675SRob Herring interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1278*724ba675SRob Herring dmas = <&audma0 0x93>, <&audma1 0xb6>; 1279*724ba675SRob Herring dma-names = "rx", "tx"; 1280*724ba675SRob Herring }; 1281*724ba675SRob Herring src8: src-8 { 1282*724ba675SRob Herring interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1283*724ba675SRob Herring dmas = <&audma0 0x95>, <&audma1 0xb8>; 1284*724ba675SRob Herring dma-names = "rx", "tx"; 1285*724ba675SRob Herring }; 1286*724ba675SRob Herring src9: src-9 { 1287*724ba675SRob Herring interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1288*724ba675SRob Herring dmas = <&audma0 0x97>, <&audma1 0xba>; 1289*724ba675SRob Herring dma-names = "rx", "tx"; 1290*724ba675SRob Herring }; 1291*724ba675SRob Herring }; 1292*724ba675SRob Herring 1293*724ba675SRob Herring rcar_sound,ssi { 1294*724ba675SRob Herring ssi0: ssi-0 { 1295*724ba675SRob Herring interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1296*724ba675SRob Herring dmas = <&audma0 0x01>, <&audma1 0x02>, 1297*724ba675SRob Herring <&audma0 0x15>, <&audma1 0x16>; 1298*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1299*724ba675SRob Herring }; 1300*724ba675SRob Herring ssi1: ssi-1 { 1301*724ba675SRob Herring interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1302*724ba675SRob Herring dmas = <&audma0 0x03>, <&audma1 0x04>, 1303*724ba675SRob Herring <&audma0 0x49>, <&audma1 0x4a>; 1304*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1305*724ba675SRob Herring }; 1306*724ba675SRob Herring ssi2: ssi-2 { 1307*724ba675SRob Herring interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1308*724ba675SRob Herring dmas = <&audma0 0x05>, <&audma1 0x06>, 1309*724ba675SRob Herring <&audma0 0x63>, <&audma1 0x64>; 1310*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1311*724ba675SRob Herring }; 1312*724ba675SRob Herring ssi3: ssi-3 { 1313*724ba675SRob Herring interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1314*724ba675SRob Herring dmas = <&audma0 0x07>, <&audma1 0x08>, 1315*724ba675SRob Herring <&audma0 0x6f>, <&audma1 0x70>; 1316*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1317*724ba675SRob Herring }; 1318*724ba675SRob Herring ssi4: ssi-4 { 1319*724ba675SRob Herring interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1320*724ba675SRob Herring dmas = <&audma0 0x09>, <&audma1 0x0a>, 1321*724ba675SRob Herring <&audma0 0x71>, <&audma1 0x72>; 1322*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1323*724ba675SRob Herring }; 1324*724ba675SRob Herring ssi5: ssi-5 { 1325*724ba675SRob Herring interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1326*724ba675SRob Herring dmas = <&audma0 0x0b>, <&audma1 0x0c>, 1327*724ba675SRob Herring <&audma0 0x73>, <&audma1 0x74>; 1328*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1329*724ba675SRob Herring }; 1330*724ba675SRob Herring ssi6: ssi-6 { 1331*724ba675SRob Herring interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1332*724ba675SRob Herring dmas = <&audma0 0x0d>, <&audma1 0x0e>, 1333*724ba675SRob Herring <&audma0 0x75>, <&audma1 0x76>; 1334*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1335*724ba675SRob Herring }; 1336*724ba675SRob Herring ssi7: ssi-7 { 1337*724ba675SRob Herring interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1338*724ba675SRob Herring dmas = <&audma0 0x0f>, <&audma1 0x10>, 1339*724ba675SRob Herring <&audma0 0x79>, <&audma1 0x7a>; 1340*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1341*724ba675SRob Herring }; 1342*724ba675SRob Herring ssi8: ssi-8 { 1343*724ba675SRob Herring interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1344*724ba675SRob Herring dmas = <&audma0 0x11>, <&audma1 0x12>, 1345*724ba675SRob Herring <&audma0 0x7b>, <&audma1 0x7c>; 1346*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1347*724ba675SRob Herring }; 1348*724ba675SRob Herring ssi9: ssi-9 { 1349*724ba675SRob Herring interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1350*724ba675SRob Herring dmas = <&audma0 0x13>, <&audma1 0x14>, 1351*724ba675SRob Herring <&audma0 0x7d>, <&audma1 0x7e>; 1352*724ba675SRob Herring dma-names = "rx", "tx", "rxu", "txu"; 1353*724ba675SRob Herring }; 1354*724ba675SRob Herring }; 1355*724ba675SRob Herring }; 1356*724ba675SRob Herring 1357*724ba675SRob Herring audma0: dma-controller@ec700000 { 1358*724ba675SRob Herring compatible = "renesas,dmac-r8a7742", 1359*724ba675SRob Herring "renesas,rcar-dmac"; 1360*724ba675SRob Herring reg = <0 0xec700000 0 0x10000>; 1361*724ba675SRob Herring interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 1362*724ba675SRob Herring <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1363*724ba675SRob Herring <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1364*724ba675SRob Herring <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1365*724ba675SRob Herring <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1366*724ba675SRob Herring <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1367*724ba675SRob Herring <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1368*724ba675SRob Herring <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1369*724ba675SRob Herring <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1370*724ba675SRob Herring <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1371*724ba675SRob Herring <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1372*724ba675SRob Herring <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1373*724ba675SRob Herring <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1374*724ba675SRob Herring <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1375*724ba675SRob Herring interrupt-names = "error", 1376*724ba675SRob Herring "ch0", "ch1", "ch2", "ch3", 1377*724ba675SRob Herring "ch4", "ch5", "ch6", "ch7", 1378*724ba675SRob Herring "ch8", "ch9", "ch10", "ch11", 1379*724ba675SRob Herring "ch12"; 1380*724ba675SRob Herring clocks = <&cpg CPG_MOD 502>; 1381*724ba675SRob Herring clock-names = "fck"; 1382*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1383*724ba675SRob Herring resets = <&cpg 502>; 1384*724ba675SRob Herring #dma-cells = <1>; 1385*724ba675SRob Herring dma-channels = <13>; 1386*724ba675SRob Herring }; 1387*724ba675SRob Herring 1388*724ba675SRob Herring audma1: dma-controller@ec720000 { 1389*724ba675SRob Herring compatible = "renesas,dmac-r8a7742", 1390*724ba675SRob Herring "renesas,rcar-dmac"; 1391*724ba675SRob Herring reg = <0 0xec720000 0 0x10000>; 1392*724ba675SRob Herring interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1393*724ba675SRob Herring <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1394*724ba675SRob Herring <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1395*724ba675SRob Herring <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1396*724ba675SRob Herring <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1397*724ba675SRob Herring <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1398*724ba675SRob Herring <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1399*724ba675SRob Herring <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1400*724ba675SRob Herring <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1401*724ba675SRob Herring <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1402*724ba675SRob Herring <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1403*724ba675SRob Herring <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1404*724ba675SRob Herring <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1405*724ba675SRob Herring <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 1406*724ba675SRob Herring interrupt-names = "error", 1407*724ba675SRob Herring "ch0", "ch1", "ch2", "ch3", 1408*724ba675SRob Herring "ch4", "ch5", "ch6", "ch7", 1409*724ba675SRob Herring "ch8", "ch9", "ch10", "ch11", 1410*724ba675SRob Herring "ch12"; 1411*724ba675SRob Herring clocks = <&cpg CPG_MOD 501>; 1412*724ba675SRob Herring clock-names = "fck"; 1413*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1414*724ba675SRob Herring resets = <&cpg 501>; 1415*724ba675SRob Herring #dma-cells = <1>; 1416*724ba675SRob Herring dma-channels = <13>; 1417*724ba675SRob Herring }; 1418*724ba675SRob Herring 1419*724ba675SRob Herring xhci: usb@ee000000 { 1420*724ba675SRob Herring compatible = "renesas,xhci-r8a7742", 1421*724ba675SRob Herring "renesas,rcar-gen2-xhci"; 1422*724ba675SRob Herring reg = <0 0xee000000 0 0xc00>; 1423*724ba675SRob Herring interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1424*724ba675SRob Herring clocks = <&cpg CPG_MOD 328>; 1425*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1426*724ba675SRob Herring resets = <&cpg 328>; 1427*724ba675SRob Herring phys = <&usb2 1>; 1428*724ba675SRob Herring phy-names = "usb"; 1429*724ba675SRob Herring status = "disabled"; 1430*724ba675SRob Herring }; 1431*724ba675SRob Herring 1432*724ba675SRob Herring pci0: pci@ee090000 { 1433*724ba675SRob Herring compatible = "renesas,pci-r8a7742", 1434*724ba675SRob Herring "renesas,pci-rcar-gen2"; 1435*724ba675SRob Herring device_type = "pci"; 1436*724ba675SRob Herring reg = <0 0xee090000 0 0xc00>, 1437*724ba675SRob Herring <0 0xee080000 0 0x1100>; 1438*724ba675SRob Herring interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1439*724ba675SRob Herring clocks = <&cpg CPG_MOD 703>; 1440*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1441*724ba675SRob Herring resets = <&cpg 703>; 1442*724ba675SRob Herring status = "disabled"; 1443*724ba675SRob Herring 1444*724ba675SRob Herring bus-range = <0 0>; 1445*724ba675SRob Herring #address-cells = <3>; 1446*724ba675SRob Herring #size-cells = <2>; 1447*724ba675SRob Herring #interrupt-cells = <1>; 1448*724ba675SRob Herring ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; 1449*724ba675SRob Herring interrupt-map-mask = <0xf800 0 0 0x7>; 1450*724ba675SRob Herring interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1451*724ba675SRob Herring <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1452*724ba675SRob Herring <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1453*724ba675SRob Herring 1454*724ba675SRob Herring usb@1,0 { 1455*724ba675SRob Herring reg = <0x800 0 0 0 0>; 1456*724ba675SRob Herring phys = <&usb0 0>; 1457*724ba675SRob Herring phy-names = "usb"; 1458*724ba675SRob Herring }; 1459*724ba675SRob Herring 1460*724ba675SRob Herring usb@2,0 { 1461*724ba675SRob Herring reg = <0x1000 0 0 0 0>; 1462*724ba675SRob Herring phys = <&usb0 0>; 1463*724ba675SRob Herring phy-names = "usb"; 1464*724ba675SRob Herring }; 1465*724ba675SRob Herring }; 1466*724ba675SRob Herring 1467*724ba675SRob Herring pci1: pci@ee0b0000 { 1468*724ba675SRob Herring compatible = "renesas,pci-r8a7742", 1469*724ba675SRob Herring "renesas,pci-rcar-gen2"; 1470*724ba675SRob Herring device_type = "pci"; 1471*724ba675SRob Herring reg = <0 0xee0b0000 0 0xc00>, 1472*724ba675SRob Herring <0 0xee0a0000 0 0x1100>; 1473*724ba675SRob Herring interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1474*724ba675SRob Herring clocks = <&cpg CPG_MOD 703>; 1475*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1476*724ba675SRob Herring resets = <&cpg 703>; 1477*724ba675SRob Herring status = "disabled"; 1478*724ba675SRob Herring 1479*724ba675SRob Herring bus-range = <1 1>; 1480*724ba675SRob Herring #address-cells = <3>; 1481*724ba675SRob Herring #size-cells = <2>; 1482*724ba675SRob Herring #interrupt-cells = <1>; 1483*724ba675SRob Herring ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; 1484*724ba675SRob Herring interrupt-map-mask = <0xf800 0 0 0x7>; 1485*724ba675SRob Herring interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1486*724ba675SRob Herring <0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1487*724ba675SRob Herring <0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1488*724ba675SRob Herring }; 1489*724ba675SRob Herring 1490*724ba675SRob Herring pci2: pci@ee0d0000 { 1491*724ba675SRob Herring compatible = "renesas,pci-r8a7742", 1492*724ba675SRob Herring "renesas,pci-rcar-gen2"; 1493*724ba675SRob Herring device_type = "pci"; 1494*724ba675SRob Herring clocks = <&cpg CPG_MOD 703>; 1495*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1496*724ba675SRob Herring resets = <&cpg 703>; 1497*724ba675SRob Herring reg = <0 0xee0d0000 0 0xc00>, 1498*724ba675SRob Herring <0 0xee0c0000 0 0x1100>; 1499*724ba675SRob Herring interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1500*724ba675SRob Herring status = "disabled"; 1501*724ba675SRob Herring 1502*724ba675SRob Herring bus-range = <2 2>; 1503*724ba675SRob Herring #address-cells = <3>; 1504*724ba675SRob Herring #size-cells = <2>; 1505*724ba675SRob Herring #interrupt-cells = <1>; 1506*724ba675SRob Herring ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; 1507*724ba675SRob Herring interrupt-map-mask = <0xf800 0 0 0x7>; 1508*724ba675SRob Herring interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1509*724ba675SRob Herring <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1510*724ba675SRob Herring <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1511*724ba675SRob Herring 1512*724ba675SRob Herring usb@1,0 { 1513*724ba675SRob Herring reg = <0x20800 0 0 0 0>; 1514*724ba675SRob Herring phys = <&usb2 0>; 1515*724ba675SRob Herring phy-names = "usb"; 1516*724ba675SRob Herring }; 1517*724ba675SRob Herring 1518*724ba675SRob Herring usb@2,0 { 1519*724ba675SRob Herring reg = <0x21000 0 0 0 0>; 1520*724ba675SRob Herring phys = <&usb2 0>; 1521*724ba675SRob Herring phy-names = "usb"; 1522*724ba675SRob Herring }; 1523*724ba675SRob Herring }; 1524*724ba675SRob Herring 1525*724ba675SRob Herring sdhi0: mmc@ee100000 { 1526*724ba675SRob Herring compatible = "renesas,sdhi-r8a7742", 1527*724ba675SRob Herring "renesas,rcar-gen2-sdhi"; 1528*724ba675SRob Herring reg = <0 0xee100000 0 0x328>; 1529*724ba675SRob Herring interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1530*724ba675SRob Herring clocks = <&cpg CPG_MOD 314>; 1531*724ba675SRob Herring dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 1532*724ba675SRob Herring <&dmac1 0xcd>, <&dmac1 0xce>; 1533*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 1534*724ba675SRob Herring max-frequency = <195000000>; 1535*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1536*724ba675SRob Herring resets = <&cpg 314>; 1537*724ba675SRob Herring status = "disabled"; 1538*724ba675SRob Herring }; 1539*724ba675SRob Herring 1540*724ba675SRob Herring sdhi1: mmc@ee120000 { 1541*724ba675SRob Herring compatible = "renesas,sdhi-r8a7742", 1542*724ba675SRob Herring "renesas,rcar-gen2-sdhi"; 1543*724ba675SRob Herring reg = <0 0xee120000 0 0x328>; 1544*724ba675SRob Herring interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1545*724ba675SRob Herring clocks = <&cpg CPG_MOD 313>; 1546*724ba675SRob Herring dmas = <&dmac0 0xc9>, <&dmac0 0xca>, 1547*724ba675SRob Herring <&dmac1 0xc9>, <&dmac1 0xca>; 1548*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 1549*724ba675SRob Herring max-frequency = <195000000>; 1550*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1551*724ba675SRob Herring resets = <&cpg 313>; 1552*724ba675SRob Herring status = "disabled"; 1553*724ba675SRob Herring }; 1554*724ba675SRob Herring 1555*724ba675SRob Herring sdhi2: mmc@ee140000 { 1556*724ba675SRob Herring compatible = "renesas,sdhi-r8a7742", 1557*724ba675SRob Herring "renesas,rcar-gen2-sdhi"; 1558*724ba675SRob Herring reg = <0 0xee140000 0 0x100>; 1559*724ba675SRob Herring interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1560*724ba675SRob Herring clocks = <&cpg CPG_MOD 312>; 1561*724ba675SRob Herring dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, 1562*724ba675SRob Herring <&dmac1 0xc1>, <&dmac1 0xc2>; 1563*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 1564*724ba675SRob Herring max-frequency = <97500000>; 1565*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1566*724ba675SRob Herring resets = <&cpg 312>; 1567*724ba675SRob Herring status = "disabled"; 1568*724ba675SRob Herring }; 1569*724ba675SRob Herring 1570*724ba675SRob Herring sdhi3: mmc@ee160000 { 1571*724ba675SRob Herring compatible = "renesas,sdhi-r8a7742", 1572*724ba675SRob Herring "renesas,rcar-gen2-sdhi"; 1573*724ba675SRob Herring reg = <0 0xee160000 0 0x100>; 1574*724ba675SRob Herring interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1575*724ba675SRob Herring clocks = <&cpg CPG_MOD 311>; 1576*724ba675SRob Herring dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, 1577*724ba675SRob Herring <&dmac1 0xd3>, <&dmac1 0xd4>; 1578*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 1579*724ba675SRob Herring max-frequency = <97500000>; 1580*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1581*724ba675SRob Herring resets = <&cpg 311>; 1582*724ba675SRob Herring status = "disabled"; 1583*724ba675SRob Herring }; 1584*724ba675SRob Herring 1585*724ba675SRob Herring mmcif0: mmc@ee200000 { 1586*724ba675SRob Herring compatible = "renesas,mmcif-r8a7742", 1587*724ba675SRob Herring "renesas,sh-mmcif"; 1588*724ba675SRob Herring reg = <0 0xee200000 0 0x80>; 1589*724ba675SRob Herring interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1590*724ba675SRob Herring clocks = <&cpg CPG_MOD 315>; 1591*724ba675SRob Herring dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, 1592*724ba675SRob Herring <&dmac1 0xd1>, <&dmac1 0xd2>; 1593*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 1594*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1595*724ba675SRob Herring resets = <&cpg 315>; 1596*724ba675SRob Herring reg-io-width = <4>; 1597*724ba675SRob Herring status = "disabled"; 1598*724ba675SRob Herring max-frequency = <97500000>; 1599*724ba675SRob Herring }; 1600*724ba675SRob Herring 1601*724ba675SRob Herring mmcif1: mmc@ee220000 { 1602*724ba675SRob Herring compatible = "renesas,mmcif-r8a7742", 1603*724ba675SRob Herring "renesas,sh-mmcif"; 1604*724ba675SRob Herring reg = <0 0xee220000 0 0x80>; 1605*724ba675SRob Herring interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1606*724ba675SRob Herring clocks = <&cpg CPG_MOD 305>; 1607*724ba675SRob Herring dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, 1608*724ba675SRob Herring <&dmac1 0xe1>, <&dmac1 0xe2>; 1609*724ba675SRob Herring dma-names = "tx", "rx", "tx", "rx"; 1610*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1611*724ba675SRob Herring resets = <&cpg 305>; 1612*724ba675SRob Herring reg-io-width = <4>; 1613*724ba675SRob Herring status = "disabled"; 1614*724ba675SRob Herring max-frequency = <97500000>; 1615*724ba675SRob Herring }; 1616*724ba675SRob Herring 1617*724ba675SRob Herring sata0: sata@ee300000 { 1618*724ba675SRob Herring compatible = "renesas,sata-r8a7742", 1619*724ba675SRob Herring "renesas,rcar-gen2-sata"; 1620*724ba675SRob Herring reg = <0 0xee300000 0 0x200000>; 1621*724ba675SRob Herring interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1622*724ba675SRob Herring clocks = <&cpg CPG_MOD 815>; 1623*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1624*724ba675SRob Herring resets = <&cpg 815>; 1625*724ba675SRob Herring status = "disabled"; 1626*724ba675SRob Herring }; 1627*724ba675SRob Herring 1628*724ba675SRob Herring sata1: sata@ee500000 { 1629*724ba675SRob Herring compatible = "renesas,sata-r8a7742", 1630*724ba675SRob Herring "renesas,rcar-gen2-sata"; 1631*724ba675SRob Herring reg = <0 0xee500000 0 0x200000>; 1632*724ba675SRob Herring interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1633*724ba675SRob Herring clocks = <&cpg CPG_MOD 814>; 1634*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1635*724ba675SRob Herring resets = <&cpg 814>; 1636*724ba675SRob Herring status = "disabled"; 1637*724ba675SRob Herring }; 1638*724ba675SRob Herring 1639*724ba675SRob Herring ether: ethernet@ee700000 { 1640*724ba675SRob Herring compatible = "renesas,ether-r8a7742", 1641*724ba675SRob Herring "renesas,rcar-gen2-ether"; 1642*724ba675SRob Herring reg = <0 0xee700000 0 0x400>; 1643*724ba675SRob Herring interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1644*724ba675SRob Herring clocks = <&cpg CPG_MOD 813>; 1645*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1646*724ba675SRob Herring resets = <&cpg 813>; 1647*724ba675SRob Herring phy-mode = "rmii"; 1648*724ba675SRob Herring #address-cells = <1>; 1649*724ba675SRob Herring #size-cells = <0>; 1650*724ba675SRob Herring status = "disabled"; 1651*724ba675SRob Herring }; 1652*724ba675SRob Herring 1653*724ba675SRob Herring gic: interrupt-controller@f1001000 { 1654*724ba675SRob Herring compatible = "arm,gic-400"; 1655*724ba675SRob Herring #interrupt-cells = <3>; 1656*724ba675SRob Herring #address-cells = <0>; 1657*724ba675SRob Herring interrupt-controller; 1658*724ba675SRob Herring reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, 1659*724ba675SRob Herring <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; 1660*724ba675SRob Herring interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1661*724ba675SRob Herring clocks = <&cpg CPG_MOD 408>; 1662*724ba675SRob Herring clock-names = "clk"; 1663*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1664*724ba675SRob Herring resets = <&cpg 408>; 1665*724ba675SRob Herring }; 1666*724ba675SRob Herring 1667*724ba675SRob Herring pciec: pcie@fe000000 { 1668*724ba675SRob Herring compatible = "renesas,pcie-r8a7742", 1669*724ba675SRob Herring "renesas,pcie-rcar-gen2"; 1670*724ba675SRob Herring reg = <0 0xfe000000 0 0x80000>; 1671*724ba675SRob Herring #address-cells = <3>; 1672*724ba675SRob Herring #size-cells = <2>; 1673*724ba675SRob Herring bus-range = <0x00 0xff>; 1674*724ba675SRob Herring device_type = "pci"; 1675*724ba675SRob Herring ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 1676*724ba675SRob Herring <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 1677*724ba675SRob Herring <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 1678*724ba675SRob Herring <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1679*724ba675SRob Herring /* Map all possible DDR as inbound ranges */ 1680*724ba675SRob Herring dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, 1681*724ba675SRob Herring <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; 1682*724ba675SRob Herring interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1683*724ba675SRob Herring <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1684*724ba675SRob Herring <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1685*724ba675SRob Herring #interrupt-cells = <1>; 1686*724ba675SRob Herring interrupt-map-mask = <0 0 0 0>; 1687*724ba675SRob Herring interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1688*724ba675SRob Herring clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1689*724ba675SRob Herring clock-names = "pcie", "pcie_bus"; 1690*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1691*724ba675SRob Herring resets = <&cpg 319>; 1692*724ba675SRob Herring status = "disabled"; 1693*724ba675SRob Herring }; 1694*724ba675SRob Herring 1695*724ba675SRob Herring vsp@fe920000 { 1696*724ba675SRob Herring compatible = "renesas,vsp1"; 1697*724ba675SRob Herring reg = <0 0xfe920000 0 0x8000>; 1698*724ba675SRob Herring interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1699*724ba675SRob Herring clocks = <&cpg CPG_MOD 130>; 1700*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1701*724ba675SRob Herring resets = <&cpg 130>; 1702*724ba675SRob Herring }; 1703*724ba675SRob Herring 1704*724ba675SRob Herring vsp@fe928000 { 1705*724ba675SRob Herring compatible = "renesas,vsp1"; 1706*724ba675SRob Herring reg = <0 0xfe928000 0 0x8000>; 1707*724ba675SRob Herring interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 1708*724ba675SRob Herring clocks = <&cpg CPG_MOD 131>; 1709*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1710*724ba675SRob Herring resets = <&cpg 131>; 1711*724ba675SRob Herring }; 1712*724ba675SRob Herring 1713*724ba675SRob Herring vsp@fe930000 { 1714*724ba675SRob Herring compatible = "renesas,vsp1"; 1715*724ba675SRob Herring reg = <0 0xfe930000 0 0x8000>; 1716*724ba675SRob Herring interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1717*724ba675SRob Herring clocks = <&cpg CPG_MOD 128>; 1718*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1719*724ba675SRob Herring resets = <&cpg 128>; 1720*724ba675SRob Herring }; 1721*724ba675SRob Herring 1722*724ba675SRob Herring vsp@fe938000 { 1723*724ba675SRob Herring compatible = "renesas,vsp1"; 1724*724ba675SRob Herring reg = <0 0xfe938000 0 0x8000>; 1725*724ba675SRob Herring interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 1726*724ba675SRob Herring clocks = <&cpg CPG_MOD 127>; 1727*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1728*724ba675SRob Herring resets = <&cpg 127>; 1729*724ba675SRob Herring }; 1730*724ba675SRob Herring 1731*724ba675SRob Herring du: display@feb00000 { 1732*724ba675SRob Herring compatible = "renesas,du-r8a7742"; 1733*724ba675SRob Herring reg = <0 0xfeb00000 0 0x70000>; 1734*724ba675SRob Herring interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1735*724ba675SRob Herring <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 1736*724ba675SRob Herring <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 1737*724ba675SRob Herring clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 1738*724ba675SRob Herring <&cpg CPG_MOD 722>; 1739*724ba675SRob Herring clock-names = "du.0", "du.1", "du.2"; 1740*724ba675SRob Herring resets = <&cpg 724>; 1741*724ba675SRob Herring reset-names = "du.0"; 1742*724ba675SRob Herring status = "disabled"; 1743*724ba675SRob Herring 1744*724ba675SRob Herring ports { 1745*724ba675SRob Herring #address-cells = <1>; 1746*724ba675SRob Herring #size-cells = <0>; 1747*724ba675SRob Herring 1748*724ba675SRob Herring port@0 { 1749*724ba675SRob Herring reg = <0>; 1750*724ba675SRob Herring du_out_rgb: endpoint { 1751*724ba675SRob Herring }; 1752*724ba675SRob Herring }; 1753*724ba675SRob Herring port@1 { 1754*724ba675SRob Herring reg = <1>; 1755*724ba675SRob Herring du_out_lvds0: endpoint { 1756*724ba675SRob Herring remote-endpoint = <&lvds0_in>; 1757*724ba675SRob Herring }; 1758*724ba675SRob Herring }; 1759*724ba675SRob Herring port@2 { 1760*724ba675SRob Herring reg = <2>; 1761*724ba675SRob Herring du_out_lvds1: endpoint { 1762*724ba675SRob Herring remote-endpoint = <&lvds1_in>; 1763*724ba675SRob Herring }; 1764*724ba675SRob Herring }; 1765*724ba675SRob Herring }; 1766*724ba675SRob Herring }; 1767*724ba675SRob Herring 1768*724ba675SRob Herring lvds0: lvds@feb90000 { 1769*724ba675SRob Herring compatible = "renesas,r8a7742-lvds"; 1770*724ba675SRob Herring reg = <0 0xfeb90000 0 0x14>; 1771*724ba675SRob Herring clocks = <&cpg CPG_MOD 726>; 1772*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1773*724ba675SRob Herring resets = <&cpg 726>; 1774*724ba675SRob Herring status = "disabled"; 1775*724ba675SRob Herring 1776*724ba675SRob Herring ports { 1777*724ba675SRob Herring #address-cells = <1>; 1778*724ba675SRob Herring #size-cells = <0>; 1779*724ba675SRob Herring 1780*724ba675SRob Herring port@0 { 1781*724ba675SRob Herring reg = <0>; 1782*724ba675SRob Herring lvds0_in: endpoint { 1783*724ba675SRob Herring remote-endpoint = <&du_out_lvds0>; 1784*724ba675SRob Herring }; 1785*724ba675SRob Herring }; 1786*724ba675SRob Herring port@1 { 1787*724ba675SRob Herring reg = <1>; 1788*724ba675SRob Herring lvds0_out: endpoint { 1789*724ba675SRob Herring }; 1790*724ba675SRob Herring }; 1791*724ba675SRob Herring }; 1792*724ba675SRob Herring }; 1793*724ba675SRob Herring 1794*724ba675SRob Herring lvds1: lvds@feb94000 { 1795*724ba675SRob Herring compatible = "renesas,r8a7742-lvds"; 1796*724ba675SRob Herring reg = <0 0xfeb94000 0 0x14>; 1797*724ba675SRob Herring clocks = <&cpg CPG_MOD 725>; 1798*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1799*724ba675SRob Herring resets = <&cpg 725>; 1800*724ba675SRob Herring status = "disabled"; 1801*724ba675SRob Herring 1802*724ba675SRob Herring ports { 1803*724ba675SRob Herring #address-cells = <1>; 1804*724ba675SRob Herring #size-cells = <0>; 1805*724ba675SRob Herring 1806*724ba675SRob Herring port@0 { 1807*724ba675SRob Herring reg = <0>; 1808*724ba675SRob Herring lvds1_in: endpoint { 1809*724ba675SRob Herring remote-endpoint = <&du_out_lvds1>; 1810*724ba675SRob Herring }; 1811*724ba675SRob Herring }; 1812*724ba675SRob Herring port@1 { 1813*724ba675SRob Herring reg = <1>; 1814*724ba675SRob Herring lvds1_out: endpoint { 1815*724ba675SRob Herring }; 1816*724ba675SRob Herring }; 1817*724ba675SRob Herring }; 1818*724ba675SRob Herring }; 1819*724ba675SRob Herring 1820*724ba675SRob Herring prr: chipid@ff000044 { 1821*724ba675SRob Herring compatible = "renesas,prr"; 1822*724ba675SRob Herring reg = <0 0xff000044 0 4>; 1823*724ba675SRob Herring }; 1824*724ba675SRob Herring 1825*724ba675SRob Herring cmt0: timer@ffca0000 { 1826*724ba675SRob Herring compatible = "renesas,r8a7742-cmt0", 1827*724ba675SRob Herring "renesas,rcar-gen2-cmt0"; 1828*724ba675SRob Herring reg = <0 0xffca0000 0 0x1004>; 1829*724ba675SRob Herring interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1830*724ba675SRob Herring <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1831*724ba675SRob Herring clocks = <&cpg CPG_MOD 124>; 1832*724ba675SRob Herring clock-names = "fck"; 1833*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1834*724ba675SRob Herring resets = <&cpg 124>; 1835*724ba675SRob Herring status = "disabled"; 1836*724ba675SRob Herring }; 1837*724ba675SRob Herring 1838*724ba675SRob Herring cmt1: timer@e6130000 { 1839*724ba675SRob Herring compatible = "renesas,r8a7742-cmt1", 1840*724ba675SRob Herring "renesas,rcar-gen2-cmt1"; 1841*724ba675SRob Herring reg = <0 0xe6130000 0 0x1004>; 1842*724ba675SRob Herring interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1843*724ba675SRob Herring <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1844*724ba675SRob Herring <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1845*724ba675SRob Herring <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1846*724ba675SRob Herring <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1847*724ba675SRob Herring <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1848*724ba675SRob Herring <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1849*724ba675SRob Herring <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1850*724ba675SRob Herring clocks = <&cpg CPG_MOD 329>; 1851*724ba675SRob Herring clock-names = "fck"; 1852*724ba675SRob Herring power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1853*724ba675SRob Herring resets = <&cpg 329>; 1854*724ba675SRob Herring status = "disabled"; 1855*724ba675SRob Herring }; 1856*724ba675SRob Herring }; 1857*724ba675SRob Herring 1858*724ba675SRob Herring thermal-zones { 1859*724ba675SRob Herring cpu_thermal: cpu-thermal { 1860*724ba675SRob Herring polling-delay-passive = <0>; 1861*724ba675SRob Herring polling-delay = <0>; 1862*724ba675SRob Herring 1863*724ba675SRob Herring thermal-sensors = <&thermal>; 1864*724ba675SRob Herring 1865*724ba675SRob Herring trips { 1866*724ba675SRob Herring cpu-crit { 1867*724ba675SRob Herring temperature = <95000>; 1868*724ba675SRob Herring hysteresis = <0>; 1869*724ba675SRob Herring type = "critical"; 1870*724ba675SRob Herring }; 1871*724ba675SRob Herring }; 1872*724ba675SRob Herring cooling-maps { 1873*724ba675SRob Herring }; 1874*724ba675SRob Herring }; 1875*724ba675SRob Herring }; 1876*724ba675SRob Herring 1877*724ba675SRob Herring timer { 1878*724ba675SRob Herring compatible = "arm,armv7-timer"; 1879*724ba675SRob Herring interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1880*724ba675SRob Herring <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1881*724ba675SRob Herring <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1882*724ba675SRob Herring <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1883*724ba675SRob Herring }; 1884*724ba675SRob Herring 1885*724ba675SRob Herring /* External USB clock - can be overridden by the board */ 1886*724ba675SRob Herring usb_extal_clk: usb_extal { 1887*724ba675SRob Herring compatible = "fixed-clock"; 1888*724ba675SRob Herring #clock-cells = <0>; 1889*724ba675SRob Herring clock-frequency = <48000000>; 1890*724ba675SRob Herring }; 1891*724ba675SRob Herring}; 1892