1724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2724ba675SRob Herring/* 3724ba675SRob Herring * Device Tree Source for the r8a73a4 SoC 4724ba675SRob Herring * 5724ba675SRob Herring * Copyright (C) 2013 Renesas Solutions Corp. 6724ba675SRob Herring * Copyright (C) 2013 Magnus Damm 7724ba675SRob Herring */ 8724ba675SRob Herring 9724ba675SRob Herring#include <dt-bindings/clock/r8a73a4-clock.h> 10724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 11724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 12724ba675SRob Herring 13724ba675SRob Herring/ { 14724ba675SRob Herring compatible = "renesas,r8a73a4"; 15724ba675SRob Herring interrupt-parent = <&gic>; 16724ba675SRob Herring #address-cells = <2>; 17724ba675SRob Herring #size-cells = <2>; 18724ba675SRob Herring 19724ba675SRob Herring cpus { 20724ba675SRob Herring #address-cells = <1>; 21724ba675SRob Herring #size-cells = <0>; 22724ba675SRob Herring 23724ba675SRob Herring cpu0: cpu@0 { 24724ba675SRob Herring device_type = "cpu"; 25724ba675SRob Herring compatible = "arm,cortex-a15"; 26724ba675SRob Herring reg = <0>; 27724ba675SRob Herring clocks = <&cpg_clocks R8A73A4_CLK_Z>; 28724ba675SRob Herring clock-frequency = <1500000000>; 29724ba675SRob Herring power-domains = <&pd_a2sl>; 30724ba675SRob Herring next-level-cache = <&L2_CA15>; 31724ba675SRob Herring }; 32724ba675SRob Herring 33724ba675SRob Herring L2_CA15: cache-controller-0 { 34724ba675SRob Herring compatible = "cache"; 35724ba675SRob Herring clocks = <&cpg_clocks R8A73A4_CLK_Z>; 36724ba675SRob Herring power-domains = <&pd_a3sm>; 37724ba675SRob Herring cache-unified; 38724ba675SRob Herring cache-level = <2>; 39724ba675SRob Herring }; 40724ba675SRob Herring 41724ba675SRob Herring L2_CA7: cache-controller-1 { 42724ba675SRob Herring compatible = "cache"; 43724ba675SRob Herring clocks = <&cpg_clocks R8A73A4_CLK_Z2>; 44724ba675SRob Herring power-domains = <&pd_a3km>; 45724ba675SRob Herring cache-unified; 46724ba675SRob Herring cache-level = <2>; 47724ba675SRob Herring }; 48724ba675SRob Herring }; 49724ba675SRob Herring 50724ba675SRob Herring ptm { 51724ba675SRob Herring compatible = "arm,coresight-etm3x"; 52724ba675SRob Herring power-domains = <&pd_d4>; 53724ba675SRob Herring }; 54724ba675SRob Herring 55724ba675SRob Herring timer { 56724ba675SRob Herring compatible = "arm,armv7-timer"; 57724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 58724ba675SRob Herring <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 59724ba675SRob Herring <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 60724ba675SRob Herring <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 61724ba675SRob Herring }; 62724ba675SRob Herring 63724ba675SRob Herring dbsc1: memory-controller@e6790000 { 64724ba675SRob Herring compatible = "renesas,dbsc-r8a73a4"; 65724ba675SRob Herring reg = <0 0xe6790000 0 0x10000>; 66724ba675SRob Herring power-domains = <&pd_a3bc>; 67724ba675SRob Herring }; 68724ba675SRob Herring 69724ba675SRob Herring dbsc2: memory-controller@e67a0000 { 70724ba675SRob Herring compatible = "renesas,dbsc-r8a73a4"; 71724ba675SRob Herring reg = <0 0xe67a0000 0 0x10000>; 72724ba675SRob Herring power-domains = <&pd_a3bc>; 73724ba675SRob Herring }; 74724ba675SRob Herring 75724ba675SRob Herring i2c5: i2c@e60b0000 { 76724ba675SRob Herring #address-cells = <1>; 77724ba675SRob Herring #size-cells = <0>; 78724ba675SRob Herring compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 79724ba675SRob Herring reg = <0 0xe60b0000 0 0x428>; 80724ba675SRob Herring interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 81724ba675SRob Herring clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; 82724ba675SRob Herring power-domains = <&pd_a3sp>; 83724ba675SRob Herring 84724ba675SRob Herring status = "disabled"; 85724ba675SRob Herring }; 86724ba675SRob Herring 87724ba675SRob Herring cmt1: timer@e6130000 { 88724ba675SRob Herring compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1"; 89724ba675SRob Herring reg = <0 0xe6130000 0 0x1004>; 90724ba675SRob Herring interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 91724ba675SRob Herring <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 92724ba675SRob Herring <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 93724ba675SRob Herring <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 94724ba675SRob Herring <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 95724ba675SRob Herring <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 96724ba675SRob Herring <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 97724ba675SRob Herring <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 98724ba675SRob Herring clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; 99724ba675SRob Herring clock-names = "fck"; 100724ba675SRob Herring power-domains = <&pd_c5>; 101724ba675SRob Herring status = "disabled"; 102724ba675SRob Herring }; 103724ba675SRob Herring 104724ba675SRob Herring irqc0: interrupt-controller@e61c0000 { 105724ba675SRob Herring compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; 106724ba675SRob Herring #interrupt-cells = <2>; 107724ba675SRob Herring interrupt-controller; 108724ba675SRob Herring reg = <0 0xe61c0000 0 0x200>; 109724ba675SRob Herring interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 110724ba675SRob Herring <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 111724ba675SRob Herring <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 112724ba675SRob Herring <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 113724ba675SRob Herring <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 114724ba675SRob Herring <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 115724ba675SRob Herring <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 116724ba675SRob Herring <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 117724ba675SRob Herring <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 118724ba675SRob Herring <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 119724ba675SRob Herring <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 120724ba675SRob Herring <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 121724ba675SRob Herring <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 122724ba675SRob Herring <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 123724ba675SRob Herring <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 124724ba675SRob Herring <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 125724ba675SRob Herring <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 126724ba675SRob Herring <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 127724ba675SRob Herring <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 128724ba675SRob Herring <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 129724ba675SRob Herring <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 130724ba675SRob Herring <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 131724ba675SRob Herring <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 132724ba675SRob Herring <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 133724ba675SRob Herring <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 134724ba675SRob Herring <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 135724ba675SRob Herring <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 136724ba675SRob Herring <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 137724ba675SRob Herring <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 138724ba675SRob Herring <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 139724ba675SRob Herring <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 140724ba675SRob Herring <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 141724ba675SRob Herring clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; 142724ba675SRob Herring power-domains = <&pd_c4>; 143724ba675SRob Herring }; 144724ba675SRob Herring 145724ba675SRob Herring irqc1: interrupt-controller@e61c0200 { 146724ba675SRob Herring compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; 147724ba675SRob Herring #interrupt-cells = <2>; 148724ba675SRob Herring interrupt-controller; 149724ba675SRob Herring reg = <0 0xe61c0200 0 0x200>; 150724ba675SRob Herring interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 151724ba675SRob Herring <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 152724ba675SRob Herring <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 153724ba675SRob Herring <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 154724ba675SRob Herring <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 155724ba675SRob Herring <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 156724ba675SRob Herring <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 157724ba675SRob Herring <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 158724ba675SRob Herring <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 159724ba675SRob Herring <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 160724ba675SRob Herring <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 161724ba675SRob Herring <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 162724ba675SRob Herring <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 163724ba675SRob Herring <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 164724ba675SRob Herring <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 165724ba675SRob Herring <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 166724ba675SRob Herring <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 167724ba675SRob Herring <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 168724ba675SRob Herring <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 169724ba675SRob Herring <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 170724ba675SRob Herring <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 171724ba675SRob Herring <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 172724ba675SRob Herring <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 173724ba675SRob Herring <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 174724ba675SRob Herring <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 175724ba675SRob Herring <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 176724ba675SRob Herring clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; 177724ba675SRob Herring power-domains = <&pd_c4>; 178724ba675SRob Herring }; 179724ba675SRob Herring 180724ba675SRob Herring pfc: pinctrl@e6050000 { 181724ba675SRob Herring compatible = "renesas,pfc-r8a73a4"; 182724ba675SRob Herring reg = <0 0xe6050000 0 0x9000>; 183724ba675SRob Herring gpio-controller; 184724ba675SRob Herring #gpio-cells = <2>; 185724ba675SRob Herring gpio-ranges = 186724ba675SRob Herring <&pfc 0 0 31>, <&pfc 32 32 9>, 187724ba675SRob Herring <&pfc 64 64 22>, <&pfc 96 96 31>, 188724ba675SRob Herring <&pfc 128 128 7>, <&pfc 160 160 19>, 189724ba675SRob Herring <&pfc 192 192 31>, <&pfc 224 224 27>, 190724ba675SRob Herring <&pfc 256 256 28>, <&pfc 288 288 21>, 191724ba675SRob Herring <&pfc 320 320 10>; 192724ba675SRob Herring interrupts-extended = 193724ba675SRob Herring <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, 194724ba675SRob Herring <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, 195724ba675SRob Herring <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, 196724ba675SRob Herring <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, 197724ba675SRob Herring <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, 198724ba675SRob Herring <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, 199724ba675SRob Herring <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, 200724ba675SRob Herring <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, 201724ba675SRob Herring <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, 202724ba675SRob Herring <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, 203724ba675SRob Herring <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, 204724ba675SRob Herring <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, 205724ba675SRob Herring <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, 206724ba675SRob Herring <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, 207724ba675SRob Herring <&irqc1 24 0>, <&irqc1 25 0>; 208724ba675SRob Herring power-domains = <&pd_c5>; 209724ba675SRob Herring }; 210724ba675SRob Herring 211724ba675SRob Herring thermal@e61f0000 { 212724ba675SRob Herring compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; 213724ba675SRob Herring reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, 214724ba675SRob Herring <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; 215724ba675SRob Herring interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 216724ba675SRob Herring clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; 217724ba675SRob Herring power-domains = <&pd_c5>; 218724ba675SRob Herring }; 219724ba675SRob Herring 220724ba675SRob Herring i2c0: i2c@e6500000 { 221724ba675SRob Herring #address-cells = <1>; 222724ba675SRob Herring #size-cells = <0>; 223724ba675SRob Herring compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 224724ba675SRob Herring reg = <0 0xe6500000 0 0x428>; 225724ba675SRob Herring interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 226724ba675SRob Herring clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; 227724ba675SRob Herring power-domains = <&pd_a3sp>; 228724ba675SRob Herring status = "disabled"; 229724ba675SRob Herring }; 230724ba675SRob Herring 231724ba675SRob Herring i2c1: i2c@e6510000 { 232724ba675SRob Herring #address-cells = <1>; 233724ba675SRob Herring #size-cells = <0>; 234724ba675SRob Herring compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 235724ba675SRob Herring reg = <0 0xe6510000 0 0x428>; 236724ba675SRob Herring interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 237724ba675SRob Herring clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; 238724ba675SRob Herring power-domains = <&pd_a3sp>; 239724ba675SRob Herring status = "disabled"; 240724ba675SRob Herring }; 241724ba675SRob Herring 242724ba675SRob Herring i2c2: i2c@e6520000 { 243724ba675SRob Herring #address-cells = <1>; 244724ba675SRob Herring #size-cells = <0>; 245724ba675SRob Herring compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 246724ba675SRob Herring reg = <0 0xe6520000 0 0x428>; 247724ba675SRob Herring interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 248724ba675SRob Herring clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; 249724ba675SRob Herring power-domains = <&pd_a3sp>; 250724ba675SRob Herring status = "disabled"; 251724ba675SRob Herring }; 252724ba675SRob Herring 253724ba675SRob Herring i2c3: i2c@e6530000 { 254724ba675SRob Herring #address-cells = <1>; 255724ba675SRob Herring #size-cells = <0>; 256724ba675SRob Herring compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 257724ba675SRob Herring reg = <0 0xe6530000 0 0x428>; 258724ba675SRob Herring interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 259724ba675SRob Herring clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; 260724ba675SRob Herring power-domains = <&pd_a3sp>; 261724ba675SRob Herring status = "disabled"; 262724ba675SRob Herring }; 263724ba675SRob Herring 264724ba675SRob Herring i2c4: i2c@e6540000 { 265724ba675SRob Herring #address-cells = <1>; 266724ba675SRob Herring #size-cells = <0>; 267724ba675SRob Herring compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 268724ba675SRob Herring reg = <0 0xe6540000 0 0x428>; 269724ba675SRob Herring interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 270724ba675SRob Herring clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; 271724ba675SRob Herring power-domains = <&pd_a3sp>; 272724ba675SRob Herring status = "disabled"; 273724ba675SRob Herring }; 274724ba675SRob Herring 275724ba675SRob Herring i2c6: i2c@e6550000 { 276724ba675SRob Herring #address-cells = <1>; 277724ba675SRob Herring #size-cells = <0>; 278724ba675SRob Herring compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 279724ba675SRob Herring reg = <0 0xe6550000 0 0x428>; 280724ba675SRob Herring interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 281724ba675SRob Herring clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; 282724ba675SRob Herring power-domains = <&pd_a3sp>; 283724ba675SRob Herring status = "disabled"; 284724ba675SRob Herring }; 285724ba675SRob Herring 286724ba675SRob Herring i2c7: i2c@e6560000 { 287724ba675SRob Herring #address-cells = <1>; 288724ba675SRob Herring #size-cells = <0>; 289724ba675SRob Herring compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 290724ba675SRob Herring reg = <0 0xe6560000 0 0x428>; 291724ba675SRob Herring interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 292724ba675SRob Herring clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; 293724ba675SRob Herring power-domains = <&pd_a3sp>; 294724ba675SRob Herring status = "disabled"; 295724ba675SRob Herring }; 296724ba675SRob Herring 297724ba675SRob Herring i2c8: i2c@e6570000 { 298724ba675SRob Herring #address-cells = <1>; 299724ba675SRob Herring #size-cells = <0>; 300724ba675SRob Herring compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 301724ba675SRob Herring reg = <0 0xe6570000 0 0x428>; 302724ba675SRob Herring interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 303724ba675SRob Herring clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; 304724ba675SRob Herring power-domains = <&pd_a3sp>; 305724ba675SRob Herring status = "disabled"; 306724ba675SRob Herring }; 307724ba675SRob Herring 308724ba675SRob Herring scifb0: serial@e6c20000 { 309724ba675SRob Herring compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 310724ba675SRob Herring reg = <0 0xe6c20000 0 0x100>; 311724ba675SRob Herring interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 312724ba675SRob Herring clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; 313724ba675SRob Herring clock-names = "fck"; 314724ba675SRob Herring power-domains = <&pd_a3sp>; 315724ba675SRob Herring status = "disabled"; 316724ba675SRob Herring }; 317724ba675SRob Herring 318724ba675SRob Herring scifb1: serial@e6c30000 { 319724ba675SRob Herring compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 320724ba675SRob Herring reg = <0 0xe6c30000 0 0x100>; 321724ba675SRob Herring interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 322724ba675SRob Herring clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; 323724ba675SRob Herring clock-names = "fck"; 324724ba675SRob Herring power-domains = <&pd_a3sp>; 325724ba675SRob Herring status = "disabled"; 326724ba675SRob Herring }; 327724ba675SRob Herring 328724ba675SRob Herring scifa0: serial@e6c40000 { 329724ba675SRob Herring compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; 330724ba675SRob Herring reg = <0 0xe6c40000 0 0x100>; 331724ba675SRob Herring interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 332724ba675SRob Herring clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; 333724ba675SRob Herring clock-names = "fck"; 334724ba675SRob Herring power-domains = <&pd_a3sp>; 335724ba675SRob Herring status = "disabled"; 336724ba675SRob Herring }; 337724ba675SRob Herring 338724ba675SRob Herring scifa1: serial@e6c50000 { 339724ba675SRob Herring compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; 340724ba675SRob Herring reg = <0 0xe6c50000 0 0x100>; 341724ba675SRob Herring interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 342724ba675SRob Herring clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; 343724ba675SRob Herring clock-names = "fck"; 344724ba675SRob Herring power-domains = <&pd_a3sp>; 345724ba675SRob Herring status = "disabled"; 346724ba675SRob Herring }; 347724ba675SRob Herring 348724ba675SRob Herring scifb2: serial@e6ce0000 { 349724ba675SRob Herring compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 350724ba675SRob Herring reg = <0 0xe6ce0000 0 0x100>; 351724ba675SRob Herring interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 352724ba675SRob Herring clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; 353724ba675SRob Herring clock-names = "fck"; 354724ba675SRob Herring power-domains = <&pd_a3sp>; 355724ba675SRob Herring status = "disabled"; 356724ba675SRob Herring }; 357724ba675SRob Herring 358724ba675SRob Herring scifb3: serial@e6cf0000 { 359724ba675SRob Herring compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 360724ba675SRob Herring reg = <0 0xe6cf0000 0 0x100>; 361724ba675SRob Herring interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 362724ba675SRob Herring clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; 363724ba675SRob Herring clock-names = "fck"; 364724ba675SRob Herring power-domains = <&pd_c4>; 365724ba675SRob Herring status = "disabled"; 366724ba675SRob Herring }; 367724ba675SRob Herring 368724ba675SRob Herring sdhi0: mmc@ee100000 { 369724ba675SRob Herring compatible = "renesas,sdhi-r8a73a4"; 370724ba675SRob Herring reg = <0 0xee100000 0 0x100>; 371724ba675SRob Herring interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 372724ba675SRob Herring clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; 373724ba675SRob Herring power-domains = <&pd_a3sp>; 374724ba675SRob Herring cap-sd-highspeed; 375724ba675SRob Herring status = "disabled"; 376724ba675SRob Herring }; 377724ba675SRob Herring 378724ba675SRob Herring sdhi1: mmc@ee120000 { 379724ba675SRob Herring compatible = "renesas,sdhi-r8a73a4"; 380724ba675SRob Herring reg = <0 0xee120000 0 0x100>; 381724ba675SRob Herring interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 382724ba675SRob Herring clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; 383724ba675SRob Herring power-domains = <&pd_a3sp>; 384724ba675SRob Herring cap-sd-highspeed; 385724ba675SRob Herring status = "disabled"; 386724ba675SRob Herring }; 387724ba675SRob Herring 388724ba675SRob Herring sdhi2: mmc@ee140000 { 389724ba675SRob Herring compatible = "renesas,sdhi-r8a73a4"; 390724ba675SRob Herring reg = <0 0xee140000 0 0x100>; 391724ba675SRob Herring interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 392724ba675SRob Herring clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; 393724ba675SRob Herring power-domains = <&pd_a3sp>; 394724ba675SRob Herring cap-sd-highspeed; 395724ba675SRob Herring status = "disabled"; 396724ba675SRob Herring }; 397724ba675SRob Herring 398724ba675SRob Herring mmcif0: mmc@ee200000 { 399724ba675SRob Herring compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; 400724ba675SRob Herring reg = <0 0xee200000 0 0x80>; 401724ba675SRob Herring interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 402724ba675SRob Herring clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; 403724ba675SRob Herring power-domains = <&pd_a3sp>; 404724ba675SRob Herring reg-io-width = <4>; 405724ba675SRob Herring status = "disabled"; 406724ba675SRob Herring }; 407724ba675SRob Herring 408724ba675SRob Herring mmcif1: mmc@ee220000 { 409724ba675SRob Herring compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; 410724ba675SRob Herring reg = <0 0xee220000 0 0x80>; 411724ba675SRob Herring interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 412724ba675SRob Herring clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; 413724ba675SRob Herring power-domains = <&pd_a3sp>; 414724ba675SRob Herring reg-io-width = <4>; 415724ba675SRob Herring status = "disabled"; 416724ba675SRob Herring }; 417724ba675SRob Herring 418724ba675SRob Herring gic: interrupt-controller@f1001000 { 419724ba675SRob Herring compatible = "arm,gic-400"; 420724ba675SRob Herring #interrupt-cells = <3>; 421724ba675SRob Herring #address-cells = <0>; 422724ba675SRob Herring interrupt-controller; 423724ba675SRob Herring reg = <0 0xf1001000 0 0x1000>, 424724ba675SRob Herring <0 0xf1002000 0 0x2000>, 425724ba675SRob Herring <0 0xf1004000 0 0x2000>, 426724ba675SRob Herring <0 0xf1006000 0 0x2000>; 427724ba675SRob Herring interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 428724ba675SRob Herring clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>; 429724ba675SRob Herring clock-names = "clk"; 430724ba675SRob Herring power-domains = <&pd_c4>; 431724ba675SRob Herring }; 432724ba675SRob Herring 433724ba675SRob Herring bsc: bus@fec10000 { 434724ba675SRob Herring compatible = "renesas,bsc-r8a73a4", "renesas,bsc", 435724ba675SRob Herring "simple-pm-bus"; 436724ba675SRob Herring #address-cells = <1>; 437724ba675SRob Herring #size-cells = <1>; 438724ba675SRob Herring ranges = <0 0 0 0x20000000>; 439724ba675SRob Herring reg = <0 0xfec10000 0 0x400>; 440724ba675SRob Herring clocks = <&zb_clk>; 441724ba675SRob Herring power-domains = <&pd_c4>; 442724ba675SRob Herring }; 443724ba675SRob Herring 444724ba675SRob Herring clocks { 445724ba675SRob Herring #address-cells = <2>; 446724ba675SRob Herring #size-cells = <2>; 447724ba675SRob Herring ranges; 448724ba675SRob Herring 449724ba675SRob Herring /* External root clocks */ 450724ba675SRob Herring extalr_clk: extalr { 451724ba675SRob Herring compatible = "fixed-clock"; 452724ba675SRob Herring #clock-cells = <0>; 453*6d4a320eSGeert Uytterhoeven /* This value must be overridden by the board. */ 454*6d4a320eSGeert Uytterhoeven clock-frequency = <0>; 455724ba675SRob Herring }; 456724ba675SRob Herring extal1_clk: extal1 { 457724ba675SRob Herring compatible = "fixed-clock"; 458724ba675SRob Herring #clock-cells = <0>; 459*6d4a320eSGeert Uytterhoeven /* This value must be overridden by the board. */ 460*6d4a320eSGeert Uytterhoeven clock-frequency = <0>; 461724ba675SRob Herring }; 462724ba675SRob Herring extal2_clk: extal2 { 463724ba675SRob Herring compatible = "fixed-clock"; 464724ba675SRob Herring #clock-cells = <0>; 465*6d4a320eSGeert Uytterhoeven /* This value must be overridden by the board. */ 466*6d4a320eSGeert Uytterhoeven clock-frequency = <0>; 467724ba675SRob Herring }; 468724ba675SRob Herring fsiack_clk: fsiack { 469724ba675SRob Herring compatible = "fixed-clock"; 470724ba675SRob Herring #clock-cells = <0>; 471724ba675SRob Herring /* This value must be overridden by the board. */ 472724ba675SRob Herring clock-frequency = <0>; 473724ba675SRob Herring }; 474724ba675SRob Herring fsibck_clk: fsibck { 475724ba675SRob Herring compatible = "fixed-clock"; 476724ba675SRob Herring #clock-cells = <0>; 477724ba675SRob Herring /* This value must be overridden by the board. */ 478724ba675SRob Herring clock-frequency = <0>; 479724ba675SRob Herring }; 480724ba675SRob Herring 481724ba675SRob Herring /* Special CPG clocks */ 482724ba675SRob Herring cpg_clocks: cpg_clocks@e6150000 { 483724ba675SRob Herring compatible = "renesas,r8a73a4-cpg-clocks"; 484724ba675SRob Herring reg = <0 0xe6150000 0 0x10000>; 485724ba675SRob Herring clocks = <&extal1_clk>, <&extal2_clk>; 486724ba675SRob Herring #clock-cells = <1>; 487724ba675SRob Herring clock-output-names = "main", "pll0", "pll1", "pll2", 488724ba675SRob Herring "pll2s", "pll2h", "z", "z2", 489724ba675SRob Herring "i", "m3", "b", "m1", "m2", 490724ba675SRob Herring "zx", "zs", "hp"; 491724ba675SRob Herring }; 492724ba675SRob Herring 493724ba675SRob Herring /* Variable factor clocks (DIV6) */ 494724ba675SRob Herring zb_clk: zb_clk@e6150010 { 495724ba675SRob Herring compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 496724ba675SRob Herring reg = <0 0xe6150010 0 4>; 497724ba675SRob Herring clocks = <&pll1_div2_clk>, <0>, 498724ba675SRob Herring <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; 499724ba675SRob Herring #clock-cells = <0>; 500724ba675SRob Herring clock-output-names = "zb"; 501724ba675SRob Herring }; 502724ba675SRob Herring sdhi0_clk: sdhi0ck@e6150074 { 503724ba675SRob Herring compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 504724ba675SRob Herring reg = <0 0xe6150074 0 4>; 505724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 506724ba675SRob Herring <0>, <&extal2_clk>; 507724ba675SRob Herring #clock-cells = <0>; 508724ba675SRob Herring }; 509724ba675SRob Herring sdhi1_clk: sdhi1ck@e6150078 { 510724ba675SRob Herring compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 511724ba675SRob Herring reg = <0 0xe6150078 0 4>; 512724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 513724ba675SRob Herring <0>, <&extal2_clk>; 514724ba675SRob Herring #clock-cells = <0>; 515724ba675SRob Herring }; 516724ba675SRob Herring sdhi2_clk: sdhi2ck@e615007c { 517724ba675SRob Herring compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 518724ba675SRob Herring reg = <0 0xe615007c 0 4>; 519724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 520724ba675SRob Herring <0>, <&extal2_clk>; 521724ba675SRob Herring #clock-cells = <0>; 522724ba675SRob Herring }; 523724ba675SRob Herring mmc0_clk: mmc0@e6150240 { 524724ba675SRob Herring compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 525724ba675SRob Herring reg = <0 0xe6150240 0 4>; 526724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 527724ba675SRob Herring <0>, <&extal2_clk>; 528724ba675SRob Herring #clock-cells = <0>; 529724ba675SRob Herring }; 530724ba675SRob Herring mmc1_clk: mmc1@e6150244 { 531724ba675SRob Herring compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 532724ba675SRob Herring reg = <0 0xe6150244 0 4>; 533724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 534724ba675SRob Herring <0>, <&extal2_clk>; 535724ba675SRob Herring #clock-cells = <0>; 536724ba675SRob Herring }; 537724ba675SRob Herring vclk1_clk: vclk1@e6150008 { 538724ba675SRob Herring compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 539724ba675SRob Herring reg = <0 0xe6150008 0 4>; 540724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 541724ba675SRob Herring <0>, <&extal2_clk>, <&main_div2_clk>, 542724ba675SRob Herring <&extalr_clk>, <0>, <0>; 543724ba675SRob Herring #clock-cells = <0>; 544724ba675SRob Herring }; 545724ba675SRob Herring vclk2_clk: vclk2@e615000c { 546724ba675SRob Herring compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 547724ba675SRob Herring reg = <0 0xe615000c 0 4>; 548724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 549724ba675SRob Herring <0>, <&extal2_clk>, <&main_div2_clk>, 550724ba675SRob Herring <&extalr_clk>, <0>, <0>; 551724ba675SRob Herring #clock-cells = <0>; 552724ba675SRob Herring }; 553724ba675SRob Herring vclk3_clk: vclk3@e615001c { 554724ba675SRob Herring compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 555724ba675SRob Herring reg = <0 0xe615001c 0 4>; 556724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 557724ba675SRob Herring <0>, <&extal2_clk>, <&main_div2_clk>, 558724ba675SRob Herring <&extalr_clk>, <0>, <0>; 559724ba675SRob Herring #clock-cells = <0>; 560724ba675SRob Herring }; 561724ba675SRob Herring vclk4_clk: vclk4@e6150014 { 562724ba675SRob Herring compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 563724ba675SRob Herring reg = <0 0xe6150014 0 4>; 564724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 565724ba675SRob Herring <0>, <&extal2_clk>, <&main_div2_clk>, 566724ba675SRob Herring <&extalr_clk>, <0>, <0>; 567724ba675SRob Herring #clock-cells = <0>; 568724ba675SRob Herring }; 569724ba675SRob Herring vclk5_clk: vclk5@e6150034 { 570724ba675SRob Herring compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 571724ba675SRob Herring reg = <0 0xe6150034 0 4>; 572724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 573724ba675SRob Herring <0>, <&extal2_clk>, <&main_div2_clk>, 574724ba675SRob Herring <&extalr_clk>, <0>, <0>; 575724ba675SRob Herring #clock-cells = <0>; 576724ba675SRob Herring }; 577724ba675SRob Herring fsia_clk: fsia@e6150018 { 578724ba675SRob Herring compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 579724ba675SRob Herring reg = <0 0xe6150018 0 4>; 580724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 581724ba675SRob Herring <&fsiack_clk>, <0>; 582724ba675SRob Herring #clock-cells = <0>; 583724ba675SRob Herring }; 584724ba675SRob Herring fsib_clk: fsib@e6150090 { 585724ba675SRob Herring compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 586724ba675SRob Herring reg = <0 0xe6150090 0 4>; 587724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 588724ba675SRob Herring <&fsibck_clk>, <0>; 589724ba675SRob Herring #clock-cells = <0>; 590724ba675SRob Herring }; 591724ba675SRob Herring mp_clk: mp@e6150080 { 592724ba675SRob Herring compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 593724ba675SRob Herring reg = <0 0xe6150080 0 4>; 594724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 595724ba675SRob Herring <&extal2_clk>, <&extal2_clk>; 596724ba675SRob Herring #clock-cells = <0>; 597724ba675SRob Herring }; 598724ba675SRob Herring m4_clk: m4@e6150098 { 599724ba675SRob Herring compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 600724ba675SRob Herring reg = <0 0xe6150098 0 4>; 601724ba675SRob Herring clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; 602724ba675SRob Herring #clock-cells = <0>; 603724ba675SRob Herring }; 604724ba675SRob Herring hsi_clk: hsi@e615026c { 605724ba675SRob Herring compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 606724ba675SRob Herring reg = <0 0xe615026c 0 4>; 607724ba675SRob Herring clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, 608724ba675SRob Herring <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; 609724ba675SRob Herring #clock-cells = <0>; 610724ba675SRob Herring }; 611724ba675SRob Herring spuv_clk: spuv@e6150094 { 612724ba675SRob Herring compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 613724ba675SRob Herring reg = <0 0xe6150094 0 4>; 614724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 615724ba675SRob Herring <&extal2_clk>, <&extal2_clk>; 616724ba675SRob Herring #clock-cells = <0>; 617724ba675SRob Herring }; 618724ba675SRob Herring 619724ba675SRob Herring /* Fixed factor clocks */ 620724ba675SRob Herring main_div2_clk: main_div2 { 621724ba675SRob Herring compatible = "fixed-factor-clock"; 622724ba675SRob Herring clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; 623724ba675SRob Herring #clock-cells = <0>; 624724ba675SRob Herring clock-div = <2>; 625724ba675SRob Herring clock-mult = <1>; 626724ba675SRob Herring }; 627724ba675SRob Herring pll0_div2_clk: pll0_div2 { 628724ba675SRob Herring compatible = "fixed-factor-clock"; 629724ba675SRob Herring clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; 630724ba675SRob Herring #clock-cells = <0>; 631724ba675SRob Herring clock-div = <2>; 632724ba675SRob Herring clock-mult = <1>; 633724ba675SRob Herring }; 634724ba675SRob Herring pll1_div2_clk: pll1_div2 { 635724ba675SRob Herring compatible = "fixed-factor-clock"; 636724ba675SRob Herring clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; 637724ba675SRob Herring #clock-cells = <0>; 638724ba675SRob Herring clock-div = <2>; 639724ba675SRob Herring clock-mult = <1>; 640724ba675SRob Herring }; 641724ba675SRob Herring extal1_div2_clk: extal1_div2 { 642724ba675SRob Herring compatible = "fixed-factor-clock"; 643724ba675SRob Herring clocks = <&extal1_clk>; 644724ba675SRob Herring #clock-cells = <0>; 645724ba675SRob Herring clock-div = <2>; 646724ba675SRob Herring clock-mult = <1>; 647724ba675SRob Herring }; 648724ba675SRob Herring 649724ba675SRob Herring /* Gate clocks */ 650724ba675SRob Herring mstp2_clks: mstp2_clks@e6150138 { 651724ba675SRob Herring compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 652724ba675SRob Herring reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; 653724ba675SRob Herring clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, 654724ba675SRob Herring <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; 655724ba675SRob Herring #clock-cells = <1>; 656724ba675SRob Herring clock-indices = < 657724ba675SRob Herring R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 658724ba675SRob Herring R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 659724ba675SRob Herring R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 660724ba675SRob Herring R8A73A4_CLK_DMAC 661724ba675SRob Herring >; 662724ba675SRob Herring clock-output-names = 663724ba675SRob Herring "scifa0", "scifa1", "scifb0", "scifb1", 664724ba675SRob Herring "scifb2", "scifb3", "dmac"; 665724ba675SRob Herring }; 666724ba675SRob Herring mstp3_clks: mstp3_clks@e615013c { 667724ba675SRob Herring compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 668724ba675SRob Herring reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 669724ba675SRob Herring clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>, 670724ba675SRob Herring <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>, 671724ba675SRob Herring <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>, 672724ba675SRob Herring <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks 673724ba675SRob Herring R8A73A4_CLK_HP>, <&cpg_clocks 674724ba675SRob Herring R8A73A4_CLK_HP>, <&extalr_clk>; 675724ba675SRob Herring #clock-cells = <1>; 676724ba675SRob Herring clock-indices = < 677724ba675SRob Herring R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1 678724ba675SRob Herring R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1 679724ba675SRob Herring R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0 680724ba675SRob Herring R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7 681724ba675SRob Herring R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1 682724ba675SRob Herring R8A73A4_CLK_CMT1 683724ba675SRob Herring >; 684724ba675SRob Herring clock-output-names = 685724ba675SRob Herring "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0", 686724ba675SRob Herring "mmcif0", "iic6", "iic7", "iic0", "iic1", 687724ba675SRob Herring "cmt1"; 688724ba675SRob Herring }; 689724ba675SRob Herring mstp4_clks: mstp4_clks@e6150140 { 690724ba675SRob Herring compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 691724ba675SRob Herring reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; 692724ba675SRob Herring clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, 693724ba675SRob Herring <&main_div2_clk>, 694724ba675SRob Herring <&cpg_clocks R8A73A4_CLK_HP>, 695724ba675SRob Herring <&cpg_clocks R8A73A4_CLK_HP>; 696724ba675SRob Herring #clock-cells = <1>; 697724ba675SRob Herring clock-indices = < 698724ba675SRob Herring R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS 699724ba675SRob Herring R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4 700724ba675SRob Herring R8A73A4_CLK_IIC3 701724ba675SRob Herring >; 702724ba675SRob Herring clock-output-names = 703724ba675SRob Herring "irqc", "intc-sys", "iic5", "iic4", "iic3"; 704724ba675SRob Herring }; 705724ba675SRob Herring mstp5_clks: mstp5_clks@e6150144 { 706724ba675SRob Herring compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 707724ba675SRob Herring reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 708724ba675SRob Herring clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; 709724ba675SRob Herring #clock-cells = <1>; 710724ba675SRob Herring clock-indices = < 711724ba675SRob Herring R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 712724ba675SRob Herring >; 713724ba675SRob Herring clock-output-names = 714724ba675SRob Herring "thermal", "iic8"; 715724ba675SRob Herring }; 716724ba675SRob Herring }; 717724ba675SRob Herring 718724ba675SRob Herring prr: chipid@ff000044 { 719724ba675SRob Herring compatible = "renesas,prr"; 720724ba675SRob Herring reg = <0 0xff000044 0 4>; 721724ba675SRob Herring }; 722724ba675SRob Herring 723724ba675SRob Herring sysc: system-controller@e6180000 { 724724ba675SRob Herring compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile"; 725724ba675SRob Herring reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>; 726724ba675SRob Herring 727724ba675SRob Herring pm-domains { 728724ba675SRob Herring pd_c5: c5 { 729724ba675SRob Herring #address-cells = <1>; 730724ba675SRob Herring #size-cells = <0>; 731724ba675SRob Herring #power-domain-cells = <0>; 732724ba675SRob Herring 733724ba675SRob Herring pd_c4: c4@0 { 734724ba675SRob Herring reg = <0>; 735724ba675SRob Herring #address-cells = <1>; 736724ba675SRob Herring #size-cells = <0>; 737724ba675SRob Herring #power-domain-cells = <0>; 738724ba675SRob Herring 739724ba675SRob Herring pd_a3sg: a3sg@16 { 740724ba675SRob Herring reg = <16>; 741724ba675SRob Herring #power-domain-cells = <0>; 742724ba675SRob Herring }; 743724ba675SRob Herring 744724ba675SRob Herring pd_a3ex: a3ex@17 { 745724ba675SRob Herring reg = <17>; 746724ba675SRob Herring #power-domain-cells = <0>; 747724ba675SRob Herring }; 748724ba675SRob Herring 749724ba675SRob Herring pd_a3sp: a3sp@18 { 750724ba675SRob Herring reg = <18>; 751724ba675SRob Herring #address-cells = <1>; 752724ba675SRob Herring #size-cells = <0>; 753724ba675SRob Herring #power-domain-cells = <0>; 754724ba675SRob Herring 755724ba675SRob Herring pd_a2us: a2us@19 { 756724ba675SRob Herring reg = <19>; 757724ba675SRob Herring #power-domain-cells = <0>; 758724ba675SRob Herring }; 759724ba675SRob Herring }; 760724ba675SRob Herring 761724ba675SRob Herring pd_a3sm: a3sm@20 { 762724ba675SRob Herring reg = <20>; 763724ba675SRob Herring #address-cells = <1>; 764724ba675SRob Herring #size-cells = <0>; 765724ba675SRob Herring #power-domain-cells = <0>; 766724ba675SRob Herring 767724ba675SRob Herring pd_a2sl: a2sl@21 { 768724ba675SRob Herring reg = <21>; 769724ba675SRob Herring #power-domain-cells = <0>; 770724ba675SRob Herring }; 771724ba675SRob Herring }; 772724ba675SRob Herring 773724ba675SRob Herring pd_a3km: a3km@22 { 774724ba675SRob Herring reg = <22>; 775724ba675SRob Herring #address-cells = <1>; 776724ba675SRob Herring #size-cells = <0>; 777724ba675SRob Herring #power-domain-cells = <0>; 778724ba675SRob Herring 779724ba675SRob Herring pd_a2kl: a2kl@23 { 780724ba675SRob Herring reg = <23>; 781724ba675SRob Herring #power-domain-cells = <0>; 782724ba675SRob Herring }; 783724ba675SRob Herring }; 784724ba675SRob Herring }; 785724ba675SRob Herring 786724ba675SRob Herring pd_c4ma: c4ma@1 { 787724ba675SRob Herring reg = <1>; 788724ba675SRob Herring #power-domain-cells = <0>; 789724ba675SRob Herring }; 790724ba675SRob Herring 791724ba675SRob Herring pd_c4cl: c4cl@2 { 792724ba675SRob Herring reg = <2>; 793724ba675SRob Herring #power-domain-cells = <0>; 794724ba675SRob Herring }; 795724ba675SRob Herring 796724ba675SRob Herring pd_d4: d4@3 { 797724ba675SRob Herring reg = <3>; 798724ba675SRob Herring #power-domain-cells = <0>; 799724ba675SRob Herring }; 800724ba675SRob Herring 801724ba675SRob Herring pd_a4bc: a4bc@4 { 802724ba675SRob Herring reg = <4>; 803724ba675SRob Herring #address-cells = <1>; 804724ba675SRob Herring #size-cells = <0>; 805724ba675SRob Herring #power-domain-cells = <0>; 806724ba675SRob Herring 807724ba675SRob Herring pd_a3bc: a3bc@5 { 808724ba675SRob Herring reg = <5>; 809724ba675SRob Herring #power-domain-cells = <0>; 810724ba675SRob Herring }; 811724ba675SRob Herring }; 812724ba675SRob Herring 813724ba675SRob Herring pd_a4l: a4l@6 { 814724ba675SRob Herring reg = <6>; 815724ba675SRob Herring #power-domain-cells = <0>; 816724ba675SRob Herring }; 817724ba675SRob Herring 818724ba675SRob Herring pd_a4lc: a4lc@7 { 819724ba675SRob Herring reg = <7>; 820724ba675SRob Herring #power-domain-cells = <0>; 821724ba675SRob Herring }; 822724ba675SRob Herring 823724ba675SRob Herring pd_a4mp: a4mp@8 { 824724ba675SRob Herring reg = <8>; 825724ba675SRob Herring #address-cells = <1>; 826724ba675SRob Herring #size-cells = <0>; 827724ba675SRob Herring #power-domain-cells = <0>; 828724ba675SRob Herring 829724ba675SRob Herring pd_a3mp: a3mp@9 { 830724ba675SRob Herring reg = <9>; 831724ba675SRob Herring #power-domain-cells = <0>; 832724ba675SRob Herring }; 833724ba675SRob Herring 834724ba675SRob Herring pd_a3vc: a3vc@10 { 835724ba675SRob Herring reg = <10>; 836724ba675SRob Herring #power-domain-cells = <0>; 837724ba675SRob Herring }; 838724ba675SRob Herring }; 839724ba675SRob Herring 840724ba675SRob Herring pd_a4sf: a4sf@11 { 841724ba675SRob Herring reg = <11>; 842724ba675SRob Herring #power-domain-cells = <0>; 843724ba675SRob Herring }; 844724ba675SRob Herring 845724ba675SRob Herring pd_a3r: a3r@12 { 846724ba675SRob Herring reg = <12>; 847724ba675SRob Herring #address-cells = <1>; 848724ba675SRob Herring #size-cells = <0>; 849724ba675SRob Herring #power-domain-cells = <0>; 850724ba675SRob Herring 851724ba675SRob Herring pd_a2rv: a2rv@13 { 852724ba675SRob Herring reg = <13>; 853724ba675SRob Herring #power-domain-cells = <0>; 854724ba675SRob Herring }; 855724ba675SRob Herring 856724ba675SRob Herring pd_a2is: a2is@14 { 857724ba675SRob Herring reg = <14>; 858724ba675SRob Herring #power-domain-cells = <0>; 859724ba675SRob Herring }; 860724ba675SRob Herring }; 861724ba675SRob Herring }; 862724ba675SRob Herring }; 863724ba675SRob Herring }; 864724ba675SRob Herring}; 865