1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree Source for the r7s72100 SoC 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2013-14 Renesas Solutions Corp. 6*724ba675SRob Herring * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> 7*724ba675SRob Herring */ 8*724ba675SRob Herring 9*724ba675SRob Herring#include <dt-bindings/clock/r7s72100-clock.h> 10*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 11*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 12*724ba675SRob Herring 13*724ba675SRob Herring/ { 14*724ba675SRob Herring compatible = "renesas,r7s72100"; 15*724ba675SRob Herring #address-cells = <1>; 16*724ba675SRob Herring #size-cells = <1>; 17*724ba675SRob Herring 18*724ba675SRob Herring aliases { 19*724ba675SRob Herring i2c0 = &i2c0; 20*724ba675SRob Herring i2c1 = &i2c1; 21*724ba675SRob Herring i2c2 = &i2c2; 22*724ba675SRob Herring i2c3 = &i2c3; 23*724ba675SRob Herring spi0 = &spi0; 24*724ba675SRob Herring spi1 = &spi1; 25*724ba675SRob Herring spi2 = &spi2; 26*724ba675SRob Herring spi3 = &spi3; 27*724ba675SRob Herring spi4 = &spi4; 28*724ba675SRob Herring }; 29*724ba675SRob Herring 30*724ba675SRob Herring /* Fixed factor clocks */ 31*724ba675SRob Herring b_clk: b { 32*724ba675SRob Herring #clock-cells = <0>; 33*724ba675SRob Herring compatible = "fixed-factor-clock"; 34*724ba675SRob Herring clocks = <&cpg_clocks R7S72100_CLK_PLL>; 35*724ba675SRob Herring clock-mult = <1>; 36*724ba675SRob Herring clock-div = <3>; 37*724ba675SRob Herring }; 38*724ba675SRob Herring 39*724ba675SRob Herring cpus { 40*724ba675SRob Herring #address-cells = <1>; 41*724ba675SRob Herring #size-cells = <0>; 42*724ba675SRob Herring 43*724ba675SRob Herring cpu@0 { 44*724ba675SRob Herring device_type = "cpu"; 45*724ba675SRob Herring compatible = "arm,cortex-a9"; 46*724ba675SRob Herring reg = <0>; 47*724ba675SRob Herring clock-frequency = <400000000>; 48*724ba675SRob Herring clocks = <&cpg_clocks R7S72100_CLK_I>; 49*724ba675SRob Herring next-level-cache = <&L2>; 50*724ba675SRob Herring }; 51*724ba675SRob Herring }; 52*724ba675SRob Herring 53*724ba675SRob Herring /* External clocks */ 54*724ba675SRob Herring extal_clk: extal { 55*724ba675SRob Herring #clock-cells = <0>; 56*724ba675SRob Herring compatible = "fixed-clock"; 57*724ba675SRob Herring /* If clk present, value must be set by board */ 58*724ba675SRob Herring clock-frequency = <0>; 59*724ba675SRob Herring }; 60*724ba675SRob Herring 61*724ba675SRob Herring p0_clk: p0 { 62*724ba675SRob Herring #clock-cells = <0>; 63*724ba675SRob Herring compatible = "fixed-factor-clock"; 64*724ba675SRob Herring clocks = <&cpg_clocks R7S72100_CLK_PLL>; 65*724ba675SRob Herring clock-mult = <1>; 66*724ba675SRob Herring clock-div = <12>; 67*724ba675SRob Herring }; 68*724ba675SRob Herring 69*724ba675SRob Herring p1_clk: p1 { 70*724ba675SRob Herring #clock-cells = <0>; 71*724ba675SRob Herring compatible = "fixed-factor-clock"; 72*724ba675SRob Herring clocks = <&cpg_clocks R7S72100_CLK_PLL>; 73*724ba675SRob Herring clock-mult = <1>; 74*724ba675SRob Herring clock-div = <6>; 75*724ba675SRob Herring }; 76*724ba675SRob Herring 77*724ba675SRob Herring pmu { 78*724ba675SRob Herring compatible = "arm,cortex-a9-pmu"; 79*724ba675SRob Herring interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; 80*724ba675SRob Herring }; 81*724ba675SRob Herring 82*724ba675SRob Herring rtc_x1_clk: rtc_x1 { 83*724ba675SRob Herring #clock-cells = <0>; 84*724ba675SRob Herring compatible = "fixed-clock"; 85*724ba675SRob Herring /* If clk present, value must be set by board to 32678 */ 86*724ba675SRob Herring clock-frequency = <0>; 87*724ba675SRob Herring }; 88*724ba675SRob Herring 89*724ba675SRob Herring rtc_x3_clk: rtc_x3 { 90*724ba675SRob Herring #clock-cells = <0>; 91*724ba675SRob Herring compatible = "fixed-clock"; 92*724ba675SRob Herring /* If clk present, value must be set by board to 4000000 */ 93*724ba675SRob Herring clock-frequency = <0>; 94*724ba675SRob Herring }; 95*724ba675SRob Herring 96*724ba675SRob Herring soc { 97*724ba675SRob Herring compatible = "simple-bus"; 98*724ba675SRob Herring interrupt-parent = <&gic>; 99*724ba675SRob Herring 100*724ba675SRob Herring #address-cells = <1>; 101*724ba675SRob Herring #size-cells = <1>; 102*724ba675SRob Herring ranges; 103*724ba675SRob Herring 104*724ba675SRob Herring L2: cache-controller@3ffff000 { 105*724ba675SRob Herring compatible = "arm,pl310-cache"; 106*724ba675SRob Herring reg = <0x3ffff000 0x1000>; 107*724ba675SRob Herring interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 108*724ba675SRob Herring arm,early-bresp-disable; 109*724ba675SRob Herring arm,full-line-zero-disable; 110*724ba675SRob Herring cache-unified; 111*724ba675SRob Herring cache-level = <2>; 112*724ba675SRob Herring }; 113*724ba675SRob Herring 114*724ba675SRob Herring scif0: serial@e8007000 { 115*724ba675SRob Herring compatible = "renesas,scif-r7s72100", "renesas,scif"; 116*724ba675SRob Herring reg = <0xe8007000 64>; 117*724ba675SRob Herring interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 118*724ba675SRob Herring <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 119*724ba675SRob Herring <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 120*724ba675SRob Herring <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 121*724ba675SRob Herring clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; 122*724ba675SRob Herring clock-names = "fck"; 123*724ba675SRob Herring power-domains = <&cpg_clocks>; 124*724ba675SRob Herring status = "disabled"; 125*724ba675SRob Herring }; 126*724ba675SRob Herring 127*724ba675SRob Herring scif1: serial@e8007800 { 128*724ba675SRob Herring compatible = "renesas,scif-r7s72100", "renesas,scif"; 129*724ba675SRob Herring reg = <0xe8007800 64>; 130*724ba675SRob Herring interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 131*724ba675SRob Herring <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 132*724ba675SRob Herring <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 133*724ba675SRob Herring <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 134*724ba675SRob Herring clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; 135*724ba675SRob Herring clock-names = "fck"; 136*724ba675SRob Herring power-domains = <&cpg_clocks>; 137*724ba675SRob Herring status = "disabled"; 138*724ba675SRob Herring }; 139*724ba675SRob Herring 140*724ba675SRob Herring scif2: serial@e8008000 { 141*724ba675SRob Herring compatible = "renesas,scif-r7s72100", "renesas,scif"; 142*724ba675SRob Herring reg = <0xe8008000 64>; 143*724ba675SRob Herring interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 144*724ba675SRob Herring <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 145*724ba675SRob Herring <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 146*724ba675SRob Herring <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 147*724ba675SRob Herring clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; 148*724ba675SRob Herring clock-names = "fck"; 149*724ba675SRob Herring power-domains = <&cpg_clocks>; 150*724ba675SRob Herring status = "disabled"; 151*724ba675SRob Herring }; 152*724ba675SRob Herring 153*724ba675SRob Herring scif3: serial@e8008800 { 154*724ba675SRob Herring compatible = "renesas,scif-r7s72100", "renesas,scif"; 155*724ba675SRob Herring reg = <0xe8008800 64>; 156*724ba675SRob Herring interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 157*724ba675SRob Herring <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 158*724ba675SRob Herring <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 159*724ba675SRob Herring <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 160*724ba675SRob Herring clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; 161*724ba675SRob Herring clock-names = "fck"; 162*724ba675SRob Herring power-domains = <&cpg_clocks>; 163*724ba675SRob Herring status = "disabled"; 164*724ba675SRob Herring }; 165*724ba675SRob Herring 166*724ba675SRob Herring scif4: serial@e8009000 { 167*724ba675SRob Herring compatible = "renesas,scif-r7s72100", "renesas,scif"; 168*724ba675SRob Herring reg = <0xe8009000 64>; 169*724ba675SRob Herring interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 170*724ba675SRob Herring <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 171*724ba675SRob Herring <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 172*724ba675SRob Herring <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 173*724ba675SRob Herring clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; 174*724ba675SRob Herring clock-names = "fck"; 175*724ba675SRob Herring power-domains = <&cpg_clocks>; 176*724ba675SRob Herring status = "disabled"; 177*724ba675SRob Herring }; 178*724ba675SRob Herring 179*724ba675SRob Herring scif5: serial@e8009800 { 180*724ba675SRob Herring compatible = "renesas,scif-r7s72100", "renesas,scif"; 181*724ba675SRob Herring reg = <0xe8009800 64>; 182*724ba675SRob Herring interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 183*724ba675SRob Herring <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 184*724ba675SRob Herring <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 185*724ba675SRob Herring <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 186*724ba675SRob Herring clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; 187*724ba675SRob Herring clock-names = "fck"; 188*724ba675SRob Herring power-domains = <&cpg_clocks>; 189*724ba675SRob Herring status = "disabled"; 190*724ba675SRob Herring }; 191*724ba675SRob Herring 192*724ba675SRob Herring scif6: serial@e800a000 { 193*724ba675SRob Herring compatible = "renesas,scif-r7s72100", "renesas,scif"; 194*724ba675SRob Herring reg = <0xe800a000 64>; 195*724ba675SRob Herring interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 196*724ba675SRob Herring <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 197*724ba675SRob Herring <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 198*724ba675SRob Herring <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 199*724ba675SRob Herring clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; 200*724ba675SRob Herring clock-names = "fck"; 201*724ba675SRob Herring power-domains = <&cpg_clocks>; 202*724ba675SRob Herring status = "disabled"; 203*724ba675SRob Herring }; 204*724ba675SRob Herring 205*724ba675SRob Herring scif7: serial@e800a800 { 206*724ba675SRob Herring compatible = "renesas,scif-r7s72100", "renesas,scif"; 207*724ba675SRob Herring reg = <0xe800a800 64>; 208*724ba675SRob Herring interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 209*724ba675SRob Herring <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 210*724ba675SRob Herring <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 211*724ba675SRob Herring <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 212*724ba675SRob Herring clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; 213*724ba675SRob Herring clock-names = "fck"; 214*724ba675SRob Herring power-domains = <&cpg_clocks>; 215*724ba675SRob Herring status = "disabled"; 216*724ba675SRob Herring }; 217*724ba675SRob Herring 218*724ba675SRob Herring spi0: spi@e800c800 { 219*724ba675SRob Herring compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 220*724ba675SRob Herring reg = <0xe800c800 0x24>; 221*724ba675SRob Herring interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 222*724ba675SRob Herring <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 223*724ba675SRob Herring <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 224*724ba675SRob Herring interrupt-names = "error", "rx", "tx"; 225*724ba675SRob Herring clocks = <&mstp10_clks R7S72100_CLK_SPI0>; 226*724ba675SRob Herring power-domains = <&cpg_clocks>; 227*724ba675SRob Herring num-cs = <1>; 228*724ba675SRob Herring #address-cells = <1>; 229*724ba675SRob Herring #size-cells = <0>; 230*724ba675SRob Herring status = "disabled"; 231*724ba675SRob Herring }; 232*724ba675SRob Herring 233*724ba675SRob Herring spi1: spi@e800d000 { 234*724ba675SRob Herring compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 235*724ba675SRob Herring reg = <0xe800d000 0x24>; 236*724ba675SRob Herring interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 237*724ba675SRob Herring <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 238*724ba675SRob Herring <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 239*724ba675SRob Herring interrupt-names = "error", "rx", "tx"; 240*724ba675SRob Herring clocks = <&mstp10_clks R7S72100_CLK_SPI1>; 241*724ba675SRob Herring power-domains = <&cpg_clocks>; 242*724ba675SRob Herring num-cs = <1>; 243*724ba675SRob Herring #address-cells = <1>; 244*724ba675SRob Herring #size-cells = <0>; 245*724ba675SRob Herring status = "disabled"; 246*724ba675SRob Herring }; 247*724ba675SRob Herring 248*724ba675SRob Herring spi2: spi@e800d800 { 249*724ba675SRob Herring compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 250*724ba675SRob Herring reg = <0xe800d800 0x24>; 251*724ba675SRob Herring interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 252*724ba675SRob Herring <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 253*724ba675SRob Herring <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 254*724ba675SRob Herring interrupt-names = "error", "rx", "tx"; 255*724ba675SRob Herring clocks = <&mstp10_clks R7S72100_CLK_SPI2>; 256*724ba675SRob Herring power-domains = <&cpg_clocks>; 257*724ba675SRob Herring num-cs = <1>; 258*724ba675SRob Herring #address-cells = <1>; 259*724ba675SRob Herring #size-cells = <0>; 260*724ba675SRob Herring status = "disabled"; 261*724ba675SRob Herring }; 262*724ba675SRob Herring 263*724ba675SRob Herring spi3: spi@e800e000 { 264*724ba675SRob Herring compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 265*724ba675SRob Herring reg = <0xe800e000 0x24>; 266*724ba675SRob Herring interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 267*724ba675SRob Herring <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 268*724ba675SRob Herring <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 269*724ba675SRob Herring interrupt-names = "error", "rx", "tx"; 270*724ba675SRob Herring clocks = <&mstp10_clks R7S72100_CLK_SPI3>; 271*724ba675SRob Herring power-domains = <&cpg_clocks>; 272*724ba675SRob Herring num-cs = <1>; 273*724ba675SRob Herring #address-cells = <1>; 274*724ba675SRob Herring #size-cells = <0>; 275*724ba675SRob Herring status = "disabled"; 276*724ba675SRob Herring }; 277*724ba675SRob Herring 278*724ba675SRob Herring spi4: spi@e800e800 { 279*724ba675SRob Herring compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 280*724ba675SRob Herring reg = <0xe800e800 0x24>; 281*724ba675SRob Herring interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 282*724ba675SRob Herring <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 283*724ba675SRob Herring <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 284*724ba675SRob Herring interrupt-names = "error", "rx", "tx"; 285*724ba675SRob Herring clocks = <&mstp10_clks R7S72100_CLK_SPI4>; 286*724ba675SRob Herring power-domains = <&cpg_clocks>; 287*724ba675SRob Herring num-cs = <1>; 288*724ba675SRob Herring #address-cells = <1>; 289*724ba675SRob Herring #size-cells = <0>; 290*724ba675SRob Herring status = "disabled"; 291*724ba675SRob Herring }; 292*724ba675SRob Herring 293*724ba675SRob Herring usbhs0: usb@e8010000 { 294*724ba675SRob Herring compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; 295*724ba675SRob Herring reg = <0xe8010000 0x1a0>; 296*724ba675SRob Herring interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 297*724ba675SRob Herring clocks = <&mstp7_clks R7S72100_CLK_USB0>; 298*724ba675SRob Herring renesas,buswait = <4>; 299*724ba675SRob Herring power-domains = <&cpg_clocks>; 300*724ba675SRob Herring status = "disabled"; 301*724ba675SRob Herring }; 302*724ba675SRob Herring 303*724ba675SRob Herring usbhs1: usb@e8207000 { 304*724ba675SRob Herring compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; 305*724ba675SRob Herring reg = <0xe8207000 0x1a0>; 306*724ba675SRob Herring interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 307*724ba675SRob Herring clocks = <&mstp7_clks R7S72100_CLK_USB1>; 308*724ba675SRob Herring renesas,buswait = <4>; 309*724ba675SRob Herring power-domains = <&cpg_clocks>; 310*724ba675SRob Herring status = "disabled"; 311*724ba675SRob Herring }; 312*724ba675SRob Herring 313*724ba675SRob Herring mmcif: mmc@e804c800 { 314*724ba675SRob Herring compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif"; 315*724ba675SRob Herring reg = <0xe804c800 0x80>; 316*724ba675SRob Herring interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 317*724ba675SRob Herring <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 318*724ba675SRob Herring <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 319*724ba675SRob Herring clocks = <&mstp8_clks R7S72100_CLK_MMCIF>; 320*724ba675SRob Herring power-domains = <&cpg_clocks>; 321*724ba675SRob Herring reg-io-width = <4>; 322*724ba675SRob Herring bus-width = <8>; 323*724ba675SRob Herring status = "disabled"; 324*724ba675SRob Herring }; 325*724ba675SRob Herring 326*724ba675SRob Herring sdhi0: mmc@e804e000 { 327*724ba675SRob Herring compatible = "renesas,sdhi-r7s72100"; 328*724ba675SRob Herring reg = <0xe804e000 0x100>; 329*724ba675SRob Herring interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 330*724ba675SRob Herring <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 331*724ba675SRob Herring <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 332*724ba675SRob Herring 333*724ba675SRob Herring clocks = <&mstp12_clks R7S72100_CLK_SDHI00>, 334*724ba675SRob Herring <&mstp12_clks R7S72100_CLK_SDHI01>; 335*724ba675SRob Herring clock-names = "core", "cd"; 336*724ba675SRob Herring power-domains = <&cpg_clocks>; 337*724ba675SRob Herring cap-sd-highspeed; 338*724ba675SRob Herring cap-sdio-irq; 339*724ba675SRob Herring status = "disabled"; 340*724ba675SRob Herring }; 341*724ba675SRob Herring 342*724ba675SRob Herring sdhi1: mmc@e804e800 { 343*724ba675SRob Herring compatible = "renesas,sdhi-r7s72100"; 344*724ba675SRob Herring reg = <0xe804e800 0x100>; 345*724ba675SRob Herring interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 346*724ba675SRob Herring <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 347*724ba675SRob Herring <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; 348*724ba675SRob Herring 349*724ba675SRob Herring clocks = <&mstp12_clks R7S72100_CLK_SDHI10>, 350*724ba675SRob Herring <&mstp12_clks R7S72100_CLK_SDHI11>; 351*724ba675SRob Herring clock-names = "core", "cd"; 352*724ba675SRob Herring power-domains = <&cpg_clocks>; 353*724ba675SRob Herring cap-sd-highspeed; 354*724ba675SRob Herring cap-sdio-irq; 355*724ba675SRob Herring status = "disabled"; 356*724ba675SRob Herring }; 357*724ba675SRob Herring 358*724ba675SRob Herring gic: interrupt-controller@e8201000 { 359*724ba675SRob Herring compatible = "arm,pl390"; 360*724ba675SRob Herring #interrupt-cells = <3>; 361*724ba675SRob Herring #address-cells = <0>; 362*724ba675SRob Herring interrupt-controller; 363*724ba675SRob Herring reg = <0xe8201000 0x1000>, 364*724ba675SRob Herring <0xe8202000 0x1000>; 365*724ba675SRob Herring }; 366*724ba675SRob Herring 367*724ba675SRob Herring ether: ethernet@e8203000 { 368*724ba675SRob Herring compatible = "renesas,ether-r7s72100"; 369*724ba675SRob Herring reg = <0xe8203000 0x800>, 370*724ba675SRob Herring <0xe8204800 0x200>; 371*724ba675SRob Herring interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 372*724ba675SRob Herring clocks = <&mstp7_clks R7S72100_CLK_ETHER>; 373*724ba675SRob Herring power-domains = <&cpg_clocks>; 374*724ba675SRob Herring phy-mode = "mii"; 375*724ba675SRob Herring #address-cells = <1>; 376*724ba675SRob Herring #size-cells = <0>; 377*724ba675SRob Herring status = "disabled"; 378*724ba675SRob Herring }; 379*724ba675SRob Herring 380*724ba675SRob Herring ceu: camera@e8210000 { 381*724ba675SRob Herring reg = <0xe8210000 0x3000>; 382*724ba675SRob Herring compatible = "renesas,r7s72100-ceu"; 383*724ba675SRob Herring interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 384*724ba675SRob Herring clocks = <&mstp6_clks R7S72100_CLK_CEU>; 385*724ba675SRob Herring power-domains = <&cpg_clocks>; 386*724ba675SRob Herring status = "disabled"; 387*724ba675SRob Herring }; 388*724ba675SRob Herring 389*724ba675SRob Herring wdt: watchdog@fcfe0000 { 390*724ba675SRob Herring compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt"; 391*724ba675SRob Herring reg = <0xfcfe0000 0x6>; 392*724ba675SRob Herring interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 393*724ba675SRob Herring clocks = <&p0_clk>; 394*724ba675SRob Herring }; 395*724ba675SRob Herring 396*724ba675SRob Herring /* Special CPG clocks */ 397*724ba675SRob Herring cpg_clocks: cpg_clocks@fcfe0000 { 398*724ba675SRob Herring #clock-cells = <1>; 399*724ba675SRob Herring compatible = "renesas,r7s72100-cpg-clocks", 400*724ba675SRob Herring "renesas,rz-cpg-clocks"; 401*724ba675SRob Herring reg = <0xfcfe0000 0x18>; 402*724ba675SRob Herring clocks = <&extal_clk>, <&usb_x1_clk>; 403*724ba675SRob Herring clock-output-names = "pll", "i", "g"; 404*724ba675SRob Herring #power-domain-cells = <0>; 405*724ba675SRob Herring }; 406*724ba675SRob Herring 407*724ba675SRob Herring /* MSTP clocks */ 408*724ba675SRob Herring mstp3_clks: mstp3_clks@fcfe0420 { 409*724ba675SRob Herring #clock-cells = <1>; 410*724ba675SRob Herring compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 411*724ba675SRob Herring reg = <0xfcfe0420 4>; 412*724ba675SRob Herring clocks = <&p0_clk>; 413*724ba675SRob Herring clock-indices = <R7S72100_CLK_MTU2>; 414*724ba675SRob Herring clock-output-names = "mtu2"; 415*724ba675SRob Herring }; 416*724ba675SRob Herring 417*724ba675SRob Herring mstp4_clks: mstp4_clks@fcfe0424 { 418*724ba675SRob Herring #clock-cells = <1>; 419*724ba675SRob Herring compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 420*724ba675SRob Herring reg = <0xfcfe0424 4>; 421*724ba675SRob Herring clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, 422*724ba675SRob Herring <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; 423*724ba675SRob Herring clock-indices = < 424*724ba675SRob Herring R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3 425*724ba675SRob Herring R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7 426*724ba675SRob Herring >; 427*724ba675SRob Herring clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; 428*724ba675SRob Herring }; 429*724ba675SRob Herring 430*724ba675SRob Herring mstp5_clks: mstp5_clks@fcfe0428 { 431*724ba675SRob Herring #clock-cells = <1>; 432*724ba675SRob Herring compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 433*724ba675SRob Herring reg = <0xfcfe0428 4>; 434*724ba675SRob Herring clocks = <&p0_clk>, <&p0_clk>; 435*724ba675SRob Herring clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>; 436*724ba675SRob Herring clock-output-names = "ostm0", "ostm1"; 437*724ba675SRob Herring }; 438*724ba675SRob Herring 439*724ba675SRob Herring mstp6_clks: mstp6_clks@fcfe042c { 440*724ba675SRob Herring #clock-cells = <1>; 441*724ba675SRob Herring compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 442*724ba675SRob Herring reg = <0xfcfe042c 4>; 443*724ba675SRob Herring clocks = <&b_clk>, <&p0_clk>; 444*724ba675SRob Herring clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>; 445*724ba675SRob Herring clock-output-names = "ceu", "rtc"; 446*724ba675SRob Herring }; 447*724ba675SRob Herring 448*724ba675SRob Herring mstp7_clks: mstp7_clks@fcfe0430 { 449*724ba675SRob Herring #clock-cells = <1>; 450*724ba675SRob Herring compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 451*724ba675SRob Herring reg = <0xfcfe0430 4>; 452*724ba675SRob Herring clocks = <&b_clk>, <&p1_clk>, <&p1_clk>; 453*724ba675SRob Herring clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>; 454*724ba675SRob Herring clock-output-names = "ether", "usb0", "usb1"; 455*724ba675SRob Herring }; 456*724ba675SRob Herring 457*724ba675SRob Herring mstp8_clks: mstp8_clks@fcfe0434 { 458*724ba675SRob Herring #clock-cells = <1>; 459*724ba675SRob Herring compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 460*724ba675SRob Herring reg = <0xfcfe0434 4>; 461*724ba675SRob Herring clocks = <&p1_clk>; 462*724ba675SRob Herring clock-indices = <R7S72100_CLK_MMCIF>; 463*724ba675SRob Herring clock-output-names = "mmcif"; 464*724ba675SRob Herring }; 465*724ba675SRob Herring 466*724ba675SRob Herring mstp9_clks: mstp9_clks@fcfe0438 { 467*724ba675SRob Herring #clock-cells = <1>; 468*724ba675SRob Herring compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 469*724ba675SRob Herring reg = <0xfcfe0438 4>; 470*724ba675SRob Herring clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>; 471*724ba675SRob Herring clock-indices = < 472*724ba675SRob Herring R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3 473*724ba675SRob Herring R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1 474*724ba675SRob Herring >; 475*724ba675SRob Herring clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1"; 476*724ba675SRob Herring }; 477*724ba675SRob Herring 478*724ba675SRob Herring mstp10_clks: mstp10_clks@fcfe043c { 479*724ba675SRob Herring #clock-cells = <1>; 480*724ba675SRob Herring compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 481*724ba675SRob Herring reg = <0xfcfe043c 4>; 482*724ba675SRob Herring clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, 483*724ba675SRob Herring <&p1_clk>; 484*724ba675SRob Herring clock-indices = < 485*724ba675SRob Herring R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3 486*724ba675SRob Herring R7S72100_CLK_SPI4 487*724ba675SRob Herring >; 488*724ba675SRob Herring clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4"; 489*724ba675SRob Herring }; 490*724ba675SRob Herring mstp12_clks: mstp12_clks@fcfe0444 { 491*724ba675SRob Herring #clock-cells = <1>; 492*724ba675SRob Herring compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 493*724ba675SRob Herring reg = <0xfcfe0444 4>; 494*724ba675SRob Herring clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; 495*724ba675SRob Herring clock-indices = < 496*724ba675SRob Herring R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01 497*724ba675SRob Herring R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11 498*724ba675SRob Herring >; 499*724ba675SRob Herring clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; 500*724ba675SRob Herring }; 501*724ba675SRob Herring 502*724ba675SRob Herring pinctrl: pinctrl@fcfe3000 { 503*724ba675SRob Herring compatible = "renesas,r7s72100-ports"; 504*724ba675SRob Herring 505*724ba675SRob Herring reg = <0xfcfe3000 0x4230>; 506*724ba675SRob Herring 507*724ba675SRob Herring port0: gpio-0 { 508*724ba675SRob Herring gpio-controller; 509*724ba675SRob Herring #gpio-cells = <2>; 510*724ba675SRob Herring gpio-ranges = <&pinctrl 0 0 6>; 511*724ba675SRob Herring }; 512*724ba675SRob Herring 513*724ba675SRob Herring port1: gpio-1 { 514*724ba675SRob Herring gpio-controller; 515*724ba675SRob Herring #gpio-cells = <2>; 516*724ba675SRob Herring gpio-ranges = <&pinctrl 0 16 16>; 517*724ba675SRob Herring }; 518*724ba675SRob Herring 519*724ba675SRob Herring port2: gpio-2 { 520*724ba675SRob Herring gpio-controller; 521*724ba675SRob Herring #gpio-cells = <2>; 522*724ba675SRob Herring gpio-ranges = <&pinctrl 0 32 16>; 523*724ba675SRob Herring }; 524*724ba675SRob Herring 525*724ba675SRob Herring port3: gpio-3 { 526*724ba675SRob Herring gpio-controller; 527*724ba675SRob Herring #gpio-cells = <2>; 528*724ba675SRob Herring gpio-ranges = <&pinctrl 0 48 16>; 529*724ba675SRob Herring }; 530*724ba675SRob Herring 531*724ba675SRob Herring port4: gpio-4 { 532*724ba675SRob Herring gpio-controller; 533*724ba675SRob Herring #gpio-cells = <2>; 534*724ba675SRob Herring gpio-ranges = <&pinctrl 0 64 16>; 535*724ba675SRob Herring }; 536*724ba675SRob Herring 537*724ba675SRob Herring port5: gpio-5 { 538*724ba675SRob Herring gpio-controller; 539*724ba675SRob Herring #gpio-cells = <2>; 540*724ba675SRob Herring gpio-ranges = <&pinctrl 0 80 11>; 541*724ba675SRob Herring }; 542*724ba675SRob Herring 543*724ba675SRob Herring port6: gpio-6 { 544*724ba675SRob Herring gpio-controller; 545*724ba675SRob Herring #gpio-cells = <2>; 546*724ba675SRob Herring gpio-ranges = <&pinctrl 0 96 16>; 547*724ba675SRob Herring }; 548*724ba675SRob Herring 549*724ba675SRob Herring port7: gpio-7 { 550*724ba675SRob Herring gpio-controller; 551*724ba675SRob Herring #gpio-cells = <2>; 552*724ba675SRob Herring gpio-ranges = <&pinctrl 0 112 16>; 553*724ba675SRob Herring }; 554*724ba675SRob Herring 555*724ba675SRob Herring port8: gpio-8 { 556*724ba675SRob Herring gpio-controller; 557*724ba675SRob Herring #gpio-cells = <2>; 558*724ba675SRob Herring gpio-ranges = <&pinctrl 0 128 16>; 559*724ba675SRob Herring }; 560*724ba675SRob Herring 561*724ba675SRob Herring port9: gpio-9 { 562*724ba675SRob Herring gpio-controller; 563*724ba675SRob Herring #gpio-cells = <2>; 564*724ba675SRob Herring gpio-ranges = <&pinctrl 0 144 8>; 565*724ba675SRob Herring }; 566*724ba675SRob Herring 567*724ba675SRob Herring port10: gpio-10 { 568*724ba675SRob Herring gpio-controller; 569*724ba675SRob Herring #gpio-cells = <2>; 570*724ba675SRob Herring gpio-ranges = <&pinctrl 0 160 16>; 571*724ba675SRob Herring }; 572*724ba675SRob Herring 573*724ba675SRob Herring port11: gpio-11 { 574*724ba675SRob Herring gpio-controller; 575*724ba675SRob Herring #gpio-cells = <2>; 576*724ba675SRob Herring gpio-ranges = <&pinctrl 0 176 16>; 577*724ba675SRob Herring }; 578*724ba675SRob Herring }; 579*724ba675SRob Herring 580*724ba675SRob Herring ostm0: timer@fcfec000 { 581*724ba675SRob Herring compatible = "renesas,r7s72100-ostm", "renesas,ostm"; 582*724ba675SRob Herring reg = <0xfcfec000 0x30>; 583*724ba675SRob Herring interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>; 584*724ba675SRob Herring clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; 585*724ba675SRob Herring power-domains = <&cpg_clocks>; 586*724ba675SRob Herring status = "disabled"; 587*724ba675SRob Herring }; 588*724ba675SRob Herring 589*724ba675SRob Herring ostm1: timer@fcfec400 { 590*724ba675SRob Herring compatible = "renesas,r7s72100-ostm", "renesas,ostm"; 591*724ba675SRob Herring reg = <0xfcfec400 0x30>; 592*724ba675SRob Herring interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>; 593*724ba675SRob Herring clocks = <&mstp5_clks R7S72100_CLK_OSTM1>; 594*724ba675SRob Herring power-domains = <&cpg_clocks>; 595*724ba675SRob Herring status = "disabled"; 596*724ba675SRob Herring }; 597*724ba675SRob Herring 598*724ba675SRob Herring i2c0: i2c@fcfee000 { 599*724ba675SRob Herring #address-cells = <1>; 600*724ba675SRob Herring #size-cells = <0>; 601*724ba675SRob Herring compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 602*724ba675SRob Herring reg = <0xfcfee000 0x44>; 603*724ba675SRob Herring interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 604*724ba675SRob Herring <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, 605*724ba675SRob Herring <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>, 606*724ba675SRob Herring <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 607*724ba675SRob Herring <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 608*724ba675SRob Herring <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 609*724ba675SRob Herring <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 610*724ba675SRob Herring <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 611*724ba675SRob Herring interrupt-names = "tei", "ri", "ti", "spi", "sti", 612*724ba675SRob Herring "naki", "ali", "tmoi"; 613*724ba675SRob Herring clocks = <&mstp9_clks R7S72100_CLK_I2C0>; 614*724ba675SRob Herring clock-frequency = <100000>; 615*724ba675SRob Herring power-domains = <&cpg_clocks>; 616*724ba675SRob Herring status = "disabled"; 617*724ba675SRob Herring }; 618*724ba675SRob Herring 619*724ba675SRob Herring i2c1: i2c@fcfee400 { 620*724ba675SRob Herring #address-cells = <1>; 621*724ba675SRob Herring #size-cells = <0>; 622*724ba675SRob Herring compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 623*724ba675SRob Herring reg = <0xfcfee400 0x44>; 624*724ba675SRob Herring interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 625*724ba675SRob Herring <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>, 626*724ba675SRob Herring <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>, 627*724ba675SRob Herring <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 628*724ba675SRob Herring <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 629*724ba675SRob Herring <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 630*724ba675SRob Herring <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 631*724ba675SRob Herring <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 632*724ba675SRob Herring interrupt-names = "tei", "ri", "ti", "spi", "sti", 633*724ba675SRob Herring "naki", "ali", "tmoi"; 634*724ba675SRob Herring clocks = <&mstp9_clks R7S72100_CLK_I2C1>; 635*724ba675SRob Herring clock-frequency = <100000>; 636*724ba675SRob Herring power-domains = <&cpg_clocks>; 637*724ba675SRob Herring status = "disabled"; 638*724ba675SRob Herring }; 639*724ba675SRob Herring 640*724ba675SRob Herring i2c2: i2c@fcfee800 { 641*724ba675SRob Herring #address-cells = <1>; 642*724ba675SRob Herring #size-cells = <0>; 643*724ba675SRob Herring compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 644*724ba675SRob Herring reg = <0xfcfee800 0x44>; 645*724ba675SRob Herring interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 646*724ba675SRob Herring <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>, 647*724ba675SRob Herring <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>, 648*724ba675SRob Herring <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 649*724ba675SRob Herring <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 650*724ba675SRob Herring <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 651*724ba675SRob Herring <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 652*724ba675SRob Herring <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 653*724ba675SRob Herring interrupt-names = "tei", "ri", "ti", "spi", "sti", 654*724ba675SRob Herring "naki", "ali", "tmoi"; 655*724ba675SRob Herring clocks = <&mstp9_clks R7S72100_CLK_I2C2>; 656*724ba675SRob Herring clock-frequency = <100000>; 657*724ba675SRob Herring power-domains = <&cpg_clocks>; 658*724ba675SRob Herring status = "disabled"; 659*724ba675SRob Herring }; 660*724ba675SRob Herring 661*724ba675SRob Herring i2c3: i2c@fcfeec00 { 662*724ba675SRob Herring #address-cells = <1>; 663*724ba675SRob Herring #size-cells = <0>; 664*724ba675SRob Herring compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 665*724ba675SRob Herring reg = <0xfcfeec00 0x44>; 666*724ba675SRob Herring interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 667*724ba675SRob Herring <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>, 668*724ba675SRob Herring <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>, 669*724ba675SRob Herring <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 670*724ba675SRob Herring <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 671*724ba675SRob Herring <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 672*724ba675SRob Herring <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 673*724ba675SRob Herring <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 674*724ba675SRob Herring interrupt-names = "tei", "ri", "ti", "spi", "sti", 675*724ba675SRob Herring "naki", "ali", "tmoi"; 676*724ba675SRob Herring clocks = <&mstp9_clks R7S72100_CLK_I2C3>; 677*724ba675SRob Herring clock-frequency = <100000>; 678*724ba675SRob Herring power-domains = <&cpg_clocks>; 679*724ba675SRob Herring status = "disabled"; 680*724ba675SRob Herring }; 681*724ba675SRob Herring 682*724ba675SRob Herring irqc: interrupt-controller@fcfef800 { 683*724ba675SRob Herring compatible = "renesas,r7s72100-irqc", 684*724ba675SRob Herring "renesas,rza1-irqc"; 685*724ba675SRob Herring #interrupt-cells = <2>; 686*724ba675SRob Herring #address-cells = <0>; 687*724ba675SRob Herring interrupt-controller; 688*724ba675SRob Herring reg = <0xfcfef800 0x6>; 689*724ba675SRob Herring interrupt-map = 690*724ba675SRob Herring <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 691*724ba675SRob Herring <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 692*724ba675SRob Herring <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 693*724ba675SRob Herring <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 694*724ba675SRob Herring <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 695*724ba675SRob Herring <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 696*724ba675SRob Herring <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 697*724ba675SRob Herring <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 698*724ba675SRob Herring interrupt-map-mask = <7 0>; 699*724ba675SRob Herring }; 700*724ba675SRob Herring 701*724ba675SRob Herring mtu2: timer@fcff0000 { 702*724ba675SRob Herring compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; 703*724ba675SRob Herring reg = <0xfcff0000 0x400>; 704*724ba675SRob Herring interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 705*724ba675SRob Herring interrupt-names = "tgi0a"; 706*724ba675SRob Herring clocks = <&mstp3_clks R7S72100_CLK_MTU2>; 707*724ba675SRob Herring clock-names = "fck"; 708*724ba675SRob Herring power-domains = <&cpg_clocks>; 709*724ba675SRob Herring status = "disabled"; 710*724ba675SRob Herring }; 711*724ba675SRob Herring 712*724ba675SRob Herring rtc: rtc@fcff1000 { 713*724ba675SRob Herring compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; 714*724ba675SRob Herring reg = <0xfcff1000 0x2e>; 715*724ba675SRob Herring interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 716*724ba675SRob Herring <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 717*724ba675SRob Herring <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 718*724ba675SRob Herring interrupt-names = "alarm", "period", "carry"; 719*724ba675SRob Herring clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, 720*724ba675SRob Herring <&rtc_x3_clk>, <&extal_clk>; 721*724ba675SRob Herring clock-names = "fck", "rtc_x1", "rtc_x3", "extal"; 722*724ba675SRob Herring power-domains = <&cpg_clocks>; 723*724ba675SRob Herring status = "disabled"; 724*724ba675SRob Herring }; 725*724ba675SRob Herring }; 726*724ba675SRob Herring 727*724ba675SRob Herring usb_x1_clk: usb_x1 { 728*724ba675SRob Herring #clock-cells = <0>; 729*724ba675SRob Herring compatible = "fixed-clock"; 730*724ba675SRob Herring /* If clk present, value must be set by board */ 731*724ba675SRob Herring clock-frequency = <0>; 732*724ba675SRob Herring }; 733*724ba675SRob Herring}; 734