1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree Source for the Emma Mobile EV2 SoC 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2012 Renesas Solutions Corp. 6*724ba675SRob Herring */ 7*724ba675SRob Herring 8*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 9*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 10*724ba675SRob Herring 11*724ba675SRob Herring/ { 12*724ba675SRob Herring compatible = "renesas,emev2"; 13*724ba675SRob Herring interrupt-parent = <&gic>; 14*724ba675SRob Herring #address-cells = <1>; 15*724ba675SRob Herring #size-cells = <1>; 16*724ba675SRob Herring 17*724ba675SRob Herring aliases { 18*724ba675SRob Herring gpio0 = &gpio0; 19*724ba675SRob Herring gpio1 = &gpio1; 20*724ba675SRob Herring gpio2 = &gpio2; 21*724ba675SRob Herring gpio3 = &gpio3; 22*724ba675SRob Herring gpio4 = &gpio4; 23*724ba675SRob Herring i2c0 = &iic0; 24*724ba675SRob Herring i2c1 = &iic1; 25*724ba675SRob Herring }; 26*724ba675SRob Herring 27*724ba675SRob Herring cpus { 28*724ba675SRob Herring #address-cells = <1>; 29*724ba675SRob Herring #size-cells = <0>; 30*724ba675SRob Herring 31*724ba675SRob Herring cpu0: cpu@0 { 32*724ba675SRob Herring device_type = "cpu"; 33*724ba675SRob Herring compatible = "arm,cortex-a9"; 34*724ba675SRob Herring reg = <0>; 35*724ba675SRob Herring clock-frequency = <533000000>; 36*724ba675SRob Herring }; 37*724ba675SRob Herring cpu1: cpu@1 { 38*724ba675SRob Herring device_type = "cpu"; 39*724ba675SRob Herring compatible = "arm,cortex-a9"; 40*724ba675SRob Herring reg = <1>; 41*724ba675SRob Herring clock-frequency = <533000000>; 42*724ba675SRob Herring }; 43*724ba675SRob Herring }; 44*724ba675SRob Herring 45*724ba675SRob Herring gic: interrupt-controller@e0020000 { 46*724ba675SRob Herring compatible = "arm,pl390"; 47*724ba675SRob Herring interrupt-controller; 48*724ba675SRob Herring #interrupt-cells = <3>; 49*724ba675SRob Herring reg = <0xe0028000 0x1000>, 50*724ba675SRob Herring <0xe0020000 0x0100>; 51*724ba675SRob Herring }; 52*724ba675SRob Herring 53*724ba675SRob Herring pmu { 54*724ba675SRob Herring compatible = "arm,cortex-a9-pmu"; 55*724ba675SRob Herring interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 56*724ba675SRob Herring <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 57*724ba675SRob Herring interrupt-affinity = <&cpu0>, <&cpu1>; 58*724ba675SRob Herring }; 59*724ba675SRob Herring 60*724ba675SRob Herring clocks@e0110000 { 61*724ba675SRob Herring compatible = "renesas,emev2-smu"; 62*724ba675SRob Herring reg = <0xe0110000 0x10000>; 63*724ba675SRob Herring #address-cells = <2>; 64*724ba675SRob Herring #size-cells = <0>; 65*724ba675SRob Herring 66*724ba675SRob Herring c32ki: c32ki { 67*724ba675SRob Herring compatible = "fixed-clock"; 68*724ba675SRob Herring clock-frequency = <32768>; 69*724ba675SRob Herring #clock-cells = <0>; 70*724ba675SRob Herring }; 71*724ba675SRob Herring iic0_sclkdiv: iic0_sclkdiv@624,0 { 72*724ba675SRob Herring compatible = "renesas,emev2-smu-clkdiv"; 73*724ba675SRob Herring reg = <0x624 0>; 74*724ba675SRob Herring clocks = <&pll3_fo>; 75*724ba675SRob Herring #clock-cells = <0>; 76*724ba675SRob Herring }; 77*724ba675SRob Herring iic0_sclk: iic0_sclk@48c,1 { 78*724ba675SRob Herring compatible = "renesas,emev2-smu-gclk"; 79*724ba675SRob Herring reg = <0x48c 1>; 80*724ba675SRob Herring clocks = <&iic0_sclkdiv>; 81*724ba675SRob Herring #clock-cells = <0>; 82*724ba675SRob Herring }; 83*724ba675SRob Herring iic1_sclkdiv: iic1_sclkdiv@624,16 { 84*724ba675SRob Herring compatible = "renesas,emev2-smu-clkdiv"; 85*724ba675SRob Herring reg = <0x624 16>; 86*724ba675SRob Herring clocks = <&pll3_fo>; 87*724ba675SRob Herring #clock-cells = <0>; 88*724ba675SRob Herring }; 89*724ba675SRob Herring iic1_sclk: iic1_sclk@490,1 { 90*724ba675SRob Herring compatible = "renesas,emev2-smu-gclk"; 91*724ba675SRob Herring reg = <0x490 1>; 92*724ba675SRob Herring clocks = <&iic1_sclkdiv>; 93*724ba675SRob Herring #clock-cells = <0>; 94*724ba675SRob Herring }; 95*724ba675SRob Herring pll3_fo: pll3_fo { 96*724ba675SRob Herring compatible = "fixed-factor-clock"; 97*724ba675SRob Herring clocks = <&c32ki>; 98*724ba675SRob Herring clock-div = <1>; 99*724ba675SRob Herring clock-mult = <7000>; 100*724ba675SRob Herring #clock-cells = <0>; 101*724ba675SRob Herring }; 102*724ba675SRob Herring usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 { 103*724ba675SRob Herring compatible = "renesas,emev2-smu-clkdiv"; 104*724ba675SRob Herring reg = <0x610 0>; 105*724ba675SRob Herring clocks = <&pll3_fo>; 106*724ba675SRob Herring #clock-cells = <0>; 107*724ba675SRob Herring }; 108*724ba675SRob Herring usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 { 109*724ba675SRob Herring compatible = "renesas,emev2-smu-clkdiv"; 110*724ba675SRob Herring reg = <0x65c 0>; 111*724ba675SRob Herring clocks = <&pll3_fo>; 112*724ba675SRob Herring #clock-cells = <0>; 113*724ba675SRob Herring }; 114*724ba675SRob Herring usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 { 115*724ba675SRob Herring compatible = "renesas,emev2-smu-clkdiv"; 116*724ba675SRob Herring reg = <0x65c 16>; 117*724ba675SRob Herring clocks = <&pll3_fo>; 118*724ba675SRob Herring #clock-cells = <0>; 119*724ba675SRob Herring }; 120*724ba675SRob Herring usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 { 121*724ba675SRob Herring compatible = "renesas,emev2-smu-clkdiv"; 122*724ba675SRob Herring reg = <0x660 0>; 123*724ba675SRob Herring clocks = <&pll3_fo>; 124*724ba675SRob Herring #clock-cells = <0>; 125*724ba675SRob Herring }; 126*724ba675SRob Herring usia_u0_sclk: usia_u0_sclk@4a0,1 { 127*724ba675SRob Herring compatible = "renesas,emev2-smu-gclk"; 128*724ba675SRob Herring reg = <0x4a0 1>; 129*724ba675SRob Herring clocks = <&usia_u0_sclkdiv>; 130*724ba675SRob Herring #clock-cells = <0>; 131*724ba675SRob Herring }; 132*724ba675SRob Herring usib_u1_sclk: usib_u1_sclk@4b8,1 { 133*724ba675SRob Herring compatible = "renesas,emev2-smu-gclk"; 134*724ba675SRob Herring reg = <0x4b8 1>; 135*724ba675SRob Herring clocks = <&usib_u1_sclkdiv>; 136*724ba675SRob Herring #clock-cells = <0>; 137*724ba675SRob Herring }; 138*724ba675SRob Herring usib_u2_sclk: usib_u2_sclk@4bc,1 { 139*724ba675SRob Herring compatible = "renesas,emev2-smu-gclk"; 140*724ba675SRob Herring reg = <0x4bc 1>; 141*724ba675SRob Herring clocks = <&usib_u2_sclkdiv>; 142*724ba675SRob Herring #clock-cells = <0>; 143*724ba675SRob Herring }; 144*724ba675SRob Herring usib_u3_sclk: usib_u3_sclk@4c0,1 { 145*724ba675SRob Herring compatible = "renesas,emev2-smu-gclk"; 146*724ba675SRob Herring reg = <0x4c0 1>; 147*724ba675SRob Herring clocks = <&usib_u3_sclkdiv>; 148*724ba675SRob Herring #clock-cells = <0>; 149*724ba675SRob Herring }; 150*724ba675SRob Herring sti_sclk: sti_sclk@528,1 { 151*724ba675SRob Herring compatible = "renesas,emev2-smu-gclk"; 152*724ba675SRob Herring reg = <0x528 1>; 153*724ba675SRob Herring clocks = <&c32ki>; 154*724ba675SRob Herring #clock-cells = <0>; 155*724ba675SRob Herring }; 156*724ba675SRob Herring }; 157*724ba675SRob Herring 158*724ba675SRob Herring timer@e0180000 { 159*724ba675SRob Herring compatible = "renesas,em-sti"; 160*724ba675SRob Herring reg = <0xe0180000 0x54>; 161*724ba675SRob Herring interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 162*724ba675SRob Herring clocks = <&sti_sclk>; 163*724ba675SRob Herring clock-names = "sclk"; 164*724ba675SRob Herring }; 165*724ba675SRob Herring 166*724ba675SRob Herring uart0: serial@e1020000 { 167*724ba675SRob Herring compatible = "renesas,em-uart"; 168*724ba675SRob Herring reg = <0xe1020000 0x38>; 169*724ba675SRob Herring interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 170*724ba675SRob Herring clocks = <&usia_u0_sclk>; 171*724ba675SRob Herring clock-names = "sclk"; 172*724ba675SRob Herring }; 173*724ba675SRob Herring 174*724ba675SRob Herring uart1: serial@e1030000 { 175*724ba675SRob Herring compatible = "renesas,em-uart"; 176*724ba675SRob Herring reg = <0xe1030000 0x38>; 177*724ba675SRob Herring interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 178*724ba675SRob Herring clocks = <&usib_u1_sclk>; 179*724ba675SRob Herring clock-names = "sclk"; 180*724ba675SRob Herring }; 181*724ba675SRob Herring 182*724ba675SRob Herring uart2: serial@e1040000 { 183*724ba675SRob Herring compatible = "renesas,em-uart"; 184*724ba675SRob Herring reg = <0xe1040000 0x38>; 185*724ba675SRob Herring interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 186*724ba675SRob Herring clocks = <&usib_u2_sclk>; 187*724ba675SRob Herring clock-names = "sclk"; 188*724ba675SRob Herring }; 189*724ba675SRob Herring 190*724ba675SRob Herring uart3: serial@e1050000 { 191*724ba675SRob Herring compatible = "renesas,em-uart"; 192*724ba675SRob Herring reg = <0xe1050000 0x38>; 193*724ba675SRob Herring interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 194*724ba675SRob Herring clocks = <&usib_u3_sclk>; 195*724ba675SRob Herring clock-names = "sclk"; 196*724ba675SRob Herring }; 197*724ba675SRob Herring 198*724ba675SRob Herring pfc: pinctrl@e0140200 { 199*724ba675SRob Herring compatible = "renesas,pfc-emev2"; 200*724ba675SRob Herring reg = <0xe0140200 0x100>; 201*724ba675SRob Herring }; 202*724ba675SRob Herring 203*724ba675SRob Herring gpio0: gpio@e0050000 { 204*724ba675SRob Herring compatible = "renesas,em-gio"; 205*724ba675SRob Herring reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; 206*724ba675SRob Herring interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 207*724ba675SRob Herring <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 208*724ba675SRob Herring gpio-controller; 209*724ba675SRob Herring gpio-ranges = <&pfc 0 0 32>; 210*724ba675SRob Herring #gpio-cells = <2>; 211*724ba675SRob Herring ngpios = <32>; 212*724ba675SRob Herring interrupt-controller; 213*724ba675SRob Herring #interrupt-cells = <2>; 214*724ba675SRob Herring }; 215*724ba675SRob Herring 216*724ba675SRob Herring gpio1: gpio@e0050080 { 217*724ba675SRob Herring compatible = "renesas,em-gio"; 218*724ba675SRob Herring reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>; 219*724ba675SRob Herring interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 220*724ba675SRob Herring <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 221*724ba675SRob Herring gpio-controller; 222*724ba675SRob Herring gpio-ranges = <&pfc 0 32 32>; 223*724ba675SRob Herring #gpio-cells = <2>; 224*724ba675SRob Herring ngpios = <32>; 225*724ba675SRob Herring interrupt-controller; 226*724ba675SRob Herring #interrupt-cells = <2>; 227*724ba675SRob Herring }; 228*724ba675SRob Herring 229*724ba675SRob Herring gpio2: gpio@e0050100 { 230*724ba675SRob Herring compatible = "renesas,em-gio"; 231*724ba675SRob Herring reg = <0xe0050100 0x2c>, <0xe0050140 0x20>; 232*724ba675SRob Herring interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 233*724ba675SRob Herring <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 234*724ba675SRob Herring gpio-controller; 235*724ba675SRob Herring gpio-ranges = <&pfc 0 64 32>; 236*724ba675SRob Herring #gpio-cells = <2>; 237*724ba675SRob Herring ngpios = <32>; 238*724ba675SRob Herring interrupt-controller; 239*724ba675SRob Herring #interrupt-cells = <2>; 240*724ba675SRob Herring }; 241*724ba675SRob Herring 242*724ba675SRob Herring gpio3: gpio@e0050180 { 243*724ba675SRob Herring compatible = "renesas,em-gio"; 244*724ba675SRob Herring reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>; 245*724ba675SRob Herring interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 246*724ba675SRob Herring <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 247*724ba675SRob Herring gpio-controller; 248*724ba675SRob Herring gpio-ranges = <&pfc 0 96 32>; 249*724ba675SRob Herring #gpio-cells = <2>; 250*724ba675SRob Herring ngpios = <32>; 251*724ba675SRob Herring interrupt-controller; 252*724ba675SRob Herring #interrupt-cells = <2>; 253*724ba675SRob Herring }; 254*724ba675SRob Herring 255*724ba675SRob Herring gpio4: gpio@e0050200 { 256*724ba675SRob Herring compatible = "renesas,em-gio"; 257*724ba675SRob Herring reg = <0xe0050200 0x2c>, <0xe0050240 0x20>; 258*724ba675SRob Herring interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 259*724ba675SRob Herring <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 260*724ba675SRob Herring gpio-controller; 261*724ba675SRob Herring gpio-ranges = <&pfc 0 128 31>; 262*724ba675SRob Herring #gpio-cells = <2>; 263*724ba675SRob Herring ngpios = <31>; 264*724ba675SRob Herring interrupt-controller; 265*724ba675SRob Herring #interrupt-cells = <2>; 266*724ba675SRob Herring }; 267*724ba675SRob Herring 268*724ba675SRob Herring iic0: i2c@e0070000 { 269*724ba675SRob Herring #address-cells = <1>; 270*724ba675SRob Herring #size-cells = <0>; 271*724ba675SRob Herring compatible = "renesas,iic-emev2"; 272*724ba675SRob Herring reg = <0xe0070000 0x28>; 273*724ba675SRob Herring interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; 274*724ba675SRob Herring clocks = <&iic0_sclk>; 275*724ba675SRob Herring clock-names = "sclk"; 276*724ba675SRob Herring status = "disabled"; 277*724ba675SRob Herring }; 278*724ba675SRob Herring 279*724ba675SRob Herring iic1: i2c@e10a0000 { 280*724ba675SRob Herring #address-cells = <1>; 281*724ba675SRob Herring #size-cells = <0>; 282*724ba675SRob Herring compatible = "renesas,iic-emev2"; 283*724ba675SRob Herring reg = <0xe10a0000 0x28>; 284*724ba675SRob Herring interrupts = <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>; 285*724ba675SRob Herring clocks = <&iic1_sclk>; 286*724ba675SRob Herring clock-names = "sclk"; 287*724ba675SRob Herring status = "disabled"; 288*724ba675SRob Herring }; 289*724ba675SRob Herring}; 290