1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Device Tree Source for Qualcomm MDM9615 SoC 4 * 5 * Copyright (C) 2016 BayLibre, SAS. 6 * Author : Neil Armstrong <narmstrong@baylibre.com> 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/clock/qcom,gcc-mdm9615.h> 13#include <dt-bindings/reset/qcom,gcc-mdm9615.h> 14#include <dt-bindings/mfd/qcom-rpm.h> 15#include <dt-bindings/soc/qcom,gsbi.h> 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 model = "Qualcomm MDM9615"; 21 compatible = "qcom,mdm9615"; 22 interrupt-parent = <&intc>; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu0: cpu@0 { 29 compatible = "arm,cortex-a5"; 30 reg = <0>; 31 device_type = "cpu"; 32 next-level-cache = <&L2>; 33 }; 34 }; 35 36 cpu-pmu { 37 compatible = "arm,cortex-a5-pmu"; 38 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 39 }; 40 41 clocks { 42 cxo_board: cxo_board { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <19200000>; 46 }; 47 }; 48 49 regulators { 50 vsdcc_fixed: vsdcc-regulator { 51 compatible = "regulator-fixed"; 52 regulator-name = "SDCC Power"; 53 regulator-min-microvolt = <2700000>; 54 regulator-max-microvolt = <2700000>; 55 regulator-always-on; 56 }; 57 }; 58 59 soc: soc { 60 #address-cells = <1>; 61 #size-cells = <1>; 62 ranges; 63 compatible = "simple-bus"; 64 65 L2: cache-controller@2040000 { 66 compatible = "arm,pl310-cache"; 67 reg = <0x02040000 0x1000>; 68 arm,data-latency = <2 2 0>; 69 cache-unified; 70 cache-level = <2>; 71 }; 72 73 intc: interrupt-controller@2000000 { 74 compatible = "qcom,msm-qgic2"; 75 interrupt-controller; 76 #interrupt-cells = <3>; 77 reg = <0x02000000 0x1000>, 78 <0x02002000 0x1000>; 79 }; 80 81 timer@200a000 { 82 compatible = "qcom,kpss-wdt-mdm9615", "qcom,kpss-timer", 83 "qcom,msm-timer"; 84 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>, 85 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>, 86 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>; 87 reg = <0x0200a000 0x100>; 88 clock-frequency = <27000000>; 89 cpu-offset = <0x80000>; 90 }; 91 92 msmgpio: pinctrl@800000 { 93 compatible = "qcom,mdm9615-pinctrl"; 94 gpio-controller; 95 gpio-ranges = <&msmgpio 0 0 88>; 96 #gpio-cells = <2>; 97 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 98 interrupt-controller; 99 #interrupt-cells = <2>; 100 reg = <0x800000 0x4000>; 101 }; 102 103 gcc: clock-controller@900000 { 104 compatible = "qcom,gcc-mdm9615"; 105 #clock-cells = <1>; 106 #power-domain-cells = <1>; 107 #reset-cells = <1>; 108 reg = <0x900000 0x4000>; 109 }; 110 111 lcc: clock-controller@28000000 { 112 compatible = "qcom,lcc-mdm9615"; 113 reg = <0x28000000 0x1000>; 114 #clock-cells = <1>; 115 #reset-cells = <1>; 116 clocks = <&cxo_board>, 117 <&gcc PLL4_VOTE>, 118 <0>, 119 <0>, <0>, 120 <0>, <0>, 121 <0>; 122 clock-names = "cxo", 123 "pll4_vote", 124 "mi2s_codec_clk", 125 "codec_i2s_mic_codec_clk", 126 "spare_i2s_mic_codec_clk", 127 "codec_i2s_spkr_codec_clk", 128 "spare_i2s_spkr_codec_clk", 129 "pcm_codec_clk"; 130 }; 131 132 l2cc: clock-controller@2011000 { 133 compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon"; 134 reg = <0x02011000 0x1000>; 135 }; 136 137 rng@1a500000 { 138 compatible = "qcom,prng"; 139 reg = <0x1a500000 0x200>; 140 clocks = <&gcc PRNG_CLK>; 141 clock-names = "core"; 142 assigned-clocks = <&gcc PRNG_CLK>; 143 assigned-clock-rates = <32000000>; 144 }; 145 146 gsbi2: gsbi@16100000 { 147 compatible = "qcom,gsbi-v1.0.0"; 148 cell-index = <2>; 149 reg = <0x16100000 0x100>; 150 clocks = <&gcc GSBI2_H_CLK>; 151 clock-names = "iface"; 152 status = "disabled"; 153 #address-cells = <1>; 154 #size-cells = <1>; 155 ranges; 156 157 gsbi2_i2c: i2c@16180000 { 158 compatible = "qcom,i2c-qup-v1.1.1"; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 reg = <0x16180000 0x1000>; 162 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 163 164 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 165 clock-names = "core", "iface"; 166 status = "disabled"; 167 }; 168 }; 169 170 gsbi3: gsbi@16200000 { 171 compatible = "qcom,gsbi-v1.0.0"; 172 cell-index = <3>; 173 reg = <0x16200000 0x100>; 174 clocks = <&gcc GSBI3_H_CLK>; 175 clock-names = "iface"; 176 status = "disabled"; 177 #address-cells = <1>; 178 #size-cells = <1>; 179 ranges; 180 181 gsbi3_spi: spi@16280000 { 182 compatible = "qcom,spi-qup-v1.1.1"; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 reg = <0x16280000 0x1000>; 186 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 187 188 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; 189 clock-names = "core", "iface"; 190 status = "disabled"; 191 }; 192 }; 193 194 gsbi4: gsbi@16300000 { 195 compatible = "qcom,gsbi-v1.0.0"; 196 cell-index = <4>; 197 reg = <0x16300000 0x100>; 198 clocks = <&gcc GSBI4_H_CLK>; 199 clock-names = "iface"; 200 status = "disabled"; 201 #address-cells = <1>; 202 #size-cells = <1>; 203 ranges; 204 205 syscon-tcsr = <&tcsr>; 206 207 gsbi4_serial: serial@16340000 { 208 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 209 reg = <0x16340000 0x1000>, 210 <0x16300000 0x1000>; 211 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 212 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 213 clock-names = "core", "iface"; 214 status = "disabled"; 215 }; 216 }; 217 218 gsbi5: gsbi@16400000 { 219 compatible = "qcom,gsbi-v1.0.0"; 220 cell-index = <5>; 221 reg = <0x16400000 0x100>; 222 clocks = <&gcc GSBI5_H_CLK>; 223 clock-names = "iface"; 224 status = "disabled"; 225 #address-cells = <1>; 226 #size-cells = <1>; 227 ranges; 228 229 syscon-tcsr = <&tcsr>; 230 231 gsbi5_i2c: i2c@16480000 { 232 compatible = "qcom,i2c-qup-v1.1.1"; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 reg = <0x16480000 0x1000>; 236 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 237 238 /* QUP clock is not initialized, set rate */ 239 assigned-clocks = <&gcc GSBI5_QUP_CLK>; 240 assigned-clock-rates = <24000000>; 241 242 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 243 clock-names = "core", "iface"; 244 status = "disabled"; 245 }; 246 247 gsbi5_serial: serial@16440000 { 248 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 249 reg = <0x16440000 0x1000>, 250 <0x16400000 0x1000>; 251 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 253 clock-names = "core", "iface"; 254 status = "disabled"; 255 }; 256 }; 257 258 qcom,ssbi@500000 { 259 compatible = "qcom,ssbi"; 260 reg = <0x500000 0x1000>; 261 qcom,controller-type = "pmic-arbiter"; 262 263 pmicintc: pmic { 264 compatible = "qcom,pm8018", "qcom,pm8921"; 265 interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>; 266 #interrupt-cells = <2>; 267 interrupt-controller; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 271 pwrkey@1c { 272 compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey"; 273 reg = <0x1c>; 274 interrupt-parent = <&pmicintc>; 275 interrupts = <50 IRQ_TYPE_EDGE_RISING>, 276 <51 IRQ_TYPE_EDGE_RISING>; 277 debounce = <15625>; 278 pull-up; 279 }; 280 281 pmicmpp: mpps@50 { 282 compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp"; 283 interrupt-controller; 284 #interrupt-cells = <2>; 285 reg = <0x50>; 286 gpio-controller; 287 #gpio-cells = <2>; 288 gpio-ranges = <&pmicmpp 0 0 6>; 289 }; 290 291 rtc@11d { 292 compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc"; 293 interrupt-parent = <&pmicintc>; 294 interrupts = <39 IRQ_TYPE_EDGE_RISING>; 295 reg = <0x11d>; 296 allow-set-time; 297 }; 298 299 pmicgpio: gpio@150 { 300 compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio"; 301 reg = <0x150>; 302 interrupt-controller; 303 #interrupt-cells = <2>; 304 gpio-controller; 305 gpio-ranges = <&pmicgpio 0 0 6>; 306 #gpio-cells = <2>; 307 }; 308 }; 309 }; 310 311 sdcc1bam: dma-controller@12182000 { 312 compatible = "qcom,bam-v1.3.0"; 313 reg = <0x12182000 0x8000>; 314 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&gcc SDC1_H_CLK>; 316 clock-names = "bam_clk"; 317 #dma-cells = <1>; 318 qcom,ee = <0>; 319 }; 320 321 sdcc2bam: dma-controller@12142000 { 322 compatible = "qcom,bam-v1.3.0"; 323 reg = <0x12142000 0x8000>; 324 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&gcc SDC2_H_CLK>; 326 clock-names = "bam_clk"; 327 #dma-cells = <1>; 328 qcom,ee = <0>; 329 }; 330 331 sdcc1: mmc@12180000 { 332 status = "disabled"; 333 compatible = "arm,pl18x", "arm,primecell"; 334 arm,primecell-periphid = <0x00051180>; 335 reg = <0x12180000 0x2000>; 336 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 338 clock-names = "mclk", "apb_pclk"; 339 bus-width = <8>; 340 max-frequency = <48000000>; 341 cap-sd-highspeed; 342 cap-mmc-highspeed; 343 vmmc-supply = <&vsdcc_fixed>; 344 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 345 dma-names = "tx", "rx"; 346 assigned-clocks = <&gcc SDC1_CLK>; 347 assigned-clock-rates = <400000>; 348 }; 349 350 sdcc2: mmc@12140000 { 351 compatible = "arm,pl18x", "arm,primecell"; 352 arm,primecell-periphid = <0x00051180>; 353 status = "disabled"; 354 reg = <0x12140000 0x2000>; 355 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; 357 clock-names = "mclk", "apb_pclk"; 358 bus-width = <4>; 359 cap-sd-highspeed; 360 cap-mmc-highspeed; 361 max-frequency = <48000000>; 362 no-1-8-v; 363 vmmc-supply = <&vsdcc_fixed>; 364 dmas = <&sdcc2bam 2>, <&sdcc2bam 1>; 365 dma-names = "tx", "rx"; 366 assigned-clocks = <&gcc SDC2_CLK>; 367 assigned-clock-rates = <400000>; 368 }; 369 370 tcsr: syscon@1a400000 { 371 compatible = "qcom,tcsr-mdm9615", "syscon"; 372 reg = <0x1a400000 0x100>; 373 }; 374 375 rpm: rpm@108000 { 376 compatible = "qcom,rpm-mdm9615"; 377 reg = <0x108000 0x1000>; 378 379 qcom,ipc = <&l2cc 0x8 2>; 380 381 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 382 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 383 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 384 interrupt-names = "ack", "err", "wakeup"; 385 386 regulators { 387 compatible = "qcom,rpm-pm8018-regulators"; 388 389 vin_lvs1-supply = <&pm8018_s3>; 390 391 vdd_l7-supply = <&pm8018_s4>; 392 vdd_l8-supply = <&pm8018_s3>; 393 vdd_l9_l10_l11_l12-supply = <&pm8018_s5>; 394 395 /* Buck SMPS */ 396 pm8018_s1: s1 { 397 regulator-min-microvolt = <500000>; 398 regulator-max-microvolt = <1150000>; 399 qcom,switch-mode-frequency = <1600000>; 400 bias-pull-down; 401 }; 402 403 pm8018_s2: s2 { 404 regulator-min-microvolt = <1225000>; 405 regulator-max-microvolt = <1300000>; 406 qcom,switch-mode-frequency = <1600000>; 407 bias-pull-down; 408 }; 409 410 pm8018_s3: s3 { 411 regulator-always-on; 412 regulator-min-microvolt = <1800000>; 413 regulator-max-microvolt = <1800000>; 414 qcom,switch-mode-frequency = <1600000>; 415 bias-pull-down; 416 }; 417 418 pm8018_s4: s4 { 419 regulator-min-microvolt = <2100000>; 420 regulator-max-microvolt = <2200000>; 421 qcom,switch-mode-frequency = <1600000>; 422 bias-pull-down; 423 }; 424 425 pm8018_s5: s5 { 426 regulator-always-on; 427 regulator-min-microvolt = <1350000>; 428 regulator-max-microvolt = <1350000>; 429 qcom,switch-mode-frequency = <1600000>; 430 bias-pull-down; 431 }; 432 433 /* PMOS LDO */ 434 pm8018_l2: l2 { 435 regulator-always-on; 436 regulator-min-microvolt = <1800000>; 437 regulator-max-microvolt = <1800000>; 438 bias-pull-down; 439 }; 440 441 pm8018_l3: l3 { 442 regulator-always-on; 443 regulator-min-microvolt = <1800000>; 444 regulator-max-microvolt = <1800000>; 445 bias-pull-down; 446 }; 447 448 pm8018_l4: l4 { 449 regulator-min-microvolt = <3300000>; 450 regulator-max-microvolt = <3300000>; 451 bias-pull-down; 452 }; 453 454 pm8018_l5: l5 { 455 regulator-min-microvolt = <2850000>; 456 regulator-max-microvolt = <2850000>; 457 bias-pull-down; 458 }; 459 460 pm8018_l6: l6 { 461 regulator-min-microvolt = <1800000>; 462 regulator-max-microvolt = <2850000>; 463 bias-pull-down; 464 }; 465 466 pm8018_l7: l7 { 467 regulator-min-microvolt = <1850000>; 468 regulator-max-microvolt = <1900000>; 469 bias-pull-down; 470 }; 471 472 pm8018_l8: l8 { 473 regulator-min-microvolt = <1200000>; 474 regulator-max-microvolt = <1200000>; 475 bias-pull-down; 476 }; 477 478 pm8018_l9: l9 { 479 regulator-min-microvolt = <750000>; 480 regulator-max-microvolt = <1150000>; 481 bias-pull-down; 482 }; 483 484 pm8018_l10: l10 { 485 regulator-min-microvolt = <1050000>; 486 regulator-max-microvolt = <1050000>; 487 bias-pull-down; 488 }; 489 490 pm8018_l11: l11 { 491 regulator-min-microvolt = <1050000>; 492 regulator-max-microvolt = <1050000>; 493 bias-pull-down; 494 }; 495 496 pm8018_l12: l12 { 497 regulator-min-microvolt = <1050000>; 498 regulator-max-microvolt = <1050000>; 499 bias-pull-down; 500 }; 501 502 pm8018_l13: l13 { 503 regulator-min-microvolt = <1850000>; 504 regulator-max-microvolt = <2950000>; 505 bias-pull-down; 506 }; 507 508 pm8018_l14: l14 { 509 regulator-min-microvolt = <2850000>; 510 regulator-max-microvolt = <2850000>; 511 bias-pull-down; 512 }; 513 514 /* Low Voltage Switch */ 515 pm8018_lvs1: lvs1 { 516 bias-pull-down; 517 }; 518 }; 519 }; 520 }; 521}; 522