1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-or-later 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright 2013 Freescale Semiconductor, Inc. 4*724ba675SRob Herring * Copyright 2013 Linaro Limited 5*724ba675SRob Herring */ 6*724ba675SRob Herring 7*724ba675SRob Herring/dts-v1/; 8*724ba675SRob Herring#include "vf610.dtsi" 9*724ba675SRob Herring 10*724ba675SRob Herring/ { 11*724ba675SRob Herring model = "PHYTEC Cosmic/Cosmic+ Board"; 12*724ba675SRob Herring compatible = "phytec,vf610-cosmic", "fsl,vf610"; 13*724ba675SRob Herring 14*724ba675SRob Herring chosen { 15*724ba675SRob Herring bootargs = "console=ttyLP1,115200"; 16*724ba675SRob Herring }; 17*724ba675SRob Herring 18*724ba675SRob Herring memory@80000000 { 19*724ba675SRob Herring device_type = "memory"; 20*724ba675SRob Herring reg = <0x80000000 0x10000000>; 21*724ba675SRob Herring }; 22*724ba675SRob Herring 23*724ba675SRob Herring enet_ext: enet_ext { 24*724ba675SRob Herring compatible = "fixed-clock"; 25*724ba675SRob Herring #clock-cells = <0>; 26*724ba675SRob Herring clock-frequency = <50000000>; 27*724ba675SRob Herring }; 28*724ba675SRob Herring}; 29*724ba675SRob Herring 30*724ba675SRob Herring&clks { 31*724ba675SRob Herring clocks = <&sxosc>, <&fxosc>, <&enet_ext>; 32*724ba675SRob Herring clock-names = "sxosc", "fxosc", "enet_ext"; 33*724ba675SRob Herring}; 34*724ba675SRob Herring 35*724ba675SRob Herring&esdhc1 { 36*724ba675SRob Herring pinctrl-names = "default"; 37*724ba675SRob Herring pinctrl-0 = <&pinctrl_esdhc1>; 38*724ba675SRob Herring bus-width = <4>; 39*724ba675SRob Herring status = "okay"; 40*724ba675SRob Herring}; 41*724ba675SRob Herring 42*724ba675SRob Herring&fec1 { 43*724ba675SRob Herring phy-mode = "rmii"; 44*724ba675SRob Herring pinctrl-names = "default"; 45*724ba675SRob Herring pinctrl-0 = <&pinctrl_fec1>; 46*724ba675SRob Herring status = "okay"; 47*724ba675SRob Herring}; 48*724ba675SRob Herring 49*724ba675SRob Herring&iomuxc { 50*724ba675SRob Herring vf610-cosmic { 51*724ba675SRob Herring pinctrl_esdhc1: esdhc1grp { 52*724ba675SRob Herring fsl,pins = < 53*724ba675SRob Herring VF610_PAD_PTA24__ESDHC1_CLK 0x31ef 54*724ba675SRob Herring VF610_PAD_PTA25__ESDHC1_CMD 0x31ef 55*724ba675SRob Herring VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef 56*724ba675SRob Herring VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef 57*724ba675SRob Herring VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef 58*724ba675SRob Herring VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef 59*724ba675SRob Herring VF610_PAD_PTB28__GPIO_98 0x219d 60*724ba675SRob Herring >; 61*724ba675SRob Herring }; 62*724ba675SRob Herring 63*724ba675SRob Herring pinctrl_fec1: fec1grp { 64*724ba675SRob Herring fsl,pins = < 65*724ba675SRob Herring VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 66*724ba675SRob Herring VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 67*724ba675SRob Herring VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 68*724ba675SRob Herring VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 69*724ba675SRob Herring VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 70*724ba675SRob Herring VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 71*724ba675SRob Herring VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 72*724ba675SRob Herring VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 73*724ba675SRob Herring VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 74*724ba675SRob Herring >; 75*724ba675SRob Herring }; 76*724ba675SRob Herring 77*724ba675SRob Herring pinctrl_uart1: uart1grp { 78*724ba675SRob Herring fsl,pins = < 79*724ba675SRob Herring VF610_PAD_PTB4__UART1_TX 0x21a2 80*724ba675SRob Herring VF610_PAD_PTB5__UART1_RX 0x21a1 81*724ba675SRob Herring >; 82*724ba675SRob Herring }; 83*724ba675SRob Herring }; 84*724ba675SRob Herring}; 85*724ba675SRob Herring 86*724ba675SRob Herring&uart1 { 87*724ba675SRob Herring pinctrl-names = "default"; 88*724ba675SRob Herring pinctrl-0 = <&pinctrl_uart1>; 89*724ba675SRob Herring status = "okay"; 90*724ba675SRob Herring}; 91