xref: /openbmc/linux/scripts/dtc/include-prefixes/arm/nxp/vf/vf500.dtsi (revision 2612e3bbc0386368a850140a6c9b990cd496a5ec)
1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2*724ba675SRob Herring//
3*724ba675SRob Herring// Copyright 2013 Freescale Semiconductor, Inc.
4*724ba675SRob Herring
5*724ba675SRob Herring#include "vfxxx.dtsi"
6*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h>
7*724ba675SRob Herring
8*724ba675SRob Herring/ {
9*724ba675SRob Herring	#address-cells = <1>;
10*724ba675SRob Herring	#size-cells = <1>;
11*724ba675SRob Herring	chosen { };
12*724ba675SRob Herring	aliases { };
13*724ba675SRob Herring
14*724ba675SRob Herring	cpus {
15*724ba675SRob Herring		#address-cells = <1>;
16*724ba675SRob Herring		#size-cells = <0>;
17*724ba675SRob Herring
18*724ba675SRob Herring		a5_cpu: cpu@0 {
19*724ba675SRob Herring			compatible = "arm,cortex-a5";
20*724ba675SRob Herring			device_type = "cpu";
21*724ba675SRob Herring			reg = <0x0>;
22*724ba675SRob Herring		};
23*724ba675SRob Herring	};
24*724ba675SRob Herring
25*724ba675SRob Herring	soc {
26*724ba675SRob Herring		bus@40000000 {
27*724ba675SRob Herring
28*724ba675SRob Herring			intc: interrupt-controller@40003000 {
29*724ba675SRob Herring				compatible = "arm,cortex-a9-gic";
30*724ba675SRob Herring				#interrupt-cells = <3>;
31*724ba675SRob Herring				interrupt-controller;
32*724ba675SRob Herring				interrupt-parent = <&intc>;
33*724ba675SRob Herring				reg = <0x40003000 0x1000>,
34*724ba675SRob Herring				      <0x40002100 0x100>;
35*724ba675SRob Herring			};
36*724ba675SRob Herring
37*724ba675SRob Herring			global_timer: timer@40002200 {
38*724ba675SRob Herring				compatible = "arm,cortex-a9-global-timer";
39*724ba675SRob Herring				reg = <0x40002200 0x20>;
40*724ba675SRob Herring				interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
41*724ba675SRob Herring				interrupt-parent = <&intc>;
42*724ba675SRob Herring				clocks = <&clks VF610_CLK_PLATFORM_BUS>;
43*724ba675SRob Herring			};
44*724ba675SRob Herring		};
45*724ba675SRob Herring
46*724ba675SRob Herring		bus@40080000 {
47*724ba675SRob Herring			pmu@40089000 {
48*724ba675SRob Herring				compatible = "arm,cortex-a5-pmu";
49*724ba675SRob Herring				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
50*724ba675SRob Herring				interrupt-affinity = <&a5_cpu>;
51*724ba675SRob Herring				reg = <0x40089000 0x1000>;
52*724ba675SRob Herring			};
53*724ba675SRob Herring		};
54*724ba675SRob Herring
55*724ba675SRob Herring	};
56*724ba675SRob Herring};
57*724ba675SRob Herring
58*724ba675SRob Herring&mscm_ir {
59*724ba675SRob Herring	interrupt-parent = <&intc>;
60*724ba675SRob Herring};
61*724ba675SRob Herring
62*724ba675SRob Herring&wdoga5 {
63*724ba675SRob Herring	status = "okay";
64*724ba675SRob Herring};
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