1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* Copyright 2016-2018 NXP Semiconductors 3*724ba675SRob Herring * Copyright 2019 Vladimir Oltean <olteanv@gmail.com> 4*724ba675SRob Herring */ 5*724ba675SRob Herring 6*724ba675SRob Herring/dts-v1/; 7*724ba675SRob Herring#include "ls1021a.dtsi" 8*724ba675SRob Herring 9*724ba675SRob Herring/ { 10*724ba675SRob Herring model = "NXP LS1021A-TSN Board"; 11*724ba675SRob Herring compatible = "fsl,ls1021a-tsn", "fsl,ls1021a"; 12*724ba675SRob Herring 13*724ba675SRob Herring sys_mclk: clock-mclk { 14*724ba675SRob Herring compatible = "fixed-clock"; 15*724ba675SRob Herring #clock-cells = <0>; 16*724ba675SRob Herring clock-frequency = <24576000>; 17*724ba675SRob Herring }; 18*724ba675SRob Herring 19*724ba675SRob Herring reg_vdda_codec: regulator-3V3 { 20*724ba675SRob Herring compatible = "regulator-fixed"; 21*724ba675SRob Herring regulator-name = "3P3V"; 22*724ba675SRob Herring regulator-min-microvolt = <3300000>; 23*724ba675SRob Herring regulator-max-microvolt = <3300000>; 24*724ba675SRob Herring regulator-always-on; 25*724ba675SRob Herring }; 26*724ba675SRob Herring 27*724ba675SRob Herring reg_vddio_codec: regulator-2V5 { 28*724ba675SRob Herring compatible = "regulator-fixed"; 29*724ba675SRob Herring regulator-name = "2P5V"; 30*724ba675SRob Herring regulator-min-microvolt = <2500000>; 31*724ba675SRob Herring regulator-max-microvolt = <2500000>; 32*724ba675SRob Herring regulator-always-on; 33*724ba675SRob Herring }; 34*724ba675SRob Herring}; 35*724ba675SRob Herring 36*724ba675SRob Herring&dspi0 { 37*724ba675SRob Herring bus-num = <0>; 38*724ba675SRob Herring status = "okay"; 39*724ba675SRob Herring 40*724ba675SRob Herring /* ADG704BRMZ 1:4 SPI mux/demux */ 41*724ba675SRob Herring sja1105: ethernet-switch@1 { 42*724ba675SRob Herring reg = <0x1>; 43*724ba675SRob Herring #address-cells = <1>; 44*724ba675SRob Herring #size-cells = <0>; 45*724ba675SRob Herring compatible = "nxp,sja1105t"; 46*724ba675SRob Herring /* 12 MHz */ 47*724ba675SRob Herring spi-max-frequency = <12000000>; 48*724ba675SRob Herring /* Sample data on trailing clock edge */ 49*724ba675SRob Herring spi-cpha; 50*724ba675SRob Herring /* SPI controller settings for SJA1105 timing requirements */ 51*724ba675SRob Herring fsl,spi-cs-sck-delay = <1000>; 52*724ba675SRob Herring fsl,spi-sck-cs-delay = <1000>; 53*724ba675SRob Herring 54*724ba675SRob Herring ports { 55*724ba675SRob Herring #address-cells = <1>; 56*724ba675SRob Herring #size-cells = <0>; 57*724ba675SRob Herring 58*724ba675SRob Herring port@0 { 59*724ba675SRob Herring /* ETH5 written on chassis */ 60*724ba675SRob Herring label = "swp5"; 61*724ba675SRob Herring phy-handle = <&rgmii_phy6>; 62*724ba675SRob Herring phy-mode = "rgmii-id"; 63*724ba675SRob Herring reg = <0>; 64*724ba675SRob Herring }; 65*724ba675SRob Herring 66*724ba675SRob Herring port@1 { 67*724ba675SRob Herring /* ETH2 written on chassis */ 68*724ba675SRob Herring label = "swp2"; 69*724ba675SRob Herring phy-handle = <&rgmii_phy3>; 70*724ba675SRob Herring phy-mode = "rgmii-id"; 71*724ba675SRob Herring reg = <1>; 72*724ba675SRob Herring }; 73*724ba675SRob Herring 74*724ba675SRob Herring port@2 { 75*724ba675SRob Herring /* ETH3 written on chassis */ 76*724ba675SRob Herring label = "swp3"; 77*724ba675SRob Herring phy-handle = <&rgmii_phy4>; 78*724ba675SRob Herring phy-mode = "rgmii-id"; 79*724ba675SRob Herring reg = <2>; 80*724ba675SRob Herring }; 81*724ba675SRob Herring 82*724ba675SRob Herring port@3 { 83*724ba675SRob Herring /* ETH4 written on chassis */ 84*724ba675SRob Herring label = "swp4"; 85*724ba675SRob Herring phy-handle = <&rgmii_phy5>; 86*724ba675SRob Herring phy-mode = "rgmii-id"; 87*724ba675SRob Herring reg = <3>; 88*724ba675SRob Herring }; 89*724ba675SRob Herring 90*724ba675SRob Herring port@4 { 91*724ba675SRob Herring /* Internal port connected to eth2 */ 92*724ba675SRob Herring ethernet = <&enet2>; 93*724ba675SRob Herring phy-mode = "rgmii"; 94*724ba675SRob Herring rx-internal-delay-ps = <0>; 95*724ba675SRob Herring tx-internal-delay-ps = <0>; 96*724ba675SRob Herring reg = <4>; 97*724ba675SRob Herring 98*724ba675SRob Herring fixed-link { 99*724ba675SRob Herring speed = <1000>; 100*724ba675SRob Herring full-duplex; 101*724ba675SRob Herring }; 102*724ba675SRob Herring }; 103*724ba675SRob Herring }; 104*724ba675SRob Herring }; 105*724ba675SRob Herring}; 106*724ba675SRob Herring 107*724ba675SRob Herring&enet0 { 108*724ba675SRob Herring tbi-handle = <&tbi0>; 109*724ba675SRob Herring phy-handle = <&sgmii_phy2>; 110*724ba675SRob Herring phy-mode = "sgmii"; 111*724ba675SRob Herring status = "okay"; 112*724ba675SRob Herring}; 113*724ba675SRob Herring 114*724ba675SRob Herring&enet1 { 115*724ba675SRob Herring tbi-handle = <&tbi1>; 116*724ba675SRob Herring phy-handle = <&sgmii_phy1>; 117*724ba675SRob Herring phy-mode = "sgmii"; 118*724ba675SRob Herring status = "okay"; 119*724ba675SRob Herring}; 120*724ba675SRob Herring 121*724ba675SRob Herring/* RGMII delays added via PCB traces */ 122*724ba675SRob Herring&enet2 { 123*724ba675SRob Herring phy-mode = "rgmii"; 124*724ba675SRob Herring status = "okay"; 125*724ba675SRob Herring 126*724ba675SRob Herring fixed-link { 127*724ba675SRob Herring speed = <1000>; 128*724ba675SRob Herring full-duplex; 129*724ba675SRob Herring }; 130*724ba675SRob Herring}; 131*724ba675SRob Herring 132*724ba675SRob Herring&esdhc { 133*724ba675SRob Herring status = "okay"; 134*724ba675SRob Herring}; 135*724ba675SRob Herring 136*724ba675SRob Herring&i2c0 { 137*724ba675SRob Herring status = "okay"; 138*724ba675SRob Herring 139*724ba675SRob Herring /* 3 axis accelerometer */ 140*724ba675SRob Herring accelerometer@1e { 141*724ba675SRob Herring compatible = "fsl,fxls8471"; 142*724ba675SRob Herring reg = <0x1e>; 143*724ba675SRob Herring }; 144*724ba675SRob Herring 145*724ba675SRob Herring /* Audio codec (SAI2) */ 146*724ba675SRob Herring audio-codec@2a { 147*724ba675SRob Herring compatible = "fsl,sgtl5000"; 148*724ba675SRob Herring VDDIO-supply = <®_vddio_codec>; 149*724ba675SRob Herring VDDA-supply = <®_vdda_codec>; 150*724ba675SRob Herring #sound-dai-cells = <0>; 151*724ba675SRob Herring clocks = <&sys_mclk>; 152*724ba675SRob Herring reg = <0x2a>; 153*724ba675SRob Herring }; 154*724ba675SRob Herring 155*724ba675SRob Herring /* Current sensing circuit for 1V VDDCORE PMIC rail */ 156*724ba675SRob Herring current-sensor@44 { 157*724ba675SRob Herring compatible = "ti,ina220"; 158*724ba675SRob Herring shunt-resistor = <1000>; 159*724ba675SRob Herring reg = <0x44>; 160*724ba675SRob Herring }; 161*724ba675SRob Herring 162*724ba675SRob Herring /* Current sensing circuit for 12V VCC rail */ 163*724ba675SRob Herring current-sensor@45 { 164*724ba675SRob Herring compatible = "ti,ina220"; 165*724ba675SRob Herring shunt-resistor = <1000>; 166*724ba675SRob Herring reg = <0x45>; 167*724ba675SRob Herring }; 168*724ba675SRob Herring 169*724ba675SRob Herring /* Thermal monitor - case */ 170*724ba675SRob Herring temperature-sensor@48 { 171*724ba675SRob Herring compatible = "national,lm75"; 172*724ba675SRob Herring reg = <0x48>; 173*724ba675SRob Herring }; 174*724ba675SRob Herring 175*724ba675SRob Herring /* Thermal monitor - chip */ 176*724ba675SRob Herring temperature-sensor@4c { 177*724ba675SRob Herring compatible = "ti,tmp451"; 178*724ba675SRob Herring reg = <0x4c>; 179*724ba675SRob Herring }; 180*724ba675SRob Herring 181*724ba675SRob Herring eeprom@51 { 182*724ba675SRob Herring compatible = "atmel,24c32"; 183*724ba675SRob Herring reg = <0x51>; 184*724ba675SRob Herring }; 185*724ba675SRob Herring 186*724ba675SRob Herring /* Unsupported devices: 187*724ba675SRob Herring * - FXAS21002C Gyroscope at 0x20 188*724ba675SRob Herring * - TI ADS7924 4-channel ADC at 0x49 189*724ba675SRob Herring */ 190*724ba675SRob Herring}; 191*724ba675SRob Herring 192*724ba675SRob Herring&ifc { 193*724ba675SRob Herring status = "disabled"; 194*724ba675SRob Herring}; 195*724ba675SRob Herring 196*724ba675SRob Herring&lpuart0 { 197*724ba675SRob Herring status = "okay"; 198*724ba675SRob Herring}; 199*724ba675SRob Herring 200*724ba675SRob Herring&lpuart3 { 201*724ba675SRob Herring status = "okay"; 202*724ba675SRob Herring}; 203*724ba675SRob Herring 204*724ba675SRob Herring&mdio0 { 205*724ba675SRob Herring /* AR8031 */ 206*724ba675SRob Herring sgmii_phy1: ethernet-phy@1 { 207*724ba675SRob Herring reg = <0x1>; 208*724ba675SRob Herring /* SGMII1_PHY_INT_B: connected to IRQ2, active low */ 209*724ba675SRob Herring interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>; 210*724ba675SRob Herring }; 211*724ba675SRob Herring 212*724ba675SRob Herring /* AR8031 */ 213*724ba675SRob Herring sgmii_phy2: ethernet-phy@2 { 214*724ba675SRob Herring reg = <0x2>; 215*724ba675SRob Herring /* SGMII2_PHY_INT_B: connected to IRQ2, active low */ 216*724ba675SRob Herring interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>; 217*724ba675SRob Herring }; 218*724ba675SRob Herring 219*724ba675SRob Herring /* BCM5464 quad PHY */ 220*724ba675SRob Herring rgmii_phy3: ethernet-phy@3 { 221*724ba675SRob Herring reg = <0x3>; 222*724ba675SRob Herring }; 223*724ba675SRob Herring 224*724ba675SRob Herring rgmii_phy4: ethernet-phy@4 { 225*724ba675SRob Herring reg = <0x4>; 226*724ba675SRob Herring }; 227*724ba675SRob Herring 228*724ba675SRob Herring rgmii_phy5: ethernet-phy@5 { 229*724ba675SRob Herring reg = <0x5>; 230*724ba675SRob Herring }; 231*724ba675SRob Herring 232*724ba675SRob Herring rgmii_phy6: ethernet-phy@6 { 233*724ba675SRob Herring reg = <0x6>; 234*724ba675SRob Herring }; 235*724ba675SRob Herring 236*724ba675SRob Herring /* SGMII PCS for enet0 */ 237*724ba675SRob Herring tbi0: tbi-phy@1f { 238*724ba675SRob Herring reg = <0x1f>; 239*724ba675SRob Herring device_type = "tbi-phy"; 240*724ba675SRob Herring }; 241*724ba675SRob Herring}; 242*724ba675SRob Herring 243*724ba675SRob Herring&mdio1 { 244*724ba675SRob Herring /* SGMII PCS for enet1 */ 245*724ba675SRob Herring tbi1: tbi-phy@1f { 246*724ba675SRob Herring reg = <0x1f>; 247*724ba675SRob Herring device_type = "tbi-phy"; 248*724ba675SRob Herring }; 249*724ba675SRob Herring}; 250*724ba675SRob Herring 251*724ba675SRob Herring&qspi { 252*724ba675SRob Herring status = "okay"; 253*724ba675SRob Herring 254*724ba675SRob Herring flash@0 { 255*724ba675SRob Herring /* Rev. A uses 64MB flash, Rev. B & C use 32MB flash */ 256*724ba675SRob Herring compatible = "jedec,spi-nor"; 257*724ba675SRob Herring spi-max-frequency = <20000000>; 258*724ba675SRob Herring #address-cells = <1>; 259*724ba675SRob Herring #size-cells = <1>; 260*724ba675SRob Herring reg = <0>; 261*724ba675SRob Herring 262*724ba675SRob Herring partitions { 263*724ba675SRob Herring compatible = "fixed-partitions"; 264*724ba675SRob Herring #address-cells = <1>; 265*724ba675SRob Herring #size-cells = <1>; 266*724ba675SRob Herring 267*724ba675SRob Herring partition@0 { 268*724ba675SRob Herring label = "RCW"; 269*724ba675SRob Herring reg = <0x0 0x40000>; 270*724ba675SRob Herring }; 271*724ba675SRob Herring 272*724ba675SRob Herring partition@40000 { 273*724ba675SRob Herring label = "U-Boot"; 274*724ba675SRob Herring reg = <0x40000 0x300000>; 275*724ba675SRob Herring }; 276*724ba675SRob Herring 277*724ba675SRob Herring partition@340000 { 278*724ba675SRob Herring label = "U-Boot Env"; 279*724ba675SRob Herring reg = <0x340000 0x100000>; 280*724ba675SRob Herring }; 281*724ba675SRob Herring }; 282*724ba675SRob Herring }; 283*724ba675SRob Herring}; 284*724ba675SRob Herring 285*724ba675SRob Herring&sai2 { 286*724ba675SRob Herring status = "okay"; 287*724ba675SRob Herring}; 288*724ba675SRob Herring 289*724ba675SRob Herring&sata { 290*724ba675SRob Herring status = "okay"; 291*724ba675SRob Herring}; 292*724ba675SRob Herring 293*724ba675SRob Herring&uart0 { 294*724ba675SRob Herring status = "okay"; 295*724ba675SRob Herring}; 296