1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0
2*724ba675SRob Herring
3*724ba675SRob Herring/ {
4*724ba675SRob Herring	memory-controller@7000f000 {
5*724ba675SRob Herring		emc-timings-0 {
6*724ba675SRob Herring			nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
7*724ba675SRob Herring
8*724ba675SRob Herring			timing-25500000 {
9*724ba675SRob Herring				clock-frequency = <25500000>;
10*724ba675SRob Herring
11*724ba675SRob Herring				nvidia,emem-configuration = <
12*724ba675SRob Herring					0x00020001 /* MC_EMEM_ARB_CFG */
13*724ba675SRob Herring					0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17*724ba675SRob Herring					0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
20*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
21*724ba675SRob Herring					0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
22*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
23*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
24*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
25*724ba675SRob Herring					0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
26*724ba675SRob Herring					0x06020102 /* MC_EMEM_ARB_DA_TURNS */
27*724ba675SRob Herring					0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
28*724ba675SRob Herring					0x74830303 /* MC_EMEM_ARB_MISC0 */
29*724ba675SRob Herring					0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
30*724ba675SRob Herring				>;
31*724ba675SRob Herring			};
32*724ba675SRob Herring
33*724ba675SRob Herring			timing-51000000 {
34*724ba675SRob Herring				clock-frequency = <51000000>;
35*724ba675SRob Herring
36*724ba675SRob Herring				nvidia,emem-configuration = <
37*724ba675SRob Herring					0x00010001 /* MC_EMEM_ARB_CFG */
38*724ba675SRob Herring					0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
39*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
40*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RP */
41*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_RC */
42*724ba675SRob Herring					0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
43*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
44*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
45*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
46*724ba675SRob Herring					0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
47*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
48*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
49*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
50*724ba675SRob Herring					0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
51*724ba675SRob Herring					0x06020102 /* MC_EMEM_ARB_DA_TURNS */
52*724ba675SRob Herring					0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
53*724ba675SRob Herring					0x73430303 /* MC_EMEM_ARB_MISC0 */
54*724ba675SRob Herring					0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
55*724ba675SRob Herring				>;
56*724ba675SRob Herring			};
57*724ba675SRob Herring
58*724ba675SRob Herring			timing-102000000 {
59*724ba675SRob Herring				clock-frequency = <102000000>;
60*724ba675SRob Herring
61*724ba675SRob Herring				nvidia,emem-configuration = <
62*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_CFG */
63*724ba675SRob Herring					0xc0000030 /* MC_EMEM_ARB_OUTSTANDING_REQ */
64*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
65*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RP */
66*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_TIMING_RC */
67*724ba675SRob Herring					0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
68*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
69*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
70*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
71*724ba675SRob Herring					0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
72*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
73*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
74*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
75*724ba675SRob Herring					0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
76*724ba675SRob Herring					0x06020102 /* MC_EMEM_ARB_DA_TURNS */
77*724ba675SRob Herring					0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
78*724ba675SRob Herring					0x72830504 /* MC_EMEM_ARB_MISC0 */
79*724ba675SRob Herring					0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
80*724ba675SRob Herring				>;
81*724ba675SRob Herring			};
82*724ba675SRob Herring
83*724ba675SRob Herring			timing-204000000 {
84*724ba675SRob Herring				clock-frequency = <204000000>;
85*724ba675SRob Herring
86*724ba675SRob Herring				nvidia,emem-configuration = <
87*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_CFG */
88*724ba675SRob Herring					0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
89*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
90*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RP */
91*724ba675SRob Herring					0x00000005 /* MC_EMEM_ARB_TIMING_RC */
92*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
93*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_TIMING_FAW */
94*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
95*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
96*724ba675SRob Herring					0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
97*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
98*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
99*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
100*724ba675SRob Herring					0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
101*724ba675SRob Herring					0x06020102 /* MC_EMEM_ARB_DA_TURNS */
102*724ba675SRob Herring					0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
103*724ba675SRob Herring					0x72440a06 /* MC_EMEM_ARB_MISC0 */
104*724ba675SRob Herring					0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
105*724ba675SRob Herring				>;
106*724ba675SRob Herring			};
107*724ba675SRob Herring
108*724ba675SRob Herring			timing-333500000 {
109*724ba675SRob Herring				clock-frequency = <333500000>;
110*724ba675SRob Herring
111*724ba675SRob Herring				nvidia,emem-configuration = <
112*724ba675SRob Herring					0x00000005 /* MC_EMEM_ARB_CFG */
113*724ba675SRob Herring					0xc000003d /* MC_EMEM_ARB_OUTSTANDING_REQ */
114*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
115*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_RP */
116*724ba675SRob Herring					0x00000008 /* MC_EMEM_ARB_TIMING_RC */
117*724ba675SRob Herring					0x00000004 /* MC_EMEM_ARB_TIMING_RAS */
118*724ba675SRob Herring					0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
119*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
120*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
121*724ba675SRob Herring					0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */
122*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
123*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
124*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
125*724ba675SRob Herring					0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
126*724ba675SRob Herring					0x06030202 /* MC_EMEM_ARB_DA_TURNS */
127*724ba675SRob Herring					0x000b0608 /* MC_EMEM_ARB_DA_COVERS */
128*724ba675SRob Herring					0x70850f09 /* MC_EMEM_ARB_MISC0 */
129*724ba675SRob Herring					0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
130*724ba675SRob Herring				>;
131*724ba675SRob Herring			};
132*724ba675SRob Herring
133*724ba675SRob Herring			timing-667000000 {
134*724ba675SRob Herring				clock-frequency = <667000000>;
135*724ba675SRob Herring
136*724ba675SRob Herring				nvidia,emem-configuration = <
137*724ba675SRob Herring					0x0000000a /* MC_EMEM_ARB_CFG */
138*724ba675SRob Herring					0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */
139*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
140*724ba675SRob Herring					0x00000004 /* MC_EMEM_ARB_TIMING_RP */
141*724ba675SRob Herring					0x00000010 /* MC_EMEM_ARB_TIMING_RC */
142*724ba675SRob Herring					0x0000000b /* MC_EMEM_ARB_TIMING_RAS */
143*724ba675SRob Herring					0x0000000a /* MC_EMEM_ARB_TIMING_FAW */
144*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
145*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
146*724ba675SRob Herring					0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */
147*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
148*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
149*724ba675SRob Herring					0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
150*724ba675SRob Herring					0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
151*724ba675SRob Herring					0x08040202 /* MC_EMEM_ARB_DA_TURNS */
152*724ba675SRob Herring					0x00130b10 /* MC_EMEM_ARB_DA_COVERS */
153*724ba675SRob Herring					0x70ea1f11 /* MC_EMEM_ARB_MISC0 */
154*724ba675SRob Herring					0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
155*724ba675SRob Herring				>;
156*724ba675SRob Herring			};
157*724ba675SRob Herring		};
158*724ba675SRob Herring
159*724ba675SRob Herring		emc-timings-1 {
160*724ba675SRob Herring			nvidia,ram-code = <1>; /* Hynix H5TC2G83CFR */
161*724ba675SRob Herring
162*724ba675SRob Herring			timing-25500000 {
163*724ba675SRob Herring				clock-frequency = <25500000>;
164*724ba675SRob Herring
165*724ba675SRob Herring				nvidia,emem-configuration = <
166*724ba675SRob Herring					0x00020001 /* MC_EMEM_ARB_CFG */
167*724ba675SRob Herring					0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
168*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
169*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RP */
170*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_RC */
171*724ba675SRob Herring					0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
172*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
173*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
174*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
175*724ba675SRob Herring					0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
176*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
177*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
178*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
179*724ba675SRob Herring					0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
180*724ba675SRob Herring					0x06020102 /* MC_EMEM_ARB_DA_TURNS */
181*724ba675SRob Herring					0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
182*724ba675SRob Herring					0x74830303 /* MC_EMEM_ARB_MISC0 */
183*724ba675SRob Herring					0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
184*724ba675SRob Herring				>;
185*724ba675SRob Herring			};
186*724ba675SRob Herring
187*724ba675SRob Herring			timing-51000000 {
188*724ba675SRob Herring				clock-frequency = <51000000>;
189*724ba675SRob Herring
190*724ba675SRob Herring				nvidia,emem-configuration = <
191*724ba675SRob Herring					0x00010001 /* MC_EMEM_ARB_CFG */
192*724ba675SRob Herring					0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
193*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
194*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RP */
195*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_RC */
196*724ba675SRob Herring					0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
197*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
198*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
199*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
200*724ba675SRob Herring					0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
201*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
202*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
203*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
204*724ba675SRob Herring					0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
205*724ba675SRob Herring					0x06020102 /* MC_EMEM_ARB_DA_TURNS */
206*724ba675SRob Herring					0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
207*724ba675SRob Herring					0x73430303 /* MC_EMEM_ARB_MISC0 */
208*724ba675SRob Herring					0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
209*724ba675SRob Herring				>;
210*724ba675SRob Herring			};
211*724ba675SRob Herring
212*724ba675SRob Herring			timing-102000000 {
213*724ba675SRob Herring				clock-frequency = <102000000>;
214*724ba675SRob Herring
215*724ba675SRob Herring				nvidia,emem-configuration = <
216*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_CFG */
217*724ba675SRob Herring					0xc0000030 /* MC_EMEM_ARB_OUTSTANDING_REQ */
218*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
219*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RP */
220*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_TIMING_RC */
221*724ba675SRob Herring					0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
222*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
223*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
224*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
225*724ba675SRob Herring					0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
226*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
227*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
228*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
229*724ba675SRob Herring					0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
230*724ba675SRob Herring					0x06020102 /* MC_EMEM_ARB_DA_TURNS */
231*724ba675SRob Herring					0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
232*724ba675SRob Herring					0x72830504 /* MC_EMEM_ARB_MISC0 */
233*724ba675SRob Herring					0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
234*724ba675SRob Herring				>;
235*724ba675SRob Herring			};
236*724ba675SRob Herring
237*724ba675SRob Herring			timing-204000000 {
238*724ba675SRob Herring				clock-frequency = <204000000>;
239*724ba675SRob Herring
240*724ba675SRob Herring				nvidia,emem-configuration = <
241*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_CFG */
242*724ba675SRob Herring					0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
243*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
244*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RP */
245*724ba675SRob Herring					0x00000005 /* MC_EMEM_ARB_TIMING_RC */
246*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
247*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_TIMING_FAW */
248*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
249*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
250*724ba675SRob Herring					0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
251*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
252*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
253*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
254*724ba675SRob Herring					0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
255*724ba675SRob Herring					0x06020102 /* MC_EMEM_ARB_DA_TURNS */
256*724ba675SRob Herring					0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
257*724ba675SRob Herring					0x72440a06 /* MC_EMEM_ARB_MISC0 */
258*724ba675SRob Herring					0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
259*724ba675SRob Herring				>;
260*724ba675SRob Herring			};
261*724ba675SRob Herring
262*724ba675SRob Herring			timing-333500000 {
263*724ba675SRob Herring				clock-frequency = <333500000>;
264*724ba675SRob Herring
265*724ba675SRob Herring				nvidia,emem-configuration = <
266*724ba675SRob Herring					0x00000005 /* MC_EMEM_ARB_CFG */
267*724ba675SRob Herring					0xc000003d /* MC_EMEM_ARB_OUTSTANDING_REQ */
268*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
269*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_RP */
270*724ba675SRob Herring					0x00000008 /* MC_EMEM_ARB_TIMING_RC */
271*724ba675SRob Herring					0x00000004 /* MC_EMEM_ARB_TIMING_RAS */
272*724ba675SRob Herring					0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
273*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
274*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
275*724ba675SRob Herring					0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */
276*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
277*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
278*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
279*724ba675SRob Herring					0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
280*724ba675SRob Herring					0x06030202 /* MC_EMEM_ARB_DA_TURNS */
281*724ba675SRob Herring					0x000b0608 /* MC_EMEM_ARB_DA_COVERS */
282*724ba675SRob Herring					0x70850f09 /* MC_EMEM_ARB_MISC0 */
283*724ba675SRob Herring					0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
284*724ba675SRob Herring				>;
285*724ba675SRob Herring			};
286*724ba675SRob Herring
287*724ba675SRob Herring			timing-667000000 {
288*724ba675SRob Herring				clock-frequency = <667000000>;
289*724ba675SRob Herring
290*724ba675SRob Herring				nvidia,emem-configuration = <
291*724ba675SRob Herring					0x0000000a /* MC_EMEM_ARB_CFG */
292*724ba675SRob Herring					0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */
293*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
294*724ba675SRob Herring					0x00000004 /* MC_EMEM_ARB_TIMING_RP */
295*724ba675SRob Herring					0x00000010 /* MC_EMEM_ARB_TIMING_RC */
296*724ba675SRob Herring					0x0000000b /* MC_EMEM_ARB_TIMING_RAS */
297*724ba675SRob Herring					0x0000000a /* MC_EMEM_ARB_TIMING_FAW */
298*724ba675SRob Herring					0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
299*724ba675SRob Herring					0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
300*724ba675SRob Herring					0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */
301*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
302*724ba675SRob Herring					0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
303*724ba675SRob Herring					0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
304*724ba675SRob Herring					0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
305*724ba675SRob Herring					0x08040202 /* MC_EMEM_ARB_DA_TURNS */
306*724ba675SRob Herring					0x00130b10 /* MC_EMEM_ARB_DA_COVERS */
307*724ba675SRob Herring					0x70ea1f11 /* MC_EMEM_ARB_MISC0 */
308*724ba675SRob Herring					0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
309*724ba675SRob Herring				>;
310*724ba675SRob Herring			};
311*724ba675SRob Herring		};
312*724ba675SRob Herring	};
313*724ba675SRob Herring
314*724ba675SRob Herring	memory-controller@7000f400 {
315*724ba675SRob Herring		emc-timings-0 {
316*724ba675SRob Herring			nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
317*724ba675SRob Herring
318*724ba675SRob Herring			timing-25500000 {
319*724ba675SRob Herring				clock-frequency = <25500000>;
320*724ba675SRob Herring
321*724ba675SRob Herring				nvidia,emc-auto-cal-interval = <0x001fffff>;
322*724ba675SRob Herring				nvidia,emc-mode-1 = <0x80100003>;
323*724ba675SRob Herring				nvidia,emc-mode-2 = <0x80200008>;
324*724ba675SRob Herring				nvidia,emc-mode-reset = <0x80001221>;
325*724ba675SRob Herring				nvidia,emc-zcal-cnt-long = <0x00000040>;
326*724ba675SRob Herring				nvidia,emc-cfg-dyn-self-ref;
327*724ba675SRob Herring				nvidia,emc-cfg-periodic-qrst;
328*724ba675SRob Herring
329*724ba675SRob Herring				nvidia,emc-configuration = <
330*724ba675SRob Herring					0x00000001 /* EMC_RC */
331*724ba675SRob Herring					0x00000004 /* EMC_RFC */
332*724ba675SRob Herring					0x00000000 /* EMC_RAS */
333*724ba675SRob Herring					0x00000000 /* EMC_RP */
334*724ba675SRob Herring					0x00000002 /* EMC_R2W */
335*724ba675SRob Herring					0x0000000a /* EMC_W2R */
336*724ba675SRob Herring					0x00000005 /* EMC_R2P */
337*724ba675SRob Herring					0x0000000b /* EMC_W2P */
338*724ba675SRob Herring					0x00000000 /* EMC_RD_RCD */
339*724ba675SRob Herring					0x00000000 /* EMC_WR_RCD */
340*724ba675SRob Herring					0x00000003 /* EMC_RRD */
341*724ba675SRob Herring					0x00000001 /* EMC_REXT */
342*724ba675SRob Herring					0x00000000 /* EMC_WEXT */
343*724ba675SRob Herring					0x00000005 /* EMC_WDV */
344*724ba675SRob Herring					0x00000005 /* EMC_QUSE */
345*724ba675SRob Herring					0x00000004 /* EMC_QRST */
346*724ba675SRob Herring					0x0000000a /* EMC_QSAFE */
347*724ba675SRob Herring					0x0000000b /* EMC_RDV */
348*724ba675SRob Herring					0x000000c0 /* EMC_REFRESH */
349*724ba675SRob Herring					0x00000000 /* EMC_BURST_REFRESH_NUM */
350*724ba675SRob Herring					0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
351*724ba675SRob Herring					0x00000002 /* EMC_PDEX2WR */
352*724ba675SRob Herring					0x00000002 /* EMC_PDEX2RD */
353*724ba675SRob Herring					0x00000001 /* EMC_PCHG2PDEN */
354*724ba675SRob Herring					0x00000000 /* EMC_ACT2PDEN */
355*724ba675SRob Herring					0x00000007 /* EMC_AR2PDEN */
356*724ba675SRob Herring					0x0000000f /* EMC_RW2PDEN */
357*724ba675SRob Herring					0x00000005 /* EMC_TXSR */
358*724ba675SRob Herring					0x00000005 /* EMC_TXSRDLL */
359*724ba675SRob Herring					0x00000004 /* EMC_TCKE */
360*724ba675SRob Herring					0x00000001 /* EMC_TFAW */
361*724ba675SRob Herring					0x00000000 /* EMC_TRPAB */
362*724ba675SRob Herring					0x00000004 /* EMC_TCLKSTABLE */
363*724ba675SRob Herring					0x00000005 /* EMC_TCLKSTOP */
364*724ba675SRob Herring					0x000000c7 /* EMC_TREFBW */
365*724ba675SRob Herring					0x00000006 /* EMC_QUSE_EXTRA */
366*724ba675SRob Herring					0x00000004 /* EMC_FBIO_CFG6 */
367*724ba675SRob Herring					0x00000000 /* EMC_ODT_WRITE */
368*724ba675SRob Herring					0x00000000 /* EMC_ODT_READ */
369*724ba675SRob Herring					0x00004288 /* EMC_FBIO_CFG5 */
370*724ba675SRob Herring					0x007800a4 /* EMC_CFG_DIG_DLL */
371*724ba675SRob Herring					0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
372*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS0 */
373*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS1 */
374*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS2 */
375*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS3 */
376*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS4 */
377*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS5 */
378*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS6 */
379*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS7 */
380*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE0 */
381*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE1 */
382*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE2 */
383*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE3 */
384*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE4 */
385*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE5 */
386*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE6 */
387*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE7 */
388*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
389*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
390*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
391*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
392*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
393*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
394*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
395*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
396*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ0 */
397*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ1 */
398*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ2 */
399*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ3 */
400*724ba675SRob Herring					0x000002a0 /* EMC_XM2CMDPADCTRL */
401*724ba675SRob Herring					0x0800211c /* EMC_XM2DQSPADCTRL2 */
402*724ba675SRob Herring					0x00000000 /* EMC_XM2DQPADCTRL2 */
403*724ba675SRob Herring					0x77fff884 /* EMC_XM2CLKPADCTRL */
404*724ba675SRob Herring					0x01f1f108 /* EMC_XM2COMPPADCTRL */
405*724ba675SRob Herring					0x05057404 /* EMC_XM2VTTGENPADCTRL */
406*724ba675SRob Herring					0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
407*724ba675SRob Herring					0x08000168 /* EMC_XM2QUSEPADCTRL */
408*724ba675SRob Herring					0x08000000 /* EMC_XM2DQSPADCTRL3 */
409*724ba675SRob Herring					0x00000802 /* EMC_CTT_TERM_CTRL */
410*724ba675SRob Herring					0x00000000 /* EMC_ZCAL_INTERVAL */
411*724ba675SRob Herring					0x00000040 /* EMC_ZCAL_WAIT_CNT */
412*724ba675SRob Herring					0x000c000c /* EMC_MRS_WAIT_CNT */
413*724ba675SRob Herring					0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
414*724ba675SRob Herring					0x00000000 /* EMC_CTT */
415*724ba675SRob Herring					0x00000000 /* EMC_CTT_DURATION */
416*724ba675SRob Herring					0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
417*724ba675SRob Herring					0xe8000000 /* EMC_FBIO_SPARE */
418*724ba675SRob Herring					0xff00ff00 /* EMC_CFG_RSV */
419*724ba675SRob Herring				>;
420*724ba675SRob Herring			};
421*724ba675SRob Herring
422*724ba675SRob Herring			timing-51000000 {
423*724ba675SRob Herring				clock-frequency = <51000000>;
424*724ba675SRob Herring
425*724ba675SRob Herring				nvidia,emc-auto-cal-interval = <0x001fffff>;
426*724ba675SRob Herring				nvidia,emc-mode-1 = <0x80100003>;
427*724ba675SRob Herring				nvidia,emc-mode-2 = <0x80200008>;
428*724ba675SRob Herring				nvidia,emc-mode-reset = <0x80001221>;
429*724ba675SRob Herring				nvidia,emc-zcal-cnt-long = <0x00000040>;
430*724ba675SRob Herring				nvidia,emc-cfg-dyn-self-ref;
431*724ba675SRob Herring				nvidia,emc-cfg-periodic-qrst;
432*724ba675SRob Herring
433*724ba675SRob Herring				nvidia,emc-configuration = <
434*724ba675SRob Herring					0x00000002 /* EMC_RC */
435*724ba675SRob Herring					0x00000008 /* EMC_RFC */
436*724ba675SRob Herring					0x00000001 /* EMC_RAS */
437*724ba675SRob Herring					0x00000000 /* EMC_RP */
438*724ba675SRob Herring					0x00000002 /* EMC_R2W */
439*724ba675SRob Herring					0x0000000a /* EMC_W2R */
440*724ba675SRob Herring					0x00000005 /* EMC_R2P */
441*724ba675SRob Herring					0x0000000b /* EMC_W2P */
442*724ba675SRob Herring					0x00000000 /* EMC_RD_RCD */
443*724ba675SRob Herring					0x00000000 /* EMC_WR_RCD */
444*724ba675SRob Herring					0x00000003 /* EMC_RRD */
445*724ba675SRob Herring					0x00000001 /* EMC_REXT */
446*724ba675SRob Herring					0x00000000 /* EMC_WEXT */
447*724ba675SRob Herring					0x00000005 /* EMC_WDV */
448*724ba675SRob Herring					0x00000005 /* EMC_QUSE */
449*724ba675SRob Herring					0x00000004 /* EMC_QRST */
450*724ba675SRob Herring					0x0000000a /* EMC_QSAFE */
451*724ba675SRob Herring					0x0000000b /* EMC_RDV */
452*724ba675SRob Herring					0x00000181 /* EMC_REFRESH */
453*724ba675SRob Herring					0x00000000 /* EMC_BURST_REFRESH_NUM */
454*724ba675SRob Herring					0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
455*724ba675SRob Herring					0x00000002 /* EMC_PDEX2WR */
456*724ba675SRob Herring					0x00000002 /* EMC_PDEX2RD */
457*724ba675SRob Herring					0x00000001 /* EMC_PCHG2PDEN */
458*724ba675SRob Herring					0x00000000 /* EMC_ACT2PDEN */
459*724ba675SRob Herring					0x00000007 /* EMC_AR2PDEN */
460*724ba675SRob Herring					0x0000000f /* EMC_RW2PDEN */
461*724ba675SRob Herring					0x00000009 /* EMC_TXSR */
462*724ba675SRob Herring					0x00000009 /* EMC_TXSRDLL */
463*724ba675SRob Herring					0x00000004 /* EMC_TCKE */
464*724ba675SRob Herring					0x00000002 /* EMC_TFAW */
465*724ba675SRob Herring					0x00000000 /* EMC_TRPAB */
466*724ba675SRob Herring					0x00000004 /* EMC_TCLKSTABLE */
467*724ba675SRob Herring					0x00000005 /* EMC_TCLKSTOP */
468*724ba675SRob Herring					0x0000018e /* EMC_TREFBW */
469*724ba675SRob Herring					0x00000006 /* EMC_QUSE_EXTRA */
470*724ba675SRob Herring					0x00000004 /* EMC_FBIO_CFG6 */
471*724ba675SRob Herring					0x00000000 /* EMC_ODT_WRITE */
472*724ba675SRob Herring					0x00000000 /* EMC_ODT_READ */
473*724ba675SRob Herring					0x00004288 /* EMC_FBIO_CFG5 */
474*724ba675SRob Herring					0x007800a4 /* EMC_CFG_DIG_DLL */
475*724ba675SRob Herring					0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
476*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS0 */
477*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS1 */
478*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS2 */
479*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS3 */
480*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS4 */
481*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS5 */
482*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS6 */
483*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS7 */
484*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE0 */
485*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE1 */
486*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE2 */
487*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE3 */
488*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE4 */
489*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE5 */
490*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE6 */
491*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE7 */
492*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
493*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
494*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
495*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
496*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
497*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
498*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
499*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
500*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ0 */
501*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ1 */
502*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ2 */
503*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ3 */
504*724ba675SRob Herring					0x000002a0 /* EMC_XM2CMDPADCTRL */
505*724ba675SRob Herring					0x0800211c /* EMC_XM2DQSPADCTRL2 */
506*724ba675SRob Herring					0x00000000 /* EMC_XM2DQPADCTRL2 */
507*724ba675SRob Herring					0x77fff884 /* EMC_XM2CLKPADCTRL */
508*724ba675SRob Herring					0x01f1f108 /* EMC_XM2COMPPADCTRL */
509*724ba675SRob Herring					0x05057404 /* EMC_XM2VTTGENPADCTRL */
510*724ba675SRob Herring					0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
511*724ba675SRob Herring					0x08000168 /* EMC_XM2QUSEPADCTRL */
512*724ba675SRob Herring					0x08000000 /* EMC_XM2DQSPADCTRL3 */
513*724ba675SRob Herring					0x00000802 /* EMC_CTT_TERM_CTRL */
514*724ba675SRob Herring					0x00000000 /* EMC_ZCAL_INTERVAL */
515*724ba675SRob Herring					0x00000040 /* EMC_ZCAL_WAIT_CNT */
516*724ba675SRob Herring					0x000c000c /* EMC_MRS_WAIT_CNT */
517*724ba675SRob Herring					0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
518*724ba675SRob Herring					0x00000000 /* EMC_CTT */
519*724ba675SRob Herring					0x00000000 /* EMC_CTT_DURATION */
520*724ba675SRob Herring					0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
521*724ba675SRob Herring					0xe8000000 /* EMC_FBIO_SPARE */
522*724ba675SRob Herring					0xff00ff00 /* EMC_CFG_RSV */
523*724ba675SRob Herring				>;
524*724ba675SRob Herring			};
525*724ba675SRob Herring
526*724ba675SRob Herring			timing-102000000 {
527*724ba675SRob Herring				clock-frequency = <102000000>;
528*724ba675SRob Herring
529*724ba675SRob Herring				nvidia,emc-auto-cal-interval = <0x001fffff>;
530*724ba675SRob Herring				nvidia,emc-mode-1 = <0x80100003>;
531*724ba675SRob Herring				nvidia,emc-mode-2 = <0x80200008>;
532*724ba675SRob Herring				nvidia,emc-mode-reset = <0x80001221>;
533*724ba675SRob Herring				nvidia,emc-zcal-cnt-long = <0x00000040>;
534*724ba675SRob Herring				nvidia,emc-cfg-dyn-self-ref;
535*724ba675SRob Herring				nvidia,emc-cfg-periodic-qrst;
536*724ba675SRob Herring
537*724ba675SRob Herring				nvidia,emc-configuration = <
538*724ba675SRob Herring					0x00000005 /* EMC_RC */
539*724ba675SRob Herring					0x00000010 /* EMC_RFC */
540*724ba675SRob Herring					0x00000003 /* EMC_RAS */
541*724ba675SRob Herring					0x00000001 /* EMC_RP */
542*724ba675SRob Herring					0x00000002 /* EMC_R2W */
543*724ba675SRob Herring					0x0000000a /* EMC_W2R */
544*724ba675SRob Herring					0x00000005 /* EMC_R2P */
545*724ba675SRob Herring					0x0000000b /* EMC_W2P */
546*724ba675SRob Herring					0x00000001 /* EMC_RD_RCD */
547*724ba675SRob Herring					0x00000001 /* EMC_WR_RCD */
548*724ba675SRob Herring					0x00000003 /* EMC_RRD */
549*724ba675SRob Herring					0x00000001 /* EMC_REXT */
550*724ba675SRob Herring					0x00000000 /* EMC_WEXT */
551*724ba675SRob Herring					0x00000005 /* EMC_WDV */
552*724ba675SRob Herring					0x00000005 /* EMC_QUSE */
553*724ba675SRob Herring					0x00000004 /* EMC_QRST */
554*724ba675SRob Herring					0x0000000a /* EMC_QSAFE */
555*724ba675SRob Herring					0x0000000b /* EMC_RDV */
556*724ba675SRob Herring					0x00000303 /* EMC_REFRESH */
557*724ba675SRob Herring					0x00000000 /* EMC_BURST_REFRESH_NUM */
558*724ba675SRob Herring					0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
559*724ba675SRob Herring					0x00000002 /* EMC_PDEX2WR */
560*724ba675SRob Herring					0x00000002 /* EMC_PDEX2RD */
561*724ba675SRob Herring					0x00000001 /* EMC_PCHG2PDEN */
562*724ba675SRob Herring					0x00000000 /* EMC_ACT2PDEN */
563*724ba675SRob Herring					0x00000007 /* EMC_AR2PDEN */
564*724ba675SRob Herring					0x0000000f /* EMC_RW2PDEN */
565*724ba675SRob Herring					0x00000012 /* EMC_TXSR */
566*724ba675SRob Herring					0x00000012 /* EMC_TXSRDLL */
567*724ba675SRob Herring					0x00000004 /* EMC_TCKE */
568*724ba675SRob Herring					0x00000004 /* EMC_TFAW */
569*724ba675SRob Herring					0x00000000 /* EMC_TRPAB */
570*724ba675SRob Herring					0x00000004 /* EMC_TCLKSTABLE */
571*724ba675SRob Herring					0x00000005 /* EMC_TCLKSTOP */
572*724ba675SRob Herring					0x0000031c /* EMC_TREFBW */
573*724ba675SRob Herring					0x00000006 /* EMC_QUSE_EXTRA */
574*724ba675SRob Herring					0x00000004 /* EMC_FBIO_CFG6 */
575*724ba675SRob Herring					0x00000000 /* EMC_ODT_WRITE */
576*724ba675SRob Herring					0x00000000 /* EMC_ODT_READ */
577*724ba675SRob Herring					0x00004288 /* EMC_FBIO_CFG5 */
578*724ba675SRob Herring					0x007800a4 /* EMC_CFG_DIG_DLL */
579*724ba675SRob Herring					0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
580*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS0 */
581*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS1 */
582*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS2 */
583*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS3 */
584*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS4 */
585*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS5 */
586*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS6 */
587*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS7 */
588*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE0 */
589*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE1 */
590*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE2 */
591*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE3 */
592*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE4 */
593*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE5 */
594*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE6 */
595*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE7 */
596*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
597*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
598*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
599*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
600*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
601*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
602*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
603*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
604*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ0 */
605*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ1 */
606*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ2 */
607*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ3 */
608*724ba675SRob Herring					0x000002a0 /* EMC_XM2CMDPADCTRL */
609*724ba675SRob Herring					0x0800211c /* EMC_XM2DQSPADCTRL2 */
610*724ba675SRob Herring					0x00000000 /* EMC_XM2DQPADCTRL2 */
611*724ba675SRob Herring					0x77fff884 /* EMC_XM2CLKPADCTRL */
612*724ba675SRob Herring					0x01f1f108 /* EMC_XM2COMPPADCTRL */
613*724ba675SRob Herring					0x05057404 /* EMC_XM2VTTGENPADCTRL */
614*724ba675SRob Herring					0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
615*724ba675SRob Herring					0x08000168 /* EMC_XM2QUSEPADCTRL */
616*724ba675SRob Herring					0x08000000 /* EMC_XM2DQSPADCTRL3 */
617*724ba675SRob Herring					0x00000802 /* EMC_CTT_TERM_CTRL */
618*724ba675SRob Herring					0x00000000 /* EMC_ZCAL_INTERVAL */
619*724ba675SRob Herring					0x00000040 /* EMC_ZCAL_WAIT_CNT */
620*724ba675SRob Herring					0x000c000c /* EMC_MRS_WAIT_CNT */
621*724ba675SRob Herring					0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
622*724ba675SRob Herring					0x00000000 /* EMC_CTT */
623*724ba675SRob Herring					0x00000000 /* EMC_CTT_DURATION */
624*724ba675SRob Herring					0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
625*724ba675SRob Herring					0xe8000000 /* EMC_FBIO_SPARE */
626*724ba675SRob Herring					0xff00ff00 /* EMC_CFG_RSV */
627*724ba675SRob Herring				>;
628*724ba675SRob Herring			};
629*724ba675SRob Herring
630*724ba675SRob Herring			timing-204000000 {
631*724ba675SRob Herring				clock-frequency = <204000000>;
632*724ba675SRob Herring
633*724ba675SRob Herring				nvidia,emc-auto-cal-interval = <0x001fffff>;
634*724ba675SRob Herring				nvidia,emc-mode-1 = <0x80100003>;
635*724ba675SRob Herring				nvidia,emc-mode-2 = <0x80200008>;
636*724ba675SRob Herring				nvidia,emc-mode-reset = <0x80001221>;
637*724ba675SRob Herring				nvidia,emc-zcal-cnt-long = <0x00000040>;
638*724ba675SRob Herring				nvidia,emc-cfg-dyn-self-ref;
639*724ba675SRob Herring				nvidia,emc-cfg-periodic-qrst;
640*724ba675SRob Herring
641*724ba675SRob Herring				nvidia,emc-configuration = <
642*724ba675SRob Herring					0x0000000a /* EMC_RC */
643*724ba675SRob Herring					0x00000020 /* EMC_RFC */
644*724ba675SRob Herring					0x00000007 /* EMC_RAS */
645*724ba675SRob Herring					0x00000002 /* EMC_RP */
646*724ba675SRob Herring					0x00000002 /* EMC_R2W */
647*724ba675SRob Herring					0x0000000a /* EMC_W2R */
648*724ba675SRob Herring					0x00000005 /* EMC_R2P */
649*724ba675SRob Herring					0x0000000b /* EMC_W2P */
650*724ba675SRob Herring					0x00000002 /* EMC_RD_RCD */
651*724ba675SRob Herring					0x00000002 /* EMC_WR_RCD */
652*724ba675SRob Herring					0x00000003 /* EMC_RRD */
653*724ba675SRob Herring					0x00000001 /* EMC_REXT */
654*724ba675SRob Herring					0x00000000 /* EMC_WEXT */
655*724ba675SRob Herring					0x00000005 /* EMC_WDV */
656*724ba675SRob Herring					0x00000005 /* EMC_QUSE */
657*724ba675SRob Herring					0x00000004 /* EMC_QRST */
658*724ba675SRob Herring					0x0000000a /* EMC_QSAFE */
659*724ba675SRob Herring					0x0000000b /* EMC_RDV */
660*724ba675SRob Herring					0x00000607 /* EMC_REFRESH */
661*724ba675SRob Herring					0x00000000 /* EMC_BURST_REFRESH_NUM */
662*724ba675SRob Herring					0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
663*724ba675SRob Herring					0x00000002 /* EMC_PDEX2WR */
664*724ba675SRob Herring					0x00000002 /* EMC_PDEX2RD */
665*724ba675SRob Herring					0x00000001 /* EMC_PCHG2PDEN */
666*724ba675SRob Herring					0x00000000 /* EMC_ACT2PDEN */
667*724ba675SRob Herring					0x00000007 /* EMC_AR2PDEN */
668*724ba675SRob Herring					0x0000000f /* EMC_RW2PDEN */
669*724ba675SRob Herring					0x00000023 /* EMC_TXSR */
670*724ba675SRob Herring					0x00000023 /* EMC_TXSRDLL */
671*724ba675SRob Herring					0x00000004 /* EMC_TCKE */
672*724ba675SRob Herring					0x00000007 /* EMC_TFAW */
673*724ba675SRob Herring					0x00000000 /* EMC_TRPAB */
674*724ba675SRob Herring					0x00000004 /* EMC_TCLKSTABLE */
675*724ba675SRob Herring					0x00000005 /* EMC_TCLKSTOP */
676*724ba675SRob Herring					0x00000638 /* EMC_TREFBW */
677*724ba675SRob Herring					0x00000006 /* EMC_QUSE_EXTRA */
678*724ba675SRob Herring					0x00000006 /* EMC_FBIO_CFG6 */
679*724ba675SRob Herring					0x00000000 /* EMC_ODT_WRITE */
680*724ba675SRob Herring					0x00000000 /* EMC_ODT_READ */
681*724ba675SRob Herring					0x00004288 /* EMC_FBIO_CFG5 */
682*724ba675SRob Herring					0x004400a4 /* EMC_CFG_DIG_DLL */
683*724ba675SRob Herring					0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
684*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQS0 */
685*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQS1 */
686*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQS2 */
687*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQS3 */
688*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQS4 */
689*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQS5 */
690*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQS6 */
691*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQS7 */
692*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE0 */
693*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE1 */
694*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE2 */
695*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE3 */
696*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE4 */
697*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE5 */
698*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE6 */
699*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE7 */
700*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
701*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
702*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
703*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
704*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
705*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
706*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
707*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
708*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQ0 */
709*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQ1 */
710*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQ2 */
711*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQ3 */
712*724ba675SRob Herring					0x000002a0 /* EMC_XM2CMDPADCTRL */
713*724ba675SRob Herring					0x0800211c /* EMC_XM2DQSPADCTRL2 */
714*724ba675SRob Herring					0x00000000 /* EMC_XM2DQPADCTRL2 */
715*724ba675SRob Herring					0x77fff884 /* EMC_XM2CLKPADCTRL */
716*724ba675SRob Herring					0x01f1f108 /* EMC_XM2COMPPADCTRL */
717*724ba675SRob Herring					0x05057404 /* EMC_XM2VTTGENPADCTRL */
718*724ba675SRob Herring					0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
719*724ba675SRob Herring					0x08000168 /* EMC_XM2QUSEPADCTRL */
720*724ba675SRob Herring					0x08000000 /* EMC_XM2DQSPADCTRL3 */
721*724ba675SRob Herring					0x00000802 /* EMC_CTT_TERM_CTRL */
722*724ba675SRob Herring					0x00020000 /* EMC_ZCAL_INTERVAL */
723*724ba675SRob Herring					0x00000100 /* EMC_ZCAL_WAIT_CNT */
724*724ba675SRob Herring					0x000c000c /* EMC_MRS_WAIT_CNT */
725*724ba675SRob Herring					0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
726*724ba675SRob Herring					0x00000000 /* EMC_CTT */
727*724ba675SRob Herring					0x00000000 /* EMC_CTT_DURATION */
728*724ba675SRob Herring					0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
729*724ba675SRob Herring					0xe8000000 /* EMC_FBIO_SPARE */
730*724ba675SRob Herring					0xff00ff00 /* EMC_CFG_RSV */
731*724ba675SRob Herring				>;
732*724ba675SRob Herring			};
733*724ba675SRob Herring
734*724ba675SRob Herring			timing-333500000 {
735*724ba675SRob Herring				clock-frequency = <333500000>;
736*724ba675SRob Herring
737*724ba675SRob Herring				nvidia,emc-auto-cal-interval = <0x001fffff>;
738*724ba675SRob Herring				nvidia,emc-mode-1 = <0x80100002>;
739*724ba675SRob Herring				nvidia,emc-mode-2 = <0x80200000>;
740*724ba675SRob Herring				nvidia,emc-mode-reset = <0x80000321>;
741*724ba675SRob Herring				nvidia,emc-zcal-cnt-long = <0x00000040>;
742*724ba675SRob Herring
743*724ba675SRob Herring				nvidia,emc-configuration = <
744*724ba675SRob Herring					0x0000000f /* EMC_RC */
745*724ba675SRob Herring					0x00000034 /* EMC_RFC */
746*724ba675SRob Herring					0x0000000a /* EMC_RAS */
747*724ba675SRob Herring					0x00000003 /* EMC_RP */
748*724ba675SRob Herring					0x00000003 /* EMC_R2W */
749*724ba675SRob Herring					0x00000008 /* EMC_W2R */
750*724ba675SRob Herring					0x00000002 /* EMC_R2P */
751*724ba675SRob Herring					0x00000009 /* EMC_W2P */
752*724ba675SRob Herring					0x00000003 /* EMC_RD_RCD */
753*724ba675SRob Herring					0x00000003 /* EMC_WR_RCD */
754*724ba675SRob Herring					0x00000002 /* EMC_RRD */
755*724ba675SRob Herring					0x00000001 /* EMC_REXT */
756*724ba675SRob Herring					0x00000000 /* EMC_WEXT */
757*724ba675SRob Herring					0x00000004 /* EMC_WDV */
758*724ba675SRob Herring					0x00000006 /* EMC_QUSE */
759*724ba675SRob Herring					0x00000004 /* EMC_QRST */
760*724ba675SRob Herring					0x0000000a /* EMC_QSAFE */
761*724ba675SRob Herring					0x0000000c /* EMC_RDV */
762*724ba675SRob Herring					0x000009e9 /* EMC_REFRESH */
763*724ba675SRob Herring					0x00000000 /* EMC_BURST_REFRESH_NUM */
764*724ba675SRob Herring					0x0000027a /* EMC_PRE_REFRESH_REQ_CNT */
765*724ba675SRob Herring					0x00000001 /* EMC_PDEX2WR */
766*724ba675SRob Herring					0x00000008 /* EMC_PDEX2RD */
767*724ba675SRob Herring					0x00000001 /* EMC_PCHG2PDEN */
768*724ba675SRob Herring					0x00000000 /* EMC_ACT2PDEN */
769*724ba675SRob Herring					0x00000007 /* EMC_AR2PDEN */
770*724ba675SRob Herring					0x0000000e /* EMC_RW2PDEN */
771*724ba675SRob Herring					0x00000039 /* EMC_TXSR */
772*724ba675SRob Herring					0x00000200 /* EMC_TXSRDLL */
773*724ba675SRob Herring					0x00000004 /* EMC_TCKE */
774*724ba675SRob Herring					0x0000000a /* EMC_TFAW */
775*724ba675SRob Herring					0x00000000 /* EMC_TRPAB */
776*724ba675SRob Herring					0x00000004 /* EMC_TCLKSTABLE */
777*724ba675SRob Herring					0x00000005 /* EMC_TCLKSTOP */
778*724ba675SRob Herring					0x00000a2a /* EMC_TREFBW */
779*724ba675SRob Herring					0x00000000 /* EMC_QUSE_EXTRA */
780*724ba675SRob Herring					0x00000004 /* EMC_FBIO_CFG6 */
781*724ba675SRob Herring					0x00000000 /* EMC_ODT_WRITE */
782*724ba675SRob Herring					0x00000000 /* EMC_ODT_READ */
783*724ba675SRob Herring					0x00007088 /* EMC_FBIO_CFG5 */
784*724ba675SRob Herring					0x002600a4 /* EMC_CFG_DIG_DLL */
785*724ba675SRob Herring					0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
786*724ba675SRob Herring					0x0003c000 /* EMC_DLL_XFORM_DQS0 */
787*724ba675SRob Herring					0x0003c000 /* EMC_DLL_XFORM_DQS1 */
788*724ba675SRob Herring					0x0003c000 /* EMC_DLL_XFORM_DQS2 */
789*724ba675SRob Herring					0x0003c000 /* EMC_DLL_XFORM_DQS3 */
790*724ba675SRob Herring					0x00014000 /* EMC_DLL_XFORM_DQS4 */
791*724ba675SRob Herring					0x00014000 /* EMC_DLL_XFORM_DQS5 */
792*724ba675SRob Herring					0x00014000 /* EMC_DLL_XFORM_DQS6 */
793*724ba675SRob Herring					0x00014000 /* EMC_DLL_XFORM_DQS7 */
794*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE0 */
795*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE1 */
796*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE2 */
797*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE3 */
798*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE4 */
799*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE5 */
800*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE6 */
801*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE7 */
802*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
803*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
804*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
805*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
806*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
807*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
808*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
809*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
810*724ba675SRob Herring					0x00048000 /* EMC_DLL_XFORM_DQ0 */
811*724ba675SRob Herring					0x00048000 /* EMC_DLL_XFORM_DQ1 */
812*724ba675SRob Herring					0x00048000 /* EMC_DLL_XFORM_DQ2 */
813*724ba675SRob Herring					0x00048000 /* EMC_DLL_XFORM_DQ3 */
814*724ba675SRob Herring					0x000002a0 /* EMC_XM2CMDPADCTRL */
815*724ba675SRob Herring					0x0800013d /* EMC_XM2DQSPADCTRL2 */
816*724ba675SRob Herring					0x00000000 /* EMC_XM2DQPADCTRL2 */
817*724ba675SRob Herring					0x77fff884 /* EMC_XM2CLKPADCTRL */
818*724ba675SRob Herring					0x01f1f508 /* EMC_XM2COMPPADCTRL */
819*724ba675SRob Herring					0x05057404 /* EMC_XM2VTTGENPADCTRL */
820*724ba675SRob Herring					0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
821*724ba675SRob Herring					0x080001e8 /* EMC_XM2QUSEPADCTRL */
822*724ba675SRob Herring					0x08000021 /* EMC_XM2DQSPADCTRL3 */
823*724ba675SRob Herring					0x00000802 /* EMC_CTT_TERM_CTRL */
824*724ba675SRob Herring					0x00020000 /* EMC_ZCAL_INTERVAL */
825*724ba675SRob Herring					0x00000100 /* EMC_ZCAL_WAIT_CNT */
826*724ba675SRob Herring					0x018b000c /* EMC_MRS_WAIT_CNT */
827*724ba675SRob Herring					0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
828*724ba675SRob Herring					0x00000000 /* EMC_CTT */
829*724ba675SRob Herring					0x00000000 /* EMC_CTT_DURATION */
830*724ba675SRob Herring					0x800014d4 /* EMC_DYN_SELF_REF_CONTROL */
831*724ba675SRob Herring					0xe8000000 /* EMC_FBIO_SPARE */
832*724ba675SRob Herring					0xff00ff89 /* EMC_CFG_RSV */
833*724ba675SRob Herring				>;
834*724ba675SRob Herring			};
835*724ba675SRob Herring
836*724ba675SRob Herring			timing-667000000 {
837*724ba675SRob Herring				clock-frequency = <667000000>;
838*724ba675SRob Herring
839*724ba675SRob Herring				nvidia,emc-auto-cal-interval = <0x001fffff>;
840*724ba675SRob Herring				nvidia,emc-mode-1 = <0x80100002>;
841*724ba675SRob Herring				nvidia,emc-mode-2 = <0x80200018>;
842*724ba675SRob Herring				nvidia,emc-mode-reset = <0x80000b71>;
843*724ba675SRob Herring				nvidia,emc-zcal-cnt-long = <0x00000040>;
844*724ba675SRob Herring				nvidia,emc-cfg-periodic-qrst;
845*724ba675SRob Herring
846*724ba675SRob Herring				nvidia,emc-configuration = <
847*724ba675SRob Herring					0x0000001f /* EMC_RC */
848*724ba675SRob Herring					0x00000069 /* EMC_RFC */
849*724ba675SRob Herring					0x00000017 /* EMC_RAS */
850*724ba675SRob Herring					0x00000007 /* EMC_RP */
851*724ba675SRob Herring					0x00000005 /* EMC_R2W */
852*724ba675SRob Herring					0x0000000c /* EMC_W2R */
853*724ba675SRob Herring					0x00000003 /* EMC_R2P */
854*724ba675SRob Herring					0x00000011 /* EMC_W2P */
855*724ba675SRob Herring					0x00000007 /* EMC_RD_RCD */
856*724ba675SRob Herring					0x00000007 /* EMC_WR_RCD */
857*724ba675SRob Herring					0x00000002 /* EMC_RRD */
858*724ba675SRob Herring					0x00000001 /* EMC_REXT */
859*724ba675SRob Herring					0x00000000 /* EMC_WEXT */
860*724ba675SRob Herring					0x00000007 /* EMC_WDV */
861*724ba675SRob Herring					0x0000000b /* EMC_QUSE */
862*724ba675SRob Herring					0x00000009 /* EMC_QRST */
863*724ba675SRob Herring					0x0000000b /* EMC_QSAFE */
864*724ba675SRob Herring					0x00000011 /* EMC_RDV */
865*724ba675SRob Herring					0x00001412 /* EMC_REFRESH */
866*724ba675SRob Herring					0x00000000 /* EMC_BURST_REFRESH_NUM */
867*724ba675SRob Herring					0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */
868*724ba675SRob Herring					0x00000002 /* EMC_PDEX2WR */
869*724ba675SRob Herring					0x0000000e /* EMC_PDEX2RD */
870*724ba675SRob Herring					0x00000001 /* EMC_PCHG2PDEN */
871*724ba675SRob Herring					0x00000000 /* EMC_ACT2PDEN */
872*724ba675SRob Herring					0x0000000c /* EMC_AR2PDEN */
873*724ba675SRob Herring					0x00000016 /* EMC_RW2PDEN */
874*724ba675SRob Herring					0x00000072 /* EMC_TXSR */
875*724ba675SRob Herring					0x00000200 /* EMC_TXSRDLL */
876*724ba675SRob Herring					0x00000005 /* EMC_TCKE */
877*724ba675SRob Herring					0x00000015 /* EMC_TFAW */
878*724ba675SRob Herring					0x00000000 /* EMC_TRPAB */
879*724ba675SRob Herring					0x00000006 /* EMC_TCLKSTABLE */
880*724ba675SRob Herring					0x00000007 /* EMC_TCLKSTOP */
881*724ba675SRob Herring					0x00001453 /* EMC_TREFBW */
882*724ba675SRob Herring					0x0000000c /* EMC_QUSE_EXTRA */
883*724ba675SRob Herring					0x00000004 /* EMC_FBIO_CFG6 */
884*724ba675SRob Herring					0x00000000 /* EMC_ODT_WRITE */
885*724ba675SRob Herring					0x00000000 /* EMC_ODT_READ */
886*724ba675SRob Herring					0x00005088 /* EMC_FBIO_CFG5 */
887*724ba675SRob Herring					0xf00b0191 /* EMC_CFG_DIG_DLL */
888*724ba675SRob Herring					0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
889*724ba675SRob Herring					0x00000008 /* EMC_DLL_XFORM_DQS0 */
890*724ba675SRob Herring					0x00000008 /* EMC_DLL_XFORM_DQS1 */
891*724ba675SRob Herring					0x00000008 /* EMC_DLL_XFORM_DQS2 */
892*724ba675SRob Herring					0x00000008 /* EMC_DLL_XFORM_DQS3 */
893*724ba675SRob Herring					0x0000000a /* EMC_DLL_XFORM_DQS4 */
894*724ba675SRob Herring					0x0000000a /* EMC_DLL_XFORM_DQS5 */
895*724ba675SRob Herring					0x0000000a /* EMC_DLL_XFORM_DQS6 */
896*724ba675SRob Herring					0x0000000a /* EMC_DLL_XFORM_DQS7 */
897*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE0 */
898*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE1 */
899*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE2 */
900*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE3 */
901*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE4 */
902*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE5 */
903*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE6 */
904*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE7 */
905*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
906*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
907*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
908*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
909*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
910*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
911*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
912*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
913*724ba675SRob Herring					0x0000000c /* EMC_DLL_XFORM_DQ0 */
914*724ba675SRob Herring					0x0000000c /* EMC_DLL_XFORM_DQ1 */
915*724ba675SRob Herring					0x0000000c /* EMC_DLL_XFORM_DQ2 */
916*724ba675SRob Herring					0x0000000c /* EMC_DLL_XFORM_DQ3 */
917*724ba675SRob Herring					0x000002a0 /* EMC_XM2CMDPADCTRL */
918*724ba675SRob Herring					0x0600013d /* EMC_XM2DQSPADCTRL2 */
919*724ba675SRob Herring					0x22220000 /* EMC_XM2DQPADCTRL2 */
920*724ba675SRob Herring					0x77fff884 /* EMC_XM2CLKPADCTRL */
921*724ba675SRob Herring					0x01f1f501 /* EMC_XM2COMPPADCTRL */
922*724ba675SRob Herring					0x07077404 /* EMC_XM2VTTGENPADCTRL */
923*724ba675SRob Herring					0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
924*724ba675SRob Herring					0x080001e8 /* EMC_XM2QUSEPADCTRL */
925*724ba675SRob Herring					0x0a000021 /* EMC_XM2DQSPADCTRL3 */
926*724ba675SRob Herring					0x00000802 /* EMC_CTT_TERM_CTRL */
927*724ba675SRob Herring					0x00020000 /* EMC_ZCAL_INTERVAL */
928*724ba675SRob Herring					0x00000100 /* EMC_ZCAL_WAIT_CNT */
929*724ba675SRob Herring					0x0156000c /* EMC_MRS_WAIT_CNT */
930*724ba675SRob Herring					0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
931*724ba675SRob Herring					0x00000000 /* EMC_CTT */
932*724ba675SRob Herring					0x00000000 /* EMC_CTT_DURATION */
933*724ba675SRob Herring					0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */
934*724ba675SRob Herring					0xf8000000 /* EMC_FBIO_SPARE */
935*724ba675SRob Herring					0xff00ff49 /* EMC_CFG_RSV */
936*724ba675SRob Herring				>;
937*724ba675SRob Herring			};
938*724ba675SRob Herring		};
939*724ba675SRob Herring
940*724ba675SRob Herring		emc-timings-1 {
941*724ba675SRob Herring			nvidia,ram-code = <1>; /* Hynix H5TC2G83CFR */
942*724ba675SRob Herring
943*724ba675SRob Herring			timing-25500000 {
944*724ba675SRob Herring				clock-frequency = <25500000>;
945*724ba675SRob Herring
946*724ba675SRob Herring				nvidia,emc-auto-cal-interval = <0x001fffff>;
947*724ba675SRob Herring				nvidia,emc-mode-1 = <0x80100003>;
948*724ba675SRob Herring				nvidia,emc-mode-2 = <0x80200008>;
949*724ba675SRob Herring				nvidia,emc-mode-reset = <0x80001221>;
950*724ba675SRob Herring				nvidia,emc-zcal-cnt-long = <0x00000040>;
951*724ba675SRob Herring				nvidia,emc-cfg-dyn-self-ref;
952*724ba675SRob Herring				nvidia,emc-cfg-periodic-qrst;
953*724ba675SRob Herring
954*724ba675SRob Herring				nvidia,emc-configuration = <
955*724ba675SRob Herring					0x00000001 /* EMC_RC */
956*724ba675SRob Herring					0x00000004 /* EMC_RFC */
957*724ba675SRob Herring					0x00000000 /* EMC_RAS */
958*724ba675SRob Herring					0x00000000 /* EMC_RP */
959*724ba675SRob Herring					0x00000002 /* EMC_R2W */
960*724ba675SRob Herring					0x0000000a /* EMC_W2R */
961*724ba675SRob Herring					0x00000005 /* EMC_R2P */
962*724ba675SRob Herring					0x0000000b /* EMC_W2P */
963*724ba675SRob Herring					0x00000000 /* EMC_RD_RCD */
964*724ba675SRob Herring					0x00000000 /* EMC_WR_RCD */
965*724ba675SRob Herring					0x00000003 /* EMC_RRD */
966*724ba675SRob Herring					0x00000001 /* EMC_REXT */
967*724ba675SRob Herring					0x00000000 /* EMC_WEXT */
968*724ba675SRob Herring					0x00000005 /* EMC_WDV */
969*724ba675SRob Herring					0x00000005 /* EMC_QUSE */
970*724ba675SRob Herring					0x00000004 /* EMC_QRST */
971*724ba675SRob Herring					0x0000000a /* EMC_QSAFE */
972*724ba675SRob Herring					0x0000000b /* EMC_RDV */
973*724ba675SRob Herring					0x000000c0 /* EMC_REFRESH */
974*724ba675SRob Herring					0x00000000 /* EMC_BURST_REFRESH_NUM */
975*724ba675SRob Herring					0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
976*724ba675SRob Herring					0x00000002 /* EMC_PDEX2WR */
977*724ba675SRob Herring					0x00000002 /* EMC_PDEX2RD */
978*724ba675SRob Herring					0x00000001 /* EMC_PCHG2PDEN */
979*724ba675SRob Herring					0x00000000 /* EMC_ACT2PDEN */
980*724ba675SRob Herring					0x00000007 /* EMC_AR2PDEN */
981*724ba675SRob Herring					0x0000000f /* EMC_RW2PDEN */
982*724ba675SRob Herring					0x00000005 /* EMC_TXSR */
983*724ba675SRob Herring					0x00000005 /* EMC_TXSRDLL */
984*724ba675SRob Herring					0x00000004 /* EMC_TCKE */
985*724ba675SRob Herring					0x00000001 /* EMC_TFAW */
986*724ba675SRob Herring					0x00000000 /* EMC_TRPAB */
987*724ba675SRob Herring					0x00000004 /* EMC_TCLKSTABLE */
988*724ba675SRob Herring					0x00000005 /* EMC_TCLKSTOP */
989*724ba675SRob Herring					0x000000c7 /* EMC_TREFBW */
990*724ba675SRob Herring					0x00000006 /* EMC_QUSE_EXTRA */
991*724ba675SRob Herring					0x00000004 /* EMC_FBIO_CFG6 */
992*724ba675SRob Herring					0x00000000 /* EMC_ODT_WRITE */
993*724ba675SRob Herring					0x00000000 /* EMC_ODT_READ */
994*724ba675SRob Herring					0x00004288 /* EMC_FBIO_CFG5 */
995*724ba675SRob Herring					0x007800a4 /* EMC_CFG_DIG_DLL */
996*724ba675SRob Herring					0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
997*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS0 */
998*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS1 */
999*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1000*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1001*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1002*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1003*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1004*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1005*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1006*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1007*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1008*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1009*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1010*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1011*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1012*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1013*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1014*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1015*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1016*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1017*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1018*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1019*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1020*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1021*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1022*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1023*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1024*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1025*724ba675SRob Herring					0x000002a0 /* EMC_XM2CMDPADCTRL */
1026*724ba675SRob Herring					0x0800211c /* EMC_XM2DQSPADCTRL2 */
1027*724ba675SRob Herring					0x00000000 /* EMC_XM2DQPADCTRL2 */
1028*724ba675SRob Herring					0x77fff884 /* EMC_XM2CLKPADCTRL */
1029*724ba675SRob Herring					0x01f1f108 /* EMC_XM2COMPPADCTRL */
1030*724ba675SRob Herring					0x05057404 /* EMC_XM2VTTGENPADCTRL */
1031*724ba675SRob Herring					0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1032*724ba675SRob Herring					0x08000168 /* EMC_XM2QUSEPADCTRL */
1033*724ba675SRob Herring					0x08000000 /* EMC_XM2DQSPADCTRL3 */
1034*724ba675SRob Herring					0x00000802 /* EMC_CTT_TERM_CTRL */
1035*724ba675SRob Herring					0x00000000 /* EMC_ZCAL_INTERVAL */
1036*724ba675SRob Herring					0x00000040 /* EMC_ZCAL_WAIT_CNT */
1037*724ba675SRob Herring					0x000c000c /* EMC_MRS_WAIT_CNT */
1038*724ba675SRob Herring					0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1039*724ba675SRob Herring					0x00000000 /* EMC_CTT */
1040*724ba675SRob Herring					0x00000000 /* EMC_CTT_DURATION */
1041*724ba675SRob Herring					0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
1042*724ba675SRob Herring					0xe8000000 /* EMC_FBIO_SPARE */
1043*724ba675SRob Herring					0xff00ff00 /* EMC_CFG_RSV */
1044*724ba675SRob Herring				>;
1045*724ba675SRob Herring			};
1046*724ba675SRob Herring
1047*724ba675SRob Herring			timing-51000000 {
1048*724ba675SRob Herring				clock-frequency = <51000000>;
1049*724ba675SRob Herring
1050*724ba675SRob Herring				nvidia,emc-auto-cal-interval = <0x001fffff>;
1051*724ba675SRob Herring				nvidia,emc-mode-1 = <0x80100003>;
1052*724ba675SRob Herring				nvidia,emc-mode-2 = <0x80200008>;
1053*724ba675SRob Herring				nvidia,emc-mode-reset = <0x80001221>;
1054*724ba675SRob Herring				nvidia,emc-zcal-cnt-long = <0x00000040>;
1055*724ba675SRob Herring				nvidia,emc-cfg-dyn-self-ref;
1056*724ba675SRob Herring				nvidia,emc-cfg-periodic-qrst;
1057*724ba675SRob Herring
1058*724ba675SRob Herring				nvidia,emc-configuration = <
1059*724ba675SRob Herring					0x00000002 /* EMC_RC */
1060*724ba675SRob Herring					0x00000008 /* EMC_RFC */
1061*724ba675SRob Herring					0x00000001 /* EMC_RAS */
1062*724ba675SRob Herring					0x00000000 /* EMC_RP */
1063*724ba675SRob Herring					0x00000002 /* EMC_R2W */
1064*724ba675SRob Herring					0x0000000a /* EMC_W2R */
1065*724ba675SRob Herring					0x00000005 /* EMC_R2P */
1066*724ba675SRob Herring					0x0000000b /* EMC_W2P */
1067*724ba675SRob Herring					0x00000000 /* EMC_RD_RCD */
1068*724ba675SRob Herring					0x00000000 /* EMC_WR_RCD */
1069*724ba675SRob Herring					0x00000003 /* EMC_RRD */
1070*724ba675SRob Herring					0x00000001 /* EMC_REXT */
1071*724ba675SRob Herring					0x00000000 /* EMC_WEXT */
1072*724ba675SRob Herring					0x00000005 /* EMC_WDV */
1073*724ba675SRob Herring					0x00000005 /* EMC_QUSE */
1074*724ba675SRob Herring					0x00000004 /* EMC_QRST */
1075*724ba675SRob Herring					0x0000000a /* EMC_QSAFE */
1076*724ba675SRob Herring					0x0000000b /* EMC_RDV */
1077*724ba675SRob Herring					0x00000181 /* EMC_REFRESH */
1078*724ba675SRob Herring					0x00000000 /* EMC_BURST_REFRESH_NUM */
1079*724ba675SRob Herring					0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
1080*724ba675SRob Herring					0x00000002 /* EMC_PDEX2WR */
1081*724ba675SRob Herring					0x00000002 /* EMC_PDEX2RD */
1082*724ba675SRob Herring					0x00000001 /* EMC_PCHG2PDEN */
1083*724ba675SRob Herring					0x00000000 /* EMC_ACT2PDEN */
1084*724ba675SRob Herring					0x00000007 /* EMC_AR2PDEN */
1085*724ba675SRob Herring					0x0000000f /* EMC_RW2PDEN */
1086*724ba675SRob Herring					0x00000009 /* EMC_TXSR */
1087*724ba675SRob Herring					0x00000009 /* EMC_TXSRDLL */
1088*724ba675SRob Herring					0x00000004 /* EMC_TCKE */
1089*724ba675SRob Herring					0x00000002 /* EMC_TFAW */
1090*724ba675SRob Herring					0x00000000 /* EMC_TRPAB */
1091*724ba675SRob Herring					0x00000004 /* EMC_TCLKSTABLE */
1092*724ba675SRob Herring					0x00000005 /* EMC_TCLKSTOP */
1093*724ba675SRob Herring					0x0000018e /* EMC_TREFBW */
1094*724ba675SRob Herring					0x00000006 /* EMC_QUSE_EXTRA */
1095*724ba675SRob Herring					0x00000004 /* EMC_FBIO_CFG6 */
1096*724ba675SRob Herring					0x00000000 /* EMC_ODT_WRITE */
1097*724ba675SRob Herring					0x00000000 /* EMC_ODT_READ */
1098*724ba675SRob Herring					0x00004288 /* EMC_FBIO_CFG5 */
1099*724ba675SRob Herring					0x007800a4 /* EMC_CFG_DIG_DLL */
1100*724ba675SRob Herring					0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1101*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1102*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1103*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1104*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1105*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1106*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1107*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1108*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1109*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1110*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1111*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1112*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1113*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1114*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1115*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1116*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1117*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1118*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1119*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1120*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1121*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1122*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1123*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1124*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1125*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1126*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1127*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1128*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1129*724ba675SRob Herring					0x000002a0 /* EMC_XM2CMDPADCTRL */
1130*724ba675SRob Herring					0x0800211c /* EMC_XM2DQSPADCTRL2 */
1131*724ba675SRob Herring					0x00000000 /* EMC_XM2DQPADCTRL2 */
1132*724ba675SRob Herring					0x77fff884 /* EMC_XM2CLKPADCTRL */
1133*724ba675SRob Herring					0x01f1f108 /* EMC_XM2COMPPADCTRL */
1134*724ba675SRob Herring					0x05057404 /* EMC_XM2VTTGENPADCTRL */
1135*724ba675SRob Herring					0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1136*724ba675SRob Herring					0x08000168 /* EMC_XM2QUSEPADCTRL */
1137*724ba675SRob Herring					0x08000000 /* EMC_XM2DQSPADCTRL3 */
1138*724ba675SRob Herring					0x00000802 /* EMC_CTT_TERM_CTRL */
1139*724ba675SRob Herring					0x00000000 /* EMC_ZCAL_INTERVAL */
1140*724ba675SRob Herring					0x00000040 /* EMC_ZCAL_WAIT_CNT */
1141*724ba675SRob Herring					0x000c000c /* EMC_MRS_WAIT_CNT */
1142*724ba675SRob Herring					0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1143*724ba675SRob Herring					0x00000000 /* EMC_CTT */
1144*724ba675SRob Herring					0x00000000 /* EMC_CTT_DURATION */
1145*724ba675SRob Herring					0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
1146*724ba675SRob Herring					0xe8000000 /* EMC_FBIO_SPARE */
1147*724ba675SRob Herring					0xff00ff00 /* EMC_CFG_RSV */
1148*724ba675SRob Herring				>;
1149*724ba675SRob Herring			};
1150*724ba675SRob Herring
1151*724ba675SRob Herring			timing-102000000 {
1152*724ba675SRob Herring				clock-frequency = <102000000>;
1153*724ba675SRob Herring
1154*724ba675SRob Herring				nvidia,emc-auto-cal-interval = <0x001fffff>;
1155*724ba675SRob Herring				nvidia,emc-mode-1 = <0x80100003>;
1156*724ba675SRob Herring				nvidia,emc-mode-2 = <0x80200008>;
1157*724ba675SRob Herring				nvidia,emc-mode-reset = <0x80001221>;
1158*724ba675SRob Herring				nvidia,emc-zcal-cnt-long = <0x00000040>;
1159*724ba675SRob Herring				nvidia,emc-cfg-dyn-self-ref;
1160*724ba675SRob Herring				nvidia,emc-cfg-periodic-qrst;
1161*724ba675SRob Herring
1162*724ba675SRob Herring				nvidia,emc-configuration = <
1163*724ba675SRob Herring					0x00000005 /* EMC_RC */
1164*724ba675SRob Herring					0x00000010 /* EMC_RFC */
1165*724ba675SRob Herring					0x00000003 /* EMC_RAS */
1166*724ba675SRob Herring					0x00000001 /* EMC_RP */
1167*724ba675SRob Herring					0x00000002 /* EMC_R2W */
1168*724ba675SRob Herring					0x0000000a /* EMC_W2R */
1169*724ba675SRob Herring					0x00000005 /* EMC_R2P */
1170*724ba675SRob Herring					0x0000000b /* EMC_W2P */
1171*724ba675SRob Herring					0x00000001 /* EMC_RD_RCD */
1172*724ba675SRob Herring					0x00000001 /* EMC_WR_RCD */
1173*724ba675SRob Herring					0x00000003 /* EMC_RRD */
1174*724ba675SRob Herring					0x00000001 /* EMC_REXT */
1175*724ba675SRob Herring					0x00000000 /* EMC_WEXT */
1176*724ba675SRob Herring					0x00000005 /* EMC_WDV */
1177*724ba675SRob Herring					0x00000005 /* EMC_QUSE */
1178*724ba675SRob Herring					0x00000004 /* EMC_QRST */
1179*724ba675SRob Herring					0x0000000a /* EMC_QSAFE */
1180*724ba675SRob Herring					0x0000000b /* EMC_RDV */
1181*724ba675SRob Herring					0x00000303 /* EMC_REFRESH */
1182*724ba675SRob Herring					0x00000000 /* EMC_BURST_REFRESH_NUM */
1183*724ba675SRob Herring					0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
1184*724ba675SRob Herring					0x00000002 /* EMC_PDEX2WR */
1185*724ba675SRob Herring					0x00000002 /* EMC_PDEX2RD */
1186*724ba675SRob Herring					0x00000001 /* EMC_PCHG2PDEN */
1187*724ba675SRob Herring					0x00000000 /* EMC_ACT2PDEN */
1188*724ba675SRob Herring					0x00000007 /* EMC_AR2PDEN */
1189*724ba675SRob Herring					0x0000000f /* EMC_RW2PDEN */
1190*724ba675SRob Herring					0x00000012 /* EMC_TXSR */
1191*724ba675SRob Herring					0x00000012 /* EMC_TXSRDLL */
1192*724ba675SRob Herring					0x00000004 /* EMC_TCKE */
1193*724ba675SRob Herring					0x00000004 /* EMC_TFAW */
1194*724ba675SRob Herring					0x00000000 /* EMC_TRPAB */
1195*724ba675SRob Herring					0x00000004 /* EMC_TCLKSTABLE */
1196*724ba675SRob Herring					0x00000005 /* EMC_TCLKSTOP */
1197*724ba675SRob Herring					0x0000031c /* EMC_TREFBW */
1198*724ba675SRob Herring					0x00000006 /* EMC_QUSE_EXTRA */
1199*724ba675SRob Herring					0x00000004 /* EMC_FBIO_CFG6 */
1200*724ba675SRob Herring					0x00000000 /* EMC_ODT_WRITE */
1201*724ba675SRob Herring					0x00000000 /* EMC_ODT_READ */
1202*724ba675SRob Herring					0x00004288 /* EMC_FBIO_CFG5 */
1203*724ba675SRob Herring					0x007800a4 /* EMC_CFG_DIG_DLL */
1204*724ba675SRob Herring					0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1205*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1206*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1207*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1208*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1209*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1210*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1211*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1212*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1213*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1214*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1215*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1216*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1217*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1218*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1219*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1220*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1221*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1222*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1223*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1224*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1225*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1226*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1227*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1228*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1229*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1230*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1231*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1232*724ba675SRob Herring					0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1233*724ba675SRob Herring					0x000002a0 /* EMC_XM2CMDPADCTRL */
1234*724ba675SRob Herring					0x0800211c /* EMC_XM2DQSPADCTRL2 */
1235*724ba675SRob Herring					0x00000000 /* EMC_XM2DQPADCTRL2 */
1236*724ba675SRob Herring					0x77fff884 /* EMC_XM2CLKPADCTRL */
1237*724ba675SRob Herring					0x01f1f108 /* EMC_XM2COMPPADCTRL */
1238*724ba675SRob Herring					0x05057404 /* EMC_XM2VTTGENPADCTRL */
1239*724ba675SRob Herring					0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1240*724ba675SRob Herring					0x08000168 /* EMC_XM2QUSEPADCTRL */
1241*724ba675SRob Herring					0x08000000 /* EMC_XM2DQSPADCTRL3 */
1242*724ba675SRob Herring					0x00000802 /* EMC_CTT_TERM_CTRL */
1243*724ba675SRob Herring					0x00000000 /* EMC_ZCAL_INTERVAL */
1244*724ba675SRob Herring					0x00000040 /* EMC_ZCAL_WAIT_CNT */
1245*724ba675SRob Herring					0x000c000c /* EMC_MRS_WAIT_CNT */
1246*724ba675SRob Herring					0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1247*724ba675SRob Herring					0x00000000 /* EMC_CTT */
1248*724ba675SRob Herring					0x00000000 /* EMC_CTT_DURATION */
1249*724ba675SRob Herring					0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
1250*724ba675SRob Herring					0xe8000000 /* EMC_FBIO_SPARE */
1251*724ba675SRob Herring					0xff00ff00 /* EMC_CFG_RSV */
1252*724ba675SRob Herring				>;
1253*724ba675SRob Herring			};
1254*724ba675SRob Herring
1255*724ba675SRob Herring			timing-204000000 {
1256*724ba675SRob Herring				clock-frequency = <204000000>;
1257*724ba675SRob Herring
1258*724ba675SRob Herring				nvidia,emc-auto-cal-interval = <0x001fffff>;
1259*724ba675SRob Herring				nvidia,emc-mode-1 = <0x80100003>;
1260*724ba675SRob Herring				nvidia,emc-mode-2 = <0x80200008>;
1261*724ba675SRob Herring				nvidia,emc-mode-reset = <0x80001221>;
1262*724ba675SRob Herring				nvidia,emc-zcal-cnt-long = <0x00000040>;
1263*724ba675SRob Herring				nvidia,emc-cfg-dyn-self-ref;
1264*724ba675SRob Herring				nvidia,emc-cfg-periodic-qrst;
1265*724ba675SRob Herring
1266*724ba675SRob Herring				nvidia,emc-configuration = <
1267*724ba675SRob Herring					0x0000000a /* EMC_RC */
1268*724ba675SRob Herring					0x00000020 /* EMC_RFC */
1269*724ba675SRob Herring					0x00000007 /* EMC_RAS */
1270*724ba675SRob Herring					0x00000002 /* EMC_RP */
1271*724ba675SRob Herring					0x00000002 /* EMC_R2W */
1272*724ba675SRob Herring					0x0000000a /* EMC_W2R */
1273*724ba675SRob Herring					0x00000005 /* EMC_R2P */
1274*724ba675SRob Herring					0x0000000b /* EMC_W2P */
1275*724ba675SRob Herring					0x00000002 /* EMC_RD_RCD */
1276*724ba675SRob Herring					0x00000002 /* EMC_WR_RCD */
1277*724ba675SRob Herring					0x00000003 /* EMC_RRD */
1278*724ba675SRob Herring					0x00000001 /* EMC_REXT */
1279*724ba675SRob Herring					0x00000000 /* EMC_WEXT */
1280*724ba675SRob Herring					0x00000005 /* EMC_WDV */
1281*724ba675SRob Herring					0x00000005 /* EMC_QUSE */
1282*724ba675SRob Herring					0x00000004 /* EMC_QRST */
1283*724ba675SRob Herring					0x0000000a /* EMC_QSAFE */
1284*724ba675SRob Herring					0x0000000b /* EMC_RDV */
1285*724ba675SRob Herring					0x00000607 /* EMC_REFRESH */
1286*724ba675SRob Herring					0x00000000 /* EMC_BURST_REFRESH_NUM */
1287*724ba675SRob Herring					0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
1288*724ba675SRob Herring					0x00000002 /* EMC_PDEX2WR */
1289*724ba675SRob Herring					0x00000002 /* EMC_PDEX2RD */
1290*724ba675SRob Herring					0x00000001 /* EMC_PCHG2PDEN */
1291*724ba675SRob Herring					0x00000000 /* EMC_ACT2PDEN */
1292*724ba675SRob Herring					0x00000007 /* EMC_AR2PDEN */
1293*724ba675SRob Herring					0x0000000f /* EMC_RW2PDEN */
1294*724ba675SRob Herring					0x00000023 /* EMC_TXSR */
1295*724ba675SRob Herring					0x00000023 /* EMC_TXSRDLL */
1296*724ba675SRob Herring					0x00000004 /* EMC_TCKE */
1297*724ba675SRob Herring					0x00000007 /* EMC_TFAW */
1298*724ba675SRob Herring					0x00000000 /* EMC_TRPAB */
1299*724ba675SRob Herring					0x00000004 /* EMC_TCLKSTABLE */
1300*724ba675SRob Herring					0x00000005 /* EMC_TCLKSTOP */
1301*724ba675SRob Herring					0x00000638 /* EMC_TREFBW */
1302*724ba675SRob Herring					0x00000006 /* EMC_QUSE_EXTRA */
1303*724ba675SRob Herring					0x00000006 /* EMC_FBIO_CFG6 */
1304*724ba675SRob Herring					0x00000000 /* EMC_ODT_WRITE */
1305*724ba675SRob Herring					0x00000000 /* EMC_ODT_READ */
1306*724ba675SRob Herring					0x00004288 /* EMC_FBIO_CFG5 */
1307*724ba675SRob Herring					0x004400a4 /* EMC_CFG_DIG_DLL */
1308*724ba675SRob Herring					0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1309*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQS0 */
1310*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQS1 */
1311*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQS2 */
1312*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQS3 */
1313*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQS4 */
1314*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQS5 */
1315*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQS6 */
1316*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQS7 */
1317*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1318*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1319*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1320*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1321*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1322*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1323*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1324*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1325*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1326*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1327*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1328*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1329*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1330*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1331*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1332*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1333*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQ0 */
1334*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQ1 */
1335*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQ2 */
1336*724ba675SRob Herring					0x00080000 /* EMC_DLL_XFORM_DQ3 */
1337*724ba675SRob Herring					0x000002a0 /* EMC_XM2CMDPADCTRL */
1338*724ba675SRob Herring					0x0800211c /* EMC_XM2DQSPADCTRL2 */
1339*724ba675SRob Herring					0x00000000 /* EMC_XM2DQPADCTRL2 */
1340*724ba675SRob Herring					0x77fff884 /* EMC_XM2CLKPADCTRL */
1341*724ba675SRob Herring					0x01f1f108 /* EMC_XM2COMPPADCTRL */
1342*724ba675SRob Herring					0x05057404 /* EMC_XM2VTTGENPADCTRL */
1343*724ba675SRob Herring					0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1344*724ba675SRob Herring					0x08000168 /* EMC_XM2QUSEPADCTRL */
1345*724ba675SRob Herring					0x08000000 /* EMC_XM2DQSPADCTRL3 */
1346*724ba675SRob Herring					0x00000802 /* EMC_CTT_TERM_CTRL */
1347*724ba675SRob Herring					0x00020000 /* EMC_ZCAL_INTERVAL */
1348*724ba675SRob Herring					0x00000100 /* EMC_ZCAL_WAIT_CNT */
1349*724ba675SRob Herring					0x000c000c /* EMC_MRS_WAIT_CNT */
1350*724ba675SRob Herring					0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1351*724ba675SRob Herring					0x00000000 /* EMC_CTT */
1352*724ba675SRob Herring					0x00000000 /* EMC_CTT_DURATION */
1353*724ba675SRob Herring					0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
1354*724ba675SRob Herring					0xe8000000 /* EMC_FBIO_SPARE */
1355*724ba675SRob Herring					0xff00ff00 /* EMC_CFG_RSV */
1356*724ba675SRob Herring				>;
1357*724ba675SRob Herring			};
1358*724ba675SRob Herring
1359*724ba675SRob Herring			timing-333500000 {
1360*724ba675SRob Herring				clock-frequency = <333500000>;
1361*724ba675SRob Herring
1362*724ba675SRob Herring				nvidia,emc-auto-cal-interval = <0x001fffff>;
1363*724ba675SRob Herring				nvidia,emc-mode-1 = <0x80100002>;
1364*724ba675SRob Herring				nvidia,emc-mode-2 = <0x80200000>;
1365*724ba675SRob Herring				nvidia,emc-mode-reset = <0x80000321>;
1366*724ba675SRob Herring				nvidia,emc-zcal-cnt-long = <0x00000040>;
1367*724ba675SRob Herring
1368*724ba675SRob Herring				nvidia,emc-configuration = <
1369*724ba675SRob Herring					0x0000000f /* EMC_RC */
1370*724ba675SRob Herring					0x00000034 /* EMC_RFC */
1371*724ba675SRob Herring					0x0000000a /* EMC_RAS */
1372*724ba675SRob Herring					0x00000003 /* EMC_RP */
1373*724ba675SRob Herring					0x00000003 /* EMC_R2W */
1374*724ba675SRob Herring					0x00000008 /* EMC_W2R */
1375*724ba675SRob Herring					0x00000002 /* EMC_R2P */
1376*724ba675SRob Herring					0x00000009 /* EMC_W2P */
1377*724ba675SRob Herring					0x00000003 /* EMC_RD_RCD */
1378*724ba675SRob Herring					0x00000003 /* EMC_WR_RCD */
1379*724ba675SRob Herring					0x00000002 /* EMC_RRD */
1380*724ba675SRob Herring					0x00000001 /* EMC_REXT */
1381*724ba675SRob Herring					0x00000000 /* EMC_WEXT */
1382*724ba675SRob Herring					0x00000004 /* EMC_WDV */
1383*724ba675SRob Herring					0x00000006 /* EMC_QUSE */
1384*724ba675SRob Herring					0x00000004 /* EMC_QRST */
1385*724ba675SRob Herring					0x0000000a /* EMC_QSAFE */
1386*724ba675SRob Herring					0x0000000c /* EMC_RDV */
1387*724ba675SRob Herring					0x000009e9 /* EMC_REFRESH */
1388*724ba675SRob Herring					0x00000000 /* EMC_BURST_REFRESH_NUM */
1389*724ba675SRob Herring					0x0000027a /* EMC_PRE_REFRESH_REQ_CNT */
1390*724ba675SRob Herring					0x00000001 /* EMC_PDEX2WR */
1391*724ba675SRob Herring					0x00000008 /* EMC_PDEX2RD */
1392*724ba675SRob Herring					0x00000001 /* EMC_PCHG2PDEN */
1393*724ba675SRob Herring					0x00000000 /* EMC_ACT2PDEN */
1394*724ba675SRob Herring					0x00000007 /* EMC_AR2PDEN */
1395*724ba675SRob Herring					0x0000000e /* EMC_RW2PDEN */
1396*724ba675SRob Herring					0x00000039 /* EMC_TXSR */
1397*724ba675SRob Herring					0x00000200 /* EMC_TXSRDLL */
1398*724ba675SRob Herring					0x00000004 /* EMC_TCKE */
1399*724ba675SRob Herring					0x0000000a /* EMC_TFAW */
1400*724ba675SRob Herring					0x00000000 /* EMC_TRPAB */
1401*724ba675SRob Herring					0x00000004 /* EMC_TCLKSTABLE */
1402*724ba675SRob Herring					0x00000005 /* EMC_TCLKSTOP */
1403*724ba675SRob Herring					0x00000a2a /* EMC_TREFBW */
1404*724ba675SRob Herring					0x00000000 /* EMC_QUSE_EXTRA */
1405*724ba675SRob Herring					0x00000004 /* EMC_FBIO_CFG6 */
1406*724ba675SRob Herring					0x00000000 /* EMC_ODT_WRITE */
1407*724ba675SRob Herring					0x00000000 /* EMC_ODT_READ */
1408*724ba675SRob Herring					0x00007088 /* EMC_FBIO_CFG5 */
1409*724ba675SRob Herring					0x002600a4 /* EMC_CFG_DIG_DLL */
1410*724ba675SRob Herring					0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1411*724ba675SRob Herring					0x0003c000 /* EMC_DLL_XFORM_DQS0 */
1412*724ba675SRob Herring					0x0003c000 /* EMC_DLL_XFORM_DQS1 */
1413*724ba675SRob Herring					0x0003c000 /* EMC_DLL_XFORM_DQS2 */
1414*724ba675SRob Herring					0x0003c000 /* EMC_DLL_XFORM_DQS3 */
1415*724ba675SRob Herring					0x00014000 /* EMC_DLL_XFORM_DQS4 */
1416*724ba675SRob Herring					0x00014000 /* EMC_DLL_XFORM_DQS5 */
1417*724ba675SRob Herring					0x00014000 /* EMC_DLL_XFORM_DQS6 */
1418*724ba675SRob Herring					0x00014000 /* EMC_DLL_XFORM_DQS7 */
1419*724ba675SRob Herring					0x00018000 /* EMC_DLL_XFORM_QUSE0 */
1420*724ba675SRob Herring					0x00018000 /* EMC_DLL_XFORM_QUSE1 */
1421*724ba675SRob Herring					0x00018000 /* EMC_DLL_XFORM_QUSE2 */
1422*724ba675SRob Herring					0x00018000 /* EMC_DLL_XFORM_QUSE3 */
1423*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1424*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1425*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1426*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1427*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1428*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1429*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1430*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1431*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1432*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1433*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1434*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1435*724ba675SRob Herring					0x00048000 /* EMC_DLL_XFORM_DQ0 */
1436*724ba675SRob Herring					0x00048000 /* EMC_DLL_XFORM_DQ1 */
1437*724ba675SRob Herring					0x00048000 /* EMC_DLL_XFORM_DQ2 */
1438*724ba675SRob Herring					0x00048000 /* EMC_DLL_XFORM_DQ3 */
1439*724ba675SRob Herring					0x000002a0 /* EMC_XM2CMDPADCTRL */
1440*724ba675SRob Herring					0x0600013d /* EMC_XM2DQSPADCTRL2 */
1441*724ba675SRob Herring					0x00000000 /* EMC_XM2DQPADCTRL2 */
1442*724ba675SRob Herring					0x77fff884 /* EMC_XM2CLKPADCTRL */
1443*724ba675SRob Herring					0x01f1f508 /* EMC_XM2COMPPADCTRL */
1444*724ba675SRob Herring					0x05057404 /* EMC_XM2VTTGENPADCTRL */
1445*724ba675SRob Herring					0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1446*724ba675SRob Herring					0x080001e8 /* EMC_XM2QUSEPADCTRL */
1447*724ba675SRob Herring					0x08000021 /* EMC_XM2DQSPADCTRL3 */
1448*724ba675SRob Herring					0x00000802 /* EMC_CTT_TERM_CTRL */
1449*724ba675SRob Herring					0x00020000 /* EMC_ZCAL_INTERVAL */
1450*724ba675SRob Herring					0x00000100 /* EMC_ZCAL_WAIT_CNT */
1451*724ba675SRob Herring					0x018b000c /* EMC_MRS_WAIT_CNT */
1452*724ba675SRob Herring					0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1453*724ba675SRob Herring					0x00000000 /* EMC_CTT */
1454*724ba675SRob Herring					0x00000000 /* EMC_CTT_DURATION */
1455*724ba675SRob Herring					0x800014d4 /* EMC_DYN_SELF_REF_CONTROL */
1456*724ba675SRob Herring					0xf8000000 /* EMC_FBIO_SPARE */
1457*724ba675SRob Herring					0xff00ff89 /* EMC_CFG_RSV */
1458*724ba675SRob Herring				>;
1459*724ba675SRob Herring			};
1460*724ba675SRob Herring
1461*724ba675SRob Herring			timing-667000000 {
1462*724ba675SRob Herring				clock-frequency = <667000000>;
1463*724ba675SRob Herring
1464*724ba675SRob Herring				nvidia,emc-auto-cal-interval = <0x001fffff>;
1465*724ba675SRob Herring				nvidia,emc-mode-1 = <0x80100002>;
1466*724ba675SRob Herring				nvidia,emc-mode-2 = <0x80200018>;
1467*724ba675SRob Herring				nvidia,emc-mode-reset = <0x80000b71>;
1468*724ba675SRob Herring				nvidia,emc-zcal-cnt-long = <0x00000040>;
1469*724ba675SRob Herring				nvidia,emc-cfg-periodic-qrst;
1470*724ba675SRob Herring
1471*724ba675SRob Herring				nvidia,emc-configuration = <
1472*724ba675SRob Herring					0x00000020 /* EMC_RC */
1473*724ba675SRob Herring					0x0000006a /* EMC_RFC */
1474*724ba675SRob Herring					0x00000017 /* EMC_RAS */
1475*724ba675SRob Herring					0x00000007 /* EMC_RP */
1476*724ba675SRob Herring					0x00000005 /* EMC_R2W */
1477*724ba675SRob Herring					0x0000000c /* EMC_W2R */
1478*724ba675SRob Herring					0x00000003 /* EMC_R2P */
1479*724ba675SRob Herring					0x00000011 /* EMC_W2P */
1480*724ba675SRob Herring					0x00000007 /* EMC_RD_RCD */
1481*724ba675SRob Herring					0x00000007 /* EMC_WR_RCD */
1482*724ba675SRob Herring					0x00000002 /* EMC_RRD */
1483*724ba675SRob Herring					0x00000001 /* EMC_REXT */
1484*724ba675SRob Herring					0x00000000 /* EMC_WEXT */
1485*724ba675SRob Herring					0x00000007 /* EMC_WDV */
1486*724ba675SRob Herring					0x0000000a /* EMC_QUSE */
1487*724ba675SRob Herring					0x00000009 /* EMC_QRST */
1488*724ba675SRob Herring					0x0000000b /* EMC_QSAFE */
1489*724ba675SRob Herring					0x00000011 /* EMC_RDV */
1490*724ba675SRob Herring					0x00001412 /* EMC_REFRESH */
1491*724ba675SRob Herring					0x00000000 /* EMC_BURST_REFRESH_NUM */
1492*724ba675SRob Herring					0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */
1493*724ba675SRob Herring					0x00000002 /* EMC_PDEX2WR */
1494*724ba675SRob Herring					0x0000000e /* EMC_PDEX2RD */
1495*724ba675SRob Herring					0x00000001 /* EMC_PCHG2PDEN */
1496*724ba675SRob Herring					0x00000000 /* EMC_ACT2PDEN */
1497*724ba675SRob Herring					0x0000000c /* EMC_AR2PDEN */
1498*724ba675SRob Herring					0x00000016 /* EMC_RW2PDEN */
1499*724ba675SRob Herring					0x00000072 /* EMC_TXSR */
1500*724ba675SRob Herring					0x00000200 /* EMC_TXSRDLL */
1501*724ba675SRob Herring					0x00000005 /* EMC_TCKE */
1502*724ba675SRob Herring					0x00000015 /* EMC_TFAW */
1503*724ba675SRob Herring					0x00000000 /* EMC_TRPAB */
1504*724ba675SRob Herring					0x00000006 /* EMC_TCLKSTABLE */
1505*724ba675SRob Herring					0x00000007 /* EMC_TCLKSTOP */
1506*724ba675SRob Herring					0x00001453 /* EMC_TREFBW */
1507*724ba675SRob Herring					0x0000000b /* EMC_QUSE_EXTRA */
1508*724ba675SRob Herring					0x00000006 /* EMC_FBIO_CFG6 */
1509*724ba675SRob Herring					0x00000000 /* EMC_ODT_WRITE */
1510*724ba675SRob Herring					0x00000000 /* EMC_ODT_READ */
1511*724ba675SRob Herring					0x00005088 /* EMC_FBIO_CFG5 */
1512*724ba675SRob Herring					0xf00b0191 /* EMC_CFG_DIG_DLL */
1513*724ba675SRob Herring					0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1514*724ba675SRob Herring					0x0000000a /* EMC_DLL_XFORM_DQS0 */
1515*724ba675SRob Herring					0x0000000a /* EMC_DLL_XFORM_DQS1 */
1516*724ba675SRob Herring					0x0000000a /* EMC_DLL_XFORM_DQS2 */
1517*724ba675SRob Herring					0x0000000a /* EMC_DLL_XFORM_DQS3 */
1518*724ba675SRob Herring					0x0000000a /* EMC_DLL_XFORM_DQS4 */
1519*724ba675SRob Herring					0x0000000a /* EMC_DLL_XFORM_DQS5 */
1520*724ba675SRob Herring					0x0000000a /* EMC_DLL_XFORM_DQS6 */
1521*724ba675SRob Herring					0x0000000a /* EMC_DLL_XFORM_DQS7 */
1522*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1523*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1524*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1525*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1526*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1527*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1528*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1529*724ba675SRob Herring					0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1530*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1531*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1532*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1533*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1534*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1535*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1536*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1537*724ba675SRob Herring					0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1538*724ba675SRob Herring					0x0000000c /* EMC_DLL_XFORM_DQ0 */
1539*724ba675SRob Herring					0x0000000c /* EMC_DLL_XFORM_DQ1 */
1540*724ba675SRob Herring					0x0000000c /* EMC_DLL_XFORM_DQ2 */
1541*724ba675SRob Herring					0x0000000c /* EMC_DLL_XFORM_DQ3 */
1542*724ba675SRob Herring					0x000002a0 /* EMC_XM2CMDPADCTRL */
1543*724ba675SRob Herring					0x0400013d /* EMC_XM2DQSPADCTRL2 */
1544*724ba675SRob Herring					0x22220000 /* EMC_XM2DQPADCTRL2 */
1545*724ba675SRob Herring					0x77fff884 /* EMC_XM2CLKPADCTRL */
1546*724ba675SRob Herring					0x01f1f501 /* EMC_XM2COMPPADCTRL */
1547*724ba675SRob Herring					0x07077404 /* EMC_XM2VTTGENPADCTRL */
1548*724ba675SRob Herring					0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
1549*724ba675SRob Herring					0x080001e8 /* EMC_XM2QUSEPADCTRL */
1550*724ba675SRob Herring					0x0a000021 /* EMC_XM2DQSPADCTRL3 */
1551*724ba675SRob Herring					0x00000802 /* EMC_CTT_TERM_CTRL */
1552*724ba675SRob Herring					0x00020000 /* EMC_ZCAL_INTERVAL */
1553*724ba675SRob Herring					0x00000100 /* EMC_ZCAL_WAIT_CNT */
1554*724ba675SRob Herring					0x0155000c /* EMC_MRS_WAIT_CNT */
1555*724ba675SRob Herring					0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1556*724ba675SRob Herring					0x00000000 /* EMC_CTT */
1557*724ba675SRob Herring					0x00000000 /* EMC_CTT_DURATION */
1558*724ba675SRob Herring					0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */
1559*724ba675SRob Herring					0xe8000000 /* EMC_FBIO_SPARE */
1560*724ba675SRob Herring					0xff00ff49 /* EMC_CFG_RSV */
1561*724ba675SRob Herring				>;
1562*724ba675SRob Herring			};
1563*724ba675SRob Herring		};
1564*724ba675SRob Herring	};
1565*724ba675SRob Herring
1566*724ba675SRob Herring	opp-table-actmon {
1567*724ba675SRob Herring		/delete-node/ opp-750000000;
1568*724ba675SRob Herring		/delete-node/ opp-800000000;
1569*724ba675SRob Herring		/delete-node/ opp-900000000;
1570*724ba675SRob Herring	};
1571*724ba675SRob Herring
1572*724ba675SRob Herring	opp-table-emc {
1573*724ba675SRob Herring		/delete-node/ opp-750000000-1300;
1574*724ba675SRob Herring		/delete-node/ opp-800000000-1300;
1575*724ba675SRob Herring		/delete-node/ opp-900000000-1350;
1576*724ba675SRob Herring	};
1577*724ba675SRob Herring};
1578