1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring#include "tegra20.dtsi" 3*724ba675SRob Herring 4*724ba675SRob Herring/ { 5*724ba675SRob Herring model = "Avionic Design Tamonten SOM"; 6*724ba675SRob Herring compatible = "ad,tamonten", "nvidia,tegra20"; 7*724ba675SRob Herring 8*724ba675SRob Herring aliases { 9*724ba675SRob Herring rtc0 = "/i2c@7000d000/tps6586x@34"; 10*724ba675SRob Herring rtc1 = "/rtc@7000e000"; 11*724ba675SRob Herring serial0 = &uartd; 12*724ba675SRob Herring }; 13*724ba675SRob Herring 14*724ba675SRob Herring chosen { 15*724ba675SRob Herring stdout-path = "serial0:115200n8"; 16*724ba675SRob Herring }; 17*724ba675SRob Herring 18*724ba675SRob Herring memory@0 { 19*724ba675SRob Herring reg = <0x00000000 0x20000000>; 20*724ba675SRob Herring }; 21*724ba675SRob Herring 22*724ba675SRob Herring host1x@50000000 { 23*724ba675SRob Herring hdmi@54280000 { 24*724ba675SRob Herring vdd-supply = <&hdmi_vdd_reg>; 25*724ba675SRob Herring pll-supply = <&hdmi_pll_reg>; 26*724ba675SRob Herring 27*724ba675SRob Herring nvidia,ddc-i2c-bus = <&hdmi_ddc>; 28*724ba675SRob Herring nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 29*724ba675SRob Herring GPIO_ACTIVE_HIGH>; 30*724ba675SRob Herring }; 31*724ba675SRob Herring }; 32*724ba675SRob Herring 33*724ba675SRob Herring pinmux@70000014 { 34*724ba675SRob Herring pinctrl-names = "default"; 35*724ba675SRob Herring pinctrl-0 = <&state_default>; 36*724ba675SRob Herring 37*724ba675SRob Herring state_default: pinmux { 38*724ba675SRob Herring ata { 39*724ba675SRob Herring nvidia,pins = "ata"; 40*724ba675SRob Herring nvidia,function = "ide"; 41*724ba675SRob Herring }; 42*724ba675SRob Herring atb { 43*724ba675SRob Herring nvidia,pins = "atb", "gma", "gme"; 44*724ba675SRob Herring nvidia,function = "sdio4"; 45*724ba675SRob Herring }; 46*724ba675SRob Herring atc { 47*724ba675SRob Herring nvidia,pins = "atc"; 48*724ba675SRob Herring nvidia,function = "nand"; 49*724ba675SRob Herring }; 50*724ba675SRob Herring atd { 51*724ba675SRob Herring nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", 52*724ba675SRob Herring "spia", "spib", "spic"; 53*724ba675SRob Herring nvidia,function = "gmi"; 54*724ba675SRob Herring }; 55*724ba675SRob Herring cdev1 { 56*724ba675SRob Herring nvidia,pins = "cdev1"; 57*724ba675SRob Herring nvidia,function = "plla_out"; 58*724ba675SRob Herring }; 59*724ba675SRob Herring cdev2 { 60*724ba675SRob Herring nvidia,pins = "cdev2"; 61*724ba675SRob Herring nvidia,function = "pllp_out4"; 62*724ba675SRob Herring }; 63*724ba675SRob Herring crtp { 64*724ba675SRob Herring nvidia,pins = "crtp"; 65*724ba675SRob Herring nvidia,function = "crt"; 66*724ba675SRob Herring }; 67*724ba675SRob Herring csus { 68*724ba675SRob Herring nvidia,pins = "csus"; 69*724ba675SRob Herring nvidia,function = "vi_sensor_clk"; 70*724ba675SRob Herring }; 71*724ba675SRob Herring dap1 { 72*724ba675SRob Herring nvidia,pins = "dap1"; 73*724ba675SRob Herring nvidia,function = "dap1"; 74*724ba675SRob Herring }; 75*724ba675SRob Herring dap2 { 76*724ba675SRob Herring nvidia,pins = "dap2"; 77*724ba675SRob Herring nvidia,function = "dap2"; 78*724ba675SRob Herring }; 79*724ba675SRob Herring dap3 { 80*724ba675SRob Herring nvidia,pins = "dap3"; 81*724ba675SRob Herring nvidia,function = "dap3"; 82*724ba675SRob Herring }; 83*724ba675SRob Herring dap4 { 84*724ba675SRob Herring nvidia,pins = "dap4"; 85*724ba675SRob Herring nvidia,function = "dap4"; 86*724ba675SRob Herring }; 87*724ba675SRob Herring dta { 88*724ba675SRob Herring nvidia,pins = "dta", "dtd"; 89*724ba675SRob Herring nvidia,function = "sdio2"; 90*724ba675SRob Herring }; 91*724ba675SRob Herring dtb { 92*724ba675SRob Herring nvidia,pins = "dtb", "dtc", "dte"; 93*724ba675SRob Herring nvidia,function = "rsvd1"; 94*724ba675SRob Herring }; 95*724ba675SRob Herring dtf { 96*724ba675SRob Herring nvidia,pins = "dtf"; 97*724ba675SRob Herring nvidia,function = "i2c3"; 98*724ba675SRob Herring }; 99*724ba675SRob Herring gmc { 100*724ba675SRob Herring nvidia,pins = "gmc"; 101*724ba675SRob Herring nvidia,function = "uartd"; 102*724ba675SRob Herring }; 103*724ba675SRob Herring gpu7 { 104*724ba675SRob Herring nvidia,pins = "gpu7"; 105*724ba675SRob Herring nvidia,function = "rtck"; 106*724ba675SRob Herring }; 107*724ba675SRob Herring gpv { 108*724ba675SRob Herring nvidia,pins = "gpv", "slxa", "slxk"; 109*724ba675SRob Herring nvidia,function = "pcie"; 110*724ba675SRob Herring }; 111*724ba675SRob Herring hdint { 112*724ba675SRob Herring nvidia,pins = "hdint"; 113*724ba675SRob Herring nvidia,function = "hdmi"; 114*724ba675SRob Herring }; 115*724ba675SRob Herring i2cp { 116*724ba675SRob Herring nvidia,pins = "i2cp"; 117*724ba675SRob Herring nvidia,function = "i2cp"; 118*724ba675SRob Herring }; 119*724ba675SRob Herring irrx { 120*724ba675SRob Herring nvidia,pins = "irrx", "irtx"; 121*724ba675SRob Herring nvidia,function = "uarta"; 122*724ba675SRob Herring }; 123*724ba675SRob Herring kbca { 124*724ba675SRob Herring nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", 125*724ba675SRob Herring "kbce", "kbcf"; 126*724ba675SRob Herring nvidia,function = "kbc"; 127*724ba675SRob Herring }; 128*724ba675SRob Herring lcsn { 129*724ba675SRob Herring nvidia,pins = "lcsn", "ld0", "ld1", "ld2", 130*724ba675SRob Herring "ld3", "ld4", "ld5", "ld6", "ld7", 131*724ba675SRob Herring "ld8", "ld9", "ld10", "ld11", "ld12", 132*724ba675SRob Herring "ld13", "ld14", "ld15", "ld16", "ld17", 133*724ba675SRob Herring "ldc", "ldi", "lhp0", "lhp1", "lhp2", 134*724ba675SRob Herring "lhs", "lm0", "lm1", "lpp", "lpw0", 135*724ba675SRob Herring "lpw1", "lpw2", "lsc0", "lsc1", "lsck", 136*724ba675SRob Herring "lsda", "lsdi", "lspi", "lvp0", "lvp1", 137*724ba675SRob Herring "lvs"; 138*724ba675SRob Herring nvidia,function = "displaya"; 139*724ba675SRob Herring }; 140*724ba675SRob Herring owc { 141*724ba675SRob Herring nvidia,pins = "owc", "spdi", "spdo", "uac"; 142*724ba675SRob Herring nvidia,function = "rsvd2"; 143*724ba675SRob Herring }; 144*724ba675SRob Herring pmc { 145*724ba675SRob Herring nvidia,pins = "pmc"; 146*724ba675SRob Herring nvidia,function = "pwr_on"; 147*724ba675SRob Herring }; 148*724ba675SRob Herring rm { 149*724ba675SRob Herring nvidia,pins = "rm"; 150*724ba675SRob Herring nvidia,function = "i2c1"; 151*724ba675SRob Herring }; 152*724ba675SRob Herring sdb { 153*724ba675SRob Herring nvidia,pins = "sdb", "sdc", "sdd"; 154*724ba675SRob Herring nvidia,function = "pwm"; 155*724ba675SRob Herring }; 156*724ba675SRob Herring sdio1 { 157*724ba675SRob Herring nvidia,pins = "sdio1"; 158*724ba675SRob Herring nvidia,function = "sdio1"; 159*724ba675SRob Herring }; 160*724ba675SRob Herring slxc { 161*724ba675SRob Herring nvidia,pins = "slxc", "slxd"; 162*724ba675SRob Herring nvidia,function = "spdif"; 163*724ba675SRob Herring }; 164*724ba675SRob Herring spid { 165*724ba675SRob Herring nvidia,pins = "spid", "spie", "spif"; 166*724ba675SRob Herring nvidia,function = "spi1"; 167*724ba675SRob Herring }; 168*724ba675SRob Herring spig { 169*724ba675SRob Herring nvidia,pins = "spig", "spih"; 170*724ba675SRob Herring nvidia,function = "spi2_alt"; 171*724ba675SRob Herring }; 172*724ba675SRob Herring uaa { 173*724ba675SRob Herring nvidia,pins = "uaa", "uab", "uda"; 174*724ba675SRob Herring nvidia,function = "ulpi"; 175*724ba675SRob Herring }; 176*724ba675SRob Herring uad { 177*724ba675SRob Herring nvidia,pins = "uad"; 178*724ba675SRob Herring nvidia,function = "irda"; 179*724ba675SRob Herring }; 180*724ba675SRob Herring uca { 181*724ba675SRob Herring nvidia,pins = "uca", "ucb"; 182*724ba675SRob Herring nvidia,function = "uartc"; 183*724ba675SRob Herring }; 184*724ba675SRob Herring conf_ata { 185*724ba675SRob Herring nvidia,pins = "ata", "atb", "atc", "atd", "ate", 186*724ba675SRob Herring "cdev1", "cdev2", "dap1", "dtb", "dtf", 187*724ba675SRob Herring "gma", "gmb", "gmc", "gmd", "gme", "gpu7", 188*724ba675SRob Herring "gpv", "i2cp", "irrx", "irtx", "pta", 189*724ba675SRob Herring "rm", "slxa", "slxk", "spia", "spib", 190*724ba675SRob Herring "uac"; 191*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 192*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 193*724ba675SRob Herring }; 194*724ba675SRob Herring conf_ck32 { 195*724ba675SRob Herring nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 196*724ba675SRob Herring "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 197*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 198*724ba675SRob Herring }; 199*724ba675SRob Herring conf_csus { 200*724ba675SRob Herring nvidia,pins = "csus", "spid", "spif"; 201*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 202*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 203*724ba675SRob Herring }; 204*724ba675SRob Herring conf_crtp { 205*724ba675SRob Herring nvidia,pins = "crtp", "dap2", "dap3", "dap4", 206*724ba675SRob Herring "dtc", "dte", "gpu", "sdio1", 207*724ba675SRob Herring "slxc", "slxd", "spdi", "spdo", "spig", 208*724ba675SRob Herring "uda"; 209*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 210*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 211*724ba675SRob Herring }; 212*724ba675SRob Herring conf_ddc { 213*724ba675SRob Herring nvidia,pins = "ddc", "dta", "dtd", "kbca", 214*724ba675SRob Herring "kbcb", "kbcc", "kbcd", "kbce", "kbcf", 215*724ba675SRob Herring "sdc", "uad", "uca"; 216*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 217*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 218*724ba675SRob Herring }; 219*724ba675SRob Herring conf_hdint { 220*724ba675SRob Herring nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 221*724ba675SRob Herring "lpw1", "lsc1", "lsck", "lsda", "lsdi", 222*724ba675SRob Herring "lvp0", "owc", "sdb"; 223*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 224*724ba675SRob Herring }; 225*724ba675SRob Herring conf_sdd { 226*724ba675SRob Herring nvidia,pins = "sdd", "spic", "spie", "spih", 227*724ba675SRob Herring "uaa", "uab", "ucb"; 228*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 229*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 230*724ba675SRob Herring }; 231*724ba675SRob Herring conf_lc { 232*724ba675SRob Herring nvidia,pins = "lc", "ls"; 233*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 234*724ba675SRob Herring }; 235*724ba675SRob Herring conf_ld0 { 236*724ba675SRob Herring nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 237*724ba675SRob Herring "ld5", "ld6", "ld7", "ld8", "ld9", 238*724ba675SRob Herring "ld10", "ld11", "ld12", "ld13", "ld14", 239*724ba675SRob Herring "ld15", "ld16", "ld17", "ldi", "lhp0", 240*724ba675SRob Herring "lhp1", "lhp2", "lhs", "lm0", "lpp", 241*724ba675SRob Herring "lpw0", "lpw2", "lsc0", "lspi", "lvp1", 242*724ba675SRob Herring "lvs", "pmc"; 243*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 244*724ba675SRob Herring }; 245*724ba675SRob Herring conf_ld17_0 { 246*724ba675SRob Herring nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 247*724ba675SRob Herring "ld23_22"; 248*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 249*724ba675SRob Herring }; 250*724ba675SRob Herring }; 251*724ba675SRob Herring 252*724ba675SRob Herring state_i2cmux_ddc: pinmux-i2cmux-ddc { 253*724ba675SRob Herring ddc { 254*724ba675SRob Herring nvidia,pins = "ddc"; 255*724ba675SRob Herring nvidia,function = "i2c2"; 256*724ba675SRob Herring }; 257*724ba675SRob Herring pta { 258*724ba675SRob Herring nvidia,pins = "pta"; 259*724ba675SRob Herring nvidia,function = "rsvd4"; 260*724ba675SRob Herring }; 261*724ba675SRob Herring }; 262*724ba675SRob Herring 263*724ba675SRob Herring state_i2cmux_idle: pinmux-i2cmux-idle { 264*724ba675SRob Herring ddc { 265*724ba675SRob Herring nvidia,pins = "ddc"; 266*724ba675SRob Herring nvidia,function = "rsvd4"; 267*724ba675SRob Herring }; 268*724ba675SRob Herring pta { 269*724ba675SRob Herring nvidia,pins = "pta"; 270*724ba675SRob Herring nvidia,function = "rsvd4"; 271*724ba675SRob Herring }; 272*724ba675SRob Herring }; 273*724ba675SRob Herring 274*724ba675SRob Herring state_i2cmux_pta: pinmux-i2cmux-pta { 275*724ba675SRob Herring ddc { 276*724ba675SRob Herring nvidia,pins = "ddc"; 277*724ba675SRob Herring nvidia,function = "rsvd4"; 278*724ba675SRob Herring }; 279*724ba675SRob Herring pta { 280*724ba675SRob Herring nvidia,pins = "pta"; 281*724ba675SRob Herring nvidia,function = "i2c2"; 282*724ba675SRob Herring }; 283*724ba675SRob Herring }; 284*724ba675SRob Herring }; 285*724ba675SRob Herring 286*724ba675SRob Herring i2s@70002800 { 287*724ba675SRob Herring status = "okay"; 288*724ba675SRob Herring }; 289*724ba675SRob Herring 290*724ba675SRob Herring serial@70006300 { 291*724ba675SRob Herring status = "okay"; 292*724ba675SRob Herring }; 293*724ba675SRob Herring 294*724ba675SRob Herring i2c@7000c000 { 295*724ba675SRob Herring clock-frequency = <400000>; 296*724ba675SRob Herring status = "okay"; 297*724ba675SRob Herring }; 298*724ba675SRob Herring 299*724ba675SRob Herring i2c@7000c400 { 300*724ba675SRob Herring clock-frequency = <100000>; 301*724ba675SRob Herring status = "okay"; 302*724ba675SRob Herring }; 303*724ba675SRob Herring 304*724ba675SRob Herring i2c@7000d000 { 305*724ba675SRob Herring clock-frequency = <400000>; 306*724ba675SRob Herring status = "okay"; 307*724ba675SRob Herring 308*724ba675SRob Herring pmic: tps6586x@34 { 309*724ba675SRob Herring compatible = "ti,tps6586x"; 310*724ba675SRob Herring reg = <0x34>; 311*724ba675SRob Herring interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 312*724ba675SRob Herring 313*724ba675SRob Herring ti,system-power-controller; 314*724ba675SRob Herring 315*724ba675SRob Herring #gpio-cells = <2>; 316*724ba675SRob Herring gpio-controller; 317*724ba675SRob Herring 318*724ba675SRob Herring /* vdd_5v0_reg must be provided by the base board */ 319*724ba675SRob Herring sys-supply = <&vdd_5v0_reg>; 320*724ba675SRob Herring vin-sm0-supply = <&sys_reg>; 321*724ba675SRob Herring vin-sm1-supply = <&sys_reg>; 322*724ba675SRob Herring vin-sm2-supply = <&sys_reg>; 323*724ba675SRob Herring vinldo01-supply = <&sm2_reg>; 324*724ba675SRob Herring vinldo23-supply = <&sm2_reg>; 325*724ba675SRob Herring vinldo4-supply = <&sm2_reg>; 326*724ba675SRob Herring vinldo678-supply = <&sm2_reg>; 327*724ba675SRob Herring vinldo9-supply = <&sm2_reg>; 328*724ba675SRob Herring 329*724ba675SRob Herring regulators { 330*724ba675SRob Herring sys_reg: sys { 331*724ba675SRob Herring regulator-name = "vdd_sys"; 332*724ba675SRob Herring regulator-always-on; 333*724ba675SRob Herring }; 334*724ba675SRob Herring 335*724ba675SRob Herring vdd_core: sm0 { 336*724ba675SRob Herring regulator-name = "vdd_sys_sm0,vdd_core"; 337*724ba675SRob Herring regulator-min-microvolt = <1200000>; 338*724ba675SRob Herring regulator-max-microvolt = <1200000>; 339*724ba675SRob Herring regulator-always-on; 340*724ba675SRob Herring }; 341*724ba675SRob Herring 342*724ba675SRob Herring sm1 { 343*724ba675SRob Herring regulator-name = "vdd_sys_sm1,vdd_cpu"; 344*724ba675SRob Herring regulator-min-microvolt = <1000000>; 345*724ba675SRob Herring regulator-max-microvolt = <1000000>; 346*724ba675SRob Herring regulator-always-on; 347*724ba675SRob Herring }; 348*724ba675SRob Herring 349*724ba675SRob Herring sm2_reg: sm2 { 350*724ba675SRob Herring regulator-name = "vdd_sys_sm2,vin_ldo*"; 351*724ba675SRob Herring regulator-min-microvolt = <3700000>; 352*724ba675SRob Herring regulator-max-microvolt = <3700000>; 353*724ba675SRob Herring regulator-always-on; 354*724ba675SRob Herring }; 355*724ba675SRob Herring 356*724ba675SRob Herring pci_clk_reg: ldo0 { 357*724ba675SRob Herring regulator-name = "vdd_ldo0,vddio_pex_clk"; 358*724ba675SRob Herring regulator-min-microvolt = <3300000>; 359*724ba675SRob Herring regulator-max-microvolt = <3300000>; 360*724ba675SRob Herring }; 361*724ba675SRob Herring 362*724ba675SRob Herring ldo1 { 363*724ba675SRob Herring regulator-name = "vdd_ldo1,avdd_pll*"; 364*724ba675SRob Herring regulator-min-microvolt = <1100000>; 365*724ba675SRob Herring regulator-max-microvolt = <1100000>; 366*724ba675SRob Herring regulator-always-on; 367*724ba675SRob Herring }; 368*724ba675SRob Herring 369*724ba675SRob Herring ldo2 { 370*724ba675SRob Herring regulator-name = "vdd_ldo2,vdd_rtc"; 371*724ba675SRob Herring regulator-min-microvolt = <1200000>; 372*724ba675SRob Herring regulator-max-microvolt = <1200000>; 373*724ba675SRob Herring }; 374*724ba675SRob Herring 375*724ba675SRob Herring ldo3 { 376*724ba675SRob Herring regulator-name = "vdd_ldo3,avdd_usb*"; 377*724ba675SRob Herring regulator-min-microvolt = <3300000>; 378*724ba675SRob Herring regulator-max-microvolt = <3300000>; 379*724ba675SRob Herring regulator-always-on; 380*724ba675SRob Herring }; 381*724ba675SRob Herring 382*724ba675SRob Herring ldo4 { 383*724ba675SRob Herring regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; 384*724ba675SRob Herring regulator-min-microvolt = <1800000>; 385*724ba675SRob Herring regulator-max-microvolt = <1800000>; 386*724ba675SRob Herring regulator-always-on; 387*724ba675SRob Herring }; 388*724ba675SRob Herring 389*724ba675SRob Herring ldo5 { 390*724ba675SRob Herring regulator-name = "vdd_ldo5,vcore_mmc"; 391*724ba675SRob Herring regulator-min-microvolt = <2850000>; 392*724ba675SRob Herring regulator-max-microvolt = <2850000>; 393*724ba675SRob Herring }; 394*724ba675SRob Herring 395*724ba675SRob Herring ldo6 { 396*724ba675SRob Herring regulator-name = "vdd_ldo6,avdd_vdac"; 397*724ba675SRob Herring /* 398*724ba675SRob Herring * According to the Tegra 2 Automotive 399*724ba675SRob Herring * DataSheet, a typical value for this 400*724ba675SRob Herring * would be 2.8V, but the PMIC only 401*724ba675SRob Herring * supports 2.85V. 402*724ba675SRob Herring */ 403*724ba675SRob Herring regulator-min-microvolt = <2850000>; 404*724ba675SRob Herring regulator-max-microvolt = <2850000>; 405*724ba675SRob Herring }; 406*724ba675SRob Herring 407*724ba675SRob Herring hdmi_vdd_reg: ldo7 { 408*724ba675SRob Herring regulator-name = "vdd_ldo7,avdd_hdmi"; 409*724ba675SRob Herring regulator-min-microvolt = <3300000>; 410*724ba675SRob Herring regulator-max-microvolt = <3300000>; 411*724ba675SRob Herring }; 412*724ba675SRob Herring 413*724ba675SRob Herring hdmi_pll_reg: ldo8 { 414*724ba675SRob Herring regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 415*724ba675SRob Herring regulator-min-microvolt = <1800000>; 416*724ba675SRob Herring regulator-max-microvolt = <1800000>; 417*724ba675SRob Herring }; 418*724ba675SRob Herring 419*724ba675SRob Herring ldo9 { 420*724ba675SRob Herring regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam"; 421*724ba675SRob Herring /* 422*724ba675SRob Herring * According to the Tegra 2 Automotive 423*724ba675SRob Herring * DataSheet, a typical value for this 424*724ba675SRob Herring * would be 2.8V, but the PMIC only 425*724ba675SRob Herring * supports 2.85V. 426*724ba675SRob Herring */ 427*724ba675SRob Herring regulator-min-microvolt = <2850000>; 428*724ba675SRob Herring regulator-max-microvolt = <2850000>; 429*724ba675SRob Herring regulator-always-on; 430*724ba675SRob Herring }; 431*724ba675SRob Herring 432*724ba675SRob Herring ldo_rtc { 433*724ba675SRob Herring regulator-name = "vdd_rtc_out"; 434*724ba675SRob Herring regulator-min-microvolt = <3300000>; 435*724ba675SRob Herring regulator-max-microvolt = <3300000>; 436*724ba675SRob Herring regulator-always-on; 437*724ba675SRob Herring }; 438*724ba675SRob Herring }; 439*724ba675SRob Herring }; 440*724ba675SRob Herring 441*724ba675SRob Herring temperature-sensor@4c { 442*724ba675SRob Herring compatible = "onnn,nct1008"; 443*724ba675SRob Herring reg = <0x4c>; 444*724ba675SRob Herring }; 445*724ba675SRob Herring }; 446*724ba675SRob Herring 447*724ba675SRob Herring pmc@7000e400 { 448*724ba675SRob Herring nvidia,invert-interrupt; 449*724ba675SRob Herring nvidia,suspend-mode = <1>; 450*724ba675SRob Herring nvidia,cpu-pwr-good-time = <5000>; 451*724ba675SRob Herring nvidia,cpu-pwr-off-time = <5000>; 452*724ba675SRob Herring nvidia,core-pwr-good-time = <3845 3845>; 453*724ba675SRob Herring nvidia,core-pwr-off-time = <3875>; 454*724ba675SRob Herring nvidia,sys-clock-req-active-high; 455*724ba675SRob Herring core-supply = <&vdd_core>; 456*724ba675SRob Herring }; 457*724ba675SRob Herring 458*724ba675SRob Herring pcie@80003000 { 459*724ba675SRob Herring avdd-pex-supply = <&pci_vdd_reg>; 460*724ba675SRob Herring vdd-pex-supply = <&pci_vdd_reg>; 461*724ba675SRob Herring avdd-pex-pll-supply = <&pci_vdd_reg>; 462*724ba675SRob Herring avdd-plle-supply = <&pci_vdd_reg>; 463*724ba675SRob Herring vddio-pex-clk-supply = <&pci_clk_reg>; 464*724ba675SRob Herring }; 465*724ba675SRob Herring 466*724ba675SRob Herring usb@c5008000 { 467*724ba675SRob Herring status = "okay"; 468*724ba675SRob Herring }; 469*724ba675SRob Herring 470*724ba675SRob Herring usb-phy@c5008000 { 471*724ba675SRob Herring status = "okay"; 472*724ba675SRob Herring }; 473*724ba675SRob Herring 474*724ba675SRob Herring mmc@c8000600 { 475*724ba675SRob Herring cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; 476*724ba675SRob Herring wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; 477*724ba675SRob Herring bus-width = <4>; 478*724ba675SRob Herring status = "okay"; 479*724ba675SRob Herring }; 480*724ba675SRob Herring 481*724ba675SRob Herring clk32k_in: clock-32k { 482*724ba675SRob Herring compatible = "fixed-clock"; 483*724ba675SRob Herring clock-frequency = <32768>; 484*724ba675SRob Herring #clock-cells = <0>; 485*724ba675SRob Herring }; 486*724ba675SRob Herring 487*724ba675SRob Herring i2cmux { 488*724ba675SRob Herring compatible = "i2c-mux-pinctrl"; 489*724ba675SRob Herring #address-cells = <1>; 490*724ba675SRob Herring #size-cells = <0>; 491*724ba675SRob Herring 492*724ba675SRob Herring i2c-parent = <&{/i2c@7000c400}>; 493*724ba675SRob Herring 494*724ba675SRob Herring pinctrl-names = "ddc", "pta", "idle"; 495*724ba675SRob Herring pinctrl-0 = <&state_i2cmux_ddc>; 496*724ba675SRob Herring pinctrl-1 = <&state_i2cmux_pta>; 497*724ba675SRob Herring pinctrl-2 = <&state_i2cmux_idle>; 498*724ba675SRob Herring 499*724ba675SRob Herring hdmi_ddc: i2c@0 { 500*724ba675SRob Herring reg = <0>; 501*724ba675SRob Herring #address-cells = <1>; 502*724ba675SRob Herring #size-cells = <0>; 503*724ba675SRob Herring }; 504*724ba675SRob Herring 505*724ba675SRob Herring i2c@1 { 506*724ba675SRob Herring reg = <1>; 507*724ba675SRob Herring #address-cells = <1>; 508*724ba675SRob Herring #size-cells = <0>; 509*724ba675SRob Herring }; 510*724ba675SRob Herring }; 511*724ba675SRob Herring 512*724ba675SRob Herring pci_vdd_reg: regulator-1v05 { 513*724ba675SRob Herring compatible = "regulator-fixed"; 514*724ba675SRob Herring regulator-name = "vdd_1v05"; 515*724ba675SRob Herring regulator-min-microvolt = <1050000>; 516*724ba675SRob Herring regulator-max-microvolt = <1050000>; 517*724ba675SRob Herring gpio = <&pmic 2 0>; 518*724ba675SRob Herring enable-active-high; 519*724ba675SRob Herring }; 520*724ba675SRob Herring}; 521