1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 OR MIT 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright 2016-2018 Toradex AG 4*724ba675SRob Herring */ 5*724ba675SRob Herring 6*724ba675SRob Herring#include "tegra124.dtsi" 7*724ba675SRob Herring#include "tegra124-apalis-emc.dtsi" 8*724ba675SRob Herring 9*724ba675SRob Herring/* 10*724ba675SRob Herring * Toradex Apalis TK1 Module Device Tree 11*724ba675SRob Herring * Compatible for Revisions 2GB: V1.2A 12*724ba675SRob Herring */ 13*724ba675SRob Herring/ { 14*724ba675SRob Herring memory@80000000 { 15*724ba675SRob Herring reg = <0x0 0x80000000 0x0 0x80000000>; 16*724ba675SRob Herring }; 17*724ba675SRob Herring 18*724ba675SRob Herring pcie@1003000 { 19*724ba675SRob Herring status = "okay"; 20*724ba675SRob Herring 21*724ba675SRob Herring avddio-pex-supply = <®_1v05_vdd>; 22*724ba675SRob Herring avdd-pex-pll-supply = <®_1v05_vdd>; 23*724ba675SRob Herring avdd-pll-erefe-supply = <®_1v05_avdd>; 24*724ba675SRob Herring dvddio-pex-supply = <®_1v05_vdd>; 25*724ba675SRob Herring hvdd-pex-pll-e-supply = <®_module_3v3>; 26*724ba675SRob Herring hvdd-pex-supply = <®_module_3v3>; 27*724ba675SRob Herring vddio-pex-ctl-supply = <®_module_3v3>; 28*724ba675SRob Herring 29*724ba675SRob Herring /* Apalis PCIe (additional lane Apalis type specific) */ 30*724ba675SRob Herring pci@1,0 { 31*724ba675SRob Herring /* PCIE1_RX/TX and TS_DIFF1/2 */ 32*724ba675SRob Herring phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>, 33*724ba675SRob Herring <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; 34*724ba675SRob Herring phy-names = "pcie-0", "pcie-1"; 35*724ba675SRob Herring }; 36*724ba675SRob Herring 37*724ba675SRob Herring /* I210 Gigabit Ethernet Controller (On-module) */ 38*724ba675SRob Herring pci@2,0 { 39*724ba675SRob Herring phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; 40*724ba675SRob Herring phy-names = "pcie-0"; 41*724ba675SRob Herring status = "okay"; 42*724ba675SRob Herring 43*724ba675SRob Herring ethernet@0,0 { 44*724ba675SRob Herring reg = <0 0 0 0 0>; 45*724ba675SRob Herring local-mac-address = [00 00 00 00 00 00]; 46*724ba675SRob Herring }; 47*724ba675SRob Herring }; 48*724ba675SRob Herring }; 49*724ba675SRob Herring 50*724ba675SRob Herring host1x@50000000 { 51*724ba675SRob Herring hdmi@54280000 { 52*724ba675SRob Herring nvidia,ddc-i2c-bus = <&hdmi_ddc>; 53*724ba675SRob Herring nvidia,hpd-gpio = 54*724ba675SRob Herring <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 55*724ba675SRob Herring pll-supply = <®_1v05_avdd_hdmi_pll>; 56*724ba675SRob Herring vdd-supply = <®_3v3_avdd_hdmi>; 57*724ba675SRob Herring }; 58*724ba675SRob Herring }; 59*724ba675SRob Herring 60*724ba675SRob Herring gpu@57000000 { 61*724ba675SRob Herring /* 62*724ba675SRob Herring * Node left disabled on purpose - the bootloader will enable 63*724ba675SRob Herring * it after having set the VPR up 64*724ba675SRob Herring */ 65*724ba675SRob Herring vdd-supply = <®_vdd_gpu>; 66*724ba675SRob Herring }; 67*724ba675SRob Herring 68*724ba675SRob Herring gpio@6000d000 { 69*724ba675SRob Herring /* I210 Gigabit Ethernet Controller Reset */ 70*724ba675SRob Herring lan-reset-n-hog { 71*724ba675SRob Herring gpio-hog; 72*724ba675SRob Herring gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>; 73*724ba675SRob Herring output-high; 74*724ba675SRob Herring line-name = "LAN_RESET_N"; 75*724ba675SRob Herring }; 76*724ba675SRob Herring 77*724ba675SRob Herring /* Control MXM3 pin 26 Reset Module Output Carrier Input */ 78*724ba675SRob Herring reset-moci-ctrl-hog { 79*724ba675SRob Herring gpio-hog; 80*724ba675SRob Herring gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; 81*724ba675SRob Herring output-high; 82*724ba675SRob Herring line-name = "RESET_MOCI_CTRL"; 83*724ba675SRob Herring }; 84*724ba675SRob Herring }; 85*724ba675SRob Herring 86*724ba675SRob Herring pinmux@70000868 { 87*724ba675SRob Herring pinctrl-names = "default"; 88*724ba675SRob Herring pinctrl-0 = <&state_default>; 89*724ba675SRob Herring 90*724ba675SRob Herring state_default: pinmux { 91*724ba675SRob Herring /* Analogue Audio (On-module) */ 92*724ba675SRob Herring dap3-fs-pp0 { 93*724ba675SRob Herring nvidia,pins = "dap3_fs_pp0"; 94*724ba675SRob Herring nvidia,function = "i2s2"; 95*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 96*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 97*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 98*724ba675SRob Herring }; 99*724ba675SRob Herring dap3-din-pp1 { 100*724ba675SRob Herring nvidia,pins = "dap3_din_pp1"; 101*724ba675SRob Herring nvidia,function = "i2s2"; 102*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 103*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 104*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 105*724ba675SRob Herring }; 106*724ba675SRob Herring dap3-dout-pp2 { 107*724ba675SRob Herring nvidia,pins = "dap3_dout_pp2"; 108*724ba675SRob Herring nvidia,function = "i2s2"; 109*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 110*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 111*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 112*724ba675SRob Herring }; 113*724ba675SRob Herring dap3-sclk-pp3 { 114*724ba675SRob Herring nvidia,pins = "dap3_sclk_pp3"; 115*724ba675SRob Herring nvidia,function = "i2s2"; 116*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 117*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 118*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 119*724ba675SRob Herring }; 120*724ba675SRob Herring dap-mclk1-pw4 { 121*724ba675SRob Herring nvidia,pins = "dap_mclk1_pw4"; 122*724ba675SRob Herring nvidia,function = "extperiph1"; 123*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 124*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 125*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 126*724ba675SRob Herring }; 127*724ba675SRob Herring 128*724ba675SRob Herring /* Apalis BKL1_ON */ 129*724ba675SRob Herring pbb5 { 130*724ba675SRob Herring nvidia,pins = "pbb5"; 131*724ba675SRob Herring nvidia,function = "vgp5"; 132*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 133*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 134*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 135*724ba675SRob Herring }; 136*724ba675SRob Herring 137*724ba675SRob Herring /* Apalis BKL1_PWM */ 138*724ba675SRob Herring pu6 { 139*724ba675SRob Herring nvidia,pins = "pu6"; 140*724ba675SRob Herring nvidia,function = "pwm3"; 141*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 142*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 143*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 144*724ba675SRob Herring }; 145*724ba675SRob Herring 146*724ba675SRob Herring /* Apalis CAM1_MCLK */ 147*724ba675SRob Herring cam-mclk-pcc0 { 148*724ba675SRob Herring nvidia,pins = "cam_mclk_pcc0"; 149*724ba675SRob Herring nvidia,function = "vi_alt3"; 150*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 151*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 152*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 153*724ba675SRob Herring }; 154*724ba675SRob Herring 155*724ba675SRob Herring /* Apalis Digital Audio */ 156*724ba675SRob Herring dap2-fs-pa2 { 157*724ba675SRob Herring nvidia,pins = "dap2_fs_pa2"; 158*724ba675SRob Herring nvidia,function = "hda"; 159*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 160*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 161*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 162*724ba675SRob Herring }; 163*724ba675SRob Herring dap2-sclk-pa3 { 164*724ba675SRob Herring nvidia,pins = "dap2_sclk_pa3"; 165*724ba675SRob Herring nvidia,function = "hda"; 166*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 167*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 168*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 169*724ba675SRob Herring }; 170*724ba675SRob Herring dap2-din-pa4 { 171*724ba675SRob Herring nvidia,pins = "dap2_din_pa4"; 172*724ba675SRob Herring nvidia,function = "hda"; 173*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 174*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 175*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 176*724ba675SRob Herring }; 177*724ba675SRob Herring dap2-dout-pa5 { 178*724ba675SRob Herring nvidia,pins = "dap2_dout_pa5"; 179*724ba675SRob Herring nvidia,function = "hda"; 180*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 181*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 182*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 183*724ba675SRob Herring }; 184*724ba675SRob Herring pbb3 { /* DAP1_RESET */ 185*724ba675SRob Herring nvidia,pins = "pbb3"; 186*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 187*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 188*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 189*724ba675SRob Herring }; 190*724ba675SRob Herring clk3-out-pee0 { 191*724ba675SRob Herring nvidia,pins = "clk3_out_pee0"; 192*724ba675SRob Herring nvidia,function = "extperiph3"; 193*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 194*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 195*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 196*724ba675SRob Herring }; 197*724ba675SRob Herring 198*724ba675SRob Herring /* Apalis GPIO */ 199*724ba675SRob Herring usb-vbus-en0-pn4 { 200*724ba675SRob Herring nvidia,pins = "usb_vbus_en0_pn4"; 201*724ba675SRob Herring nvidia,function = "rsvd2"; 202*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 203*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 204*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 205*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 206*724ba675SRob Herring }; 207*724ba675SRob Herring usb-vbus-en1-pn5 { 208*724ba675SRob Herring nvidia,pins = "usb_vbus_en1_pn5"; 209*724ba675SRob Herring nvidia,function = "rsvd2"; 210*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 211*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 212*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 213*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 214*724ba675SRob Herring }; 215*724ba675SRob Herring pex-l0-rst-n-pdd1 { 216*724ba675SRob Herring nvidia,pins = "pex_l0_rst_n_pdd1"; 217*724ba675SRob Herring nvidia,function = "rsvd2"; 218*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 219*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 220*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 221*724ba675SRob Herring }; 222*724ba675SRob Herring pex-l0-clkreq-n-pdd2 { 223*724ba675SRob Herring nvidia,pins = "pex_l0_clkreq_n_pdd2"; 224*724ba675SRob Herring nvidia,function = "rsvd2"; 225*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 226*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 227*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 228*724ba675SRob Herring }; 229*724ba675SRob Herring pex-l1-rst-n-pdd5 { 230*724ba675SRob Herring nvidia,pins = "pex_l1_rst_n_pdd5"; 231*724ba675SRob Herring nvidia,function = "rsvd2"; 232*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 233*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 234*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 235*724ba675SRob Herring }; 236*724ba675SRob Herring pex-l1-clkreq-n-pdd6 { 237*724ba675SRob Herring nvidia,pins = "pex_l1_clkreq_n_pdd6"; 238*724ba675SRob Herring nvidia,function = "rsvd2"; 239*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 240*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 241*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 242*724ba675SRob Herring }; 243*724ba675SRob Herring dp-hpd-pff0 { 244*724ba675SRob Herring nvidia,pins = "dp_hpd_pff0"; 245*724ba675SRob Herring nvidia,function = "dp"; 246*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 247*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 248*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 249*724ba675SRob Herring }; 250*724ba675SRob Herring pff2 { 251*724ba675SRob Herring nvidia,pins = "pff2"; 252*724ba675SRob Herring nvidia,function = "rsvd2"; 253*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 254*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 255*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 256*724ba675SRob Herring }; 257*724ba675SRob Herring owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */ 258*724ba675SRob Herring nvidia,pins = "owr"; 259*724ba675SRob Herring nvidia,function = "rsvd2"; 260*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 261*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 262*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 263*724ba675SRob Herring nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; 264*724ba675SRob Herring }; 265*724ba675SRob Herring 266*724ba675SRob Herring /* Apalis HDMI1_CEC */ 267*724ba675SRob Herring hdmi-cec-pee3 { 268*724ba675SRob Herring nvidia,pins = "hdmi_cec_pee3"; 269*724ba675SRob Herring nvidia,function = "cec"; 270*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 271*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 272*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 273*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 274*724ba675SRob Herring }; 275*724ba675SRob Herring 276*724ba675SRob Herring /* Apalis HDMI1_HPD */ 277*724ba675SRob Herring hdmi-int-pn7 { 278*724ba675SRob Herring nvidia,pins = "hdmi_int_pn7"; 279*724ba675SRob Herring nvidia,function = "rsvd1"; 280*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 281*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 282*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 283*724ba675SRob Herring nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; 284*724ba675SRob Herring }; 285*724ba675SRob Herring 286*724ba675SRob Herring /* Apalis I2C1 */ 287*724ba675SRob Herring gen1-i2c-scl-pc4 { 288*724ba675SRob Herring nvidia,pins = "gen1_i2c_scl_pc4"; 289*724ba675SRob Herring nvidia,function = "i2c1"; 290*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 291*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 292*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 293*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 294*724ba675SRob Herring }; 295*724ba675SRob Herring gen1-i2c-sda-pc5 { 296*724ba675SRob Herring nvidia,pins = "gen1_i2c_sda_pc5"; 297*724ba675SRob Herring nvidia,function = "i2c1"; 298*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 299*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 300*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 301*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 302*724ba675SRob Herring }; 303*724ba675SRob Herring 304*724ba675SRob Herring /* Apalis I2C3 (CAM) */ 305*724ba675SRob Herring cam-i2c-scl-pbb1 { 306*724ba675SRob Herring nvidia,pins = "cam_i2c_scl_pbb1"; 307*724ba675SRob Herring nvidia,function = "i2c3"; 308*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 309*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 310*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 311*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 312*724ba675SRob Herring }; 313*724ba675SRob Herring cam-i2c-sda-pbb2 { 314*724ba675SRob Herring nvidia,pins = "cam_i2c_sda_pbb2"; 315*724ba675SRob Herring nvidia,function = "i2c3"; 316*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 317*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 318*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 319*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 320*724ba675SRob Herring }; 321*724ba675SRob Herring 322*724ba675SRob Herring /* Apalis I2C4 (DDC) */ 323*724ba675SRob Herring ddc-scl-pv4 { 324*724ba675SRob Herring nvidia,pins = "ddc_scl_pv4"; 325*724ba675SRob Herring nvidia,function = "i2c4"; 326*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 327*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 328*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 329*724ba675SRob Herring nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; 330*724ba675SRob Herring }; 331*724ba675SRob Herring ddc-sda-pv5 { 332*724ba675SRob Herring nvidia,pins = "ddc_sda_pv5"; 333*724ba675SRob Herring nvidia,function = "i2c4"; 334*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 335*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 336*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 337*724ba675SRob Herring nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; 338*724ba675SRob Herring }; 339*724ba675SRob Herring 340*724ba675SRob Herring /* Apalis MMC1 */ 341*724ba675SRob Herring sdmmc1-cd-n-pv3 { /* CD# GPIO */ 342*724ba675SRob Herring nvidia,pins = "sdmmc1_wp_n_pv3"; 343*724ba675SRob Herring nvidia,function = "sdmmc1"; 344*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 345*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 346*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 347*724ba675SRob Herring }; 348*724ba675SRob Herring clk2-out-pw5 { /* D5 GPIO */ 349*724ba675SRob Herring nvidia,pins = "clk2_out_pw5"; 350*724ba675SRob Herring nvidia,function = "rsvd2"; 351*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 352*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 353*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 354*724ba675SRob Herring }; 355*724ba675SRob Herring sdmmc1-dat3-py4 { 356*724ba675SRob Herring nvidia,pins = "sdmmc1_dat3_py4"; 357*724ba675SRob Herring nvidia,function = "sdmmc1"; 358*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 359*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 360*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 361*724ba675SRob Herring }; 362*724ba675SRob Herring sdmmc1-dat2-py5 { 363*724ba675SRob Herring nvidia,pins = "sdmmc1_dat2_py5"; 364*724ba675SRob Herring nvidia,function = "sdmmc1"; 365*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 366*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 367*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 368*724ba675SRob Herring }; 369*724ba675SRob Herring sdmmc1-dat1-py6 { 370*724ba675SRob Herring nvidia,pins = "sdmmc1_dat1_py6"; 371*724ba675SRob Herring nvidia,function = "sdmmc1"; 372*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 373*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 374*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 375*724ba675SRob Herring }; 376*724ba675SRob Herring sdmmc1-dat0-py7 { 377*724ba675SRob Herring nvidia,pins = "sdmmc1_dat0_py7"; 378*724ba675SRob Herring nvidia,function = "sdmmc1"; 379*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 380*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 381*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 382*724ba675SRob Herring }; 383*724ba675SRob Herring sdmmc1-clk-pz0 { 384*724ba675SRob Herring nvidia,pins = "sdmmc1_clk_pz0"; 385*724ba675SRob Herring nvidia,function = "sdmmc1"; 386*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 387*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 388*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 389*724ba675SRob Herring }; 390*724ba675SRob Herring sdmmc1-cmd-pz1 { 391*724ba675SRob Herring nvidia,pins = "sdmmc1_cmd_pz1"; 392*724ba675SRob Herring nvidia,function = "sdmmc1"; 393*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 394*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 395*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 396*724ba675SRob Herring }; 397*724ba675SRob Herring clk2-req-pcc5 { /* D4 GPIO */ 398*724ba675SRob Herring nvidia,pins = "clk2_req_pcc5"; 399*724ba675SRob Herring nvidia,function = "rsvd2"; 400*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 401*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 402*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 403*724ba675SRob Herring }; 404*724ba675SRob Herring sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */ 405*724ba675SRob Herring nvidia,pins = "sdmmc3_clk_lb_in_pee5"; 406*724ba675SRob Herring nvidia,function = "rsvd2"; 407*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 408*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 409*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 410*724ba675SRob Herring }; 411*724ba675SRob Herring usb-vbus-en2-pff1 { /* D7 GPIO */ 412*724ba675SRob Herring nvidia,pins = "usb_vbus_en2_pff1"; 413*724ba675SRob Herring nvidia,function = "rsvd2"; 414*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 415*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 416*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 417*724ba675SRob Herring }; 418*724ba675SRob Herring 419*724ba675SRob Herring /* Apalis PWM */ 420*724ba675SRob Herring ph0 { 421*724ba675SRob Herring nvidia,pins = "ph0"; 422*724ba675SRob Herring nvidia,function = "pwm0"; 423*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 424*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 425*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 426*724ba675SRob Herring }; 427*724ba675SRob Herring ph1 { 428*724ba675SRob Herring nvidia,pins = "ph1"; 429*724ba675SRob Herring nvidia,function = "pwm1"; 430*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 431*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 432*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 433*724ba675SRob Herring }; 434*724ba675SRob Herring ph2 { 435*724ba675SRob Herring nvidia,pins = "ph2"; 436*724ba675SRob Herring nvidia,function = "pwm2"; 437*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 438*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 439*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 440*724ba675SRob Herring }; 441*724ba675SRob Herring /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ 442*724ba675SRob Herring ph3 { 443*724ba675SRob Herring nvidia,pins = "ph3"; 444*724ba675SRob Herring nvidia,function = "pwm3"; 445*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 446*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 447*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 448*724ba675SRob Herring }; 449*724ba675SRob Herring 450*724ba675SRob Herring /* Apalis SATA1_ACT# */ 451*724ba675SRob Herring dap1-dout-pn2 { 452*724ba675SRob Herring nvidia,pins = "dap1_dout_pn2"; 453*724ba675SRob Herring nvidia,function = "gmi"; 454*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 455*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 456*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 457*724ba675SRob Herring }; 458*724ba675SRob Herring 459*724ba675SRob Herring /* Apalis SD1 */ 460*724ba675SRob Herring sdmmc3-clk-pa6 { 461*724ba675SRob Herring nvidia,pins = "sdmmc3_clk_pa6"; 462*724ba675SRob Herring nvidia,function = "sdmmc3"; 463*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 464*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 465*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 466*724ba675SRob Herring }; 467*724ba675SRob Herring sdmmc3-cmd-pa7 { 468*724ba675SRob Herring nvidia,pins = "sdmmc3_cmd_pa7"; 469*724ba675SRob Herring nvidia,function = "sdmmc3"; 470*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 471*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 472*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 473*724ba675SRob Herring }; 474*724ba675SRob Herring sdmmc3-dat3-pb4 { 475*724ba675SRob Herring nvidia,pins = "sdmmc3_dat3_pb4"; 476*724ba675SRob Herring nvidia,function = "sdmmc3"; 477*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 478*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 479*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 480*724ba675SRob Herring }; 481*724ba675SRob Herring sdmmc3-dat2-pb5 { 482*724ba675SRob Herring nvidia,pins = "sdmmc3_dat2_pb5"; 483*724ba675SRob Herring nvidia,function = "sdmmc3"; 484*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 485*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 486*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 487*724ba675SRob Herring }; 488*724ba675SRob Herring sdmmc3-dat1-pb6 { 489*724ba675SRob Herring nvidia,pins = "sdmmc3_dat1_pb6"; 490*724ba675SRob Herring nvidia,function = "sdmmc3"; 491*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 492*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 493*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 494*724ba675SRob Herring }; 495*724ba675SRob Herring sdmmc3-dat0-pb7 { 496*724ba675SRob Herring nvidia,pins = "sdmmc3_dat0_pb7"; 497*724ba675SRob Herring nvidia,function = "sdmmc3"; 498*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 499*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 500*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 501*724ba675SRob Herring }; 502*724ba675SRob Herring sdmmc3-cd-n-pv2 { /* CD# GPIO */ 503*724ba675SRob Herring nvidia,pins = "sdmmc3_cd_n_pv2"; 504*724ba675SRob Herring nvidia,function = "rsvd3"; 505*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 506*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 507*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 508*724ba675SRob Herring }; 509*724ba675SRob Herring 510*724ba675SRob Herring /* Apalis SPDIF */ 511*724ba675SRob Herring spdif-out-pk5 { 512*724ba675SRob Herring nvidia,pins = "spdif_out_pk5"; 513*724ba675SRob Herring nvidia,function = "spdif"; 514*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 515*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 516*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 517*724ba675SRob Herring }; 518*724ba675SRob Herring spdif-in-pk6 { 519*724ba675SRob Herring nvidia,pins = "spdif_in_pk6"; 520*724ba675SRob Herring nvidia,function = "spdif"; 521*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 522*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 523*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 524*724ba675SRob Herring }; 525*724ba675SRob Herring 526*724ba675SRob Herring /* Apalis SPI1 */ 527*724ba675SRob Herring ulpi-clk-py0 { 528*724ba675SRob Herring nvidia,pins = "ulpi_clk_py0"; 529*724ba675SRob Herring nvidia,function = "spi1"; 530*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 531*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 532*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 533*724ba675SRob Herring }; 534*724ba675SRob Herring ulpi-dir-py1 { 535*724ba675SRob Herring nvidia,pins = "ulpi_dir_py1"; 536*724ba675SRob Herring nvidia,function = "spi1"; 537*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 538*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 539*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 540*724ba675SRob Herring }; 541*724ba675SRob Herring ulpi-nxt-py2 { 542*724ba675SRob Herring nvidia,pins = "ulpi_nxt_py2"; 543*724ba675SRob Herring nvidia,function = "spi1"; 544*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 545*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 546*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 547*724ba675SRob Herring }; 548*724ba675SRob Herring ulpi-stp-py3 { 549*724ba675SRob Herring nvidia,pins = "ulpi_stp_py3"; 550*724ba675SRob Herring nvidia,function = "spi1"; 551*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 552*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 553*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 554*724ba675SRob Herring }; 555*724ba675SRob Herring 556*724ba675SRob Herring /* Apalis SPI2 */ 557*724ba675SRob Herring pg5 { 558*724ba675SRob Herring nvidia,pins = "pg5"; 559*724ba675SRob Herring nvidia,function = "spi4"; 560*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 561*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 562*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 563*724ba675SRob Herring }; 564*724ba675SRob Herring pg6 { 565*724ba675SRob Herring nvidia,pins = "pg6"; 566*724ba675SRob Herring nvidia,function = "spi4"; 567*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 568*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 569*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 570*724ba675SRob Herring }; 571*724ba675SRob Herring pg7 { 572*724ba675SRob Herring nvidia,pins = "pg7"; 573*724ba675SRob Herring nvidia,function = "spi4"; 574*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 575*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 576*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 577*724ba675SRob Herring }; 578*724ba675SRob Herring pi3 { 579*724ba675SRob Herring nvidia,pins = "pi3"; 580*724ba675SRob Herring nvidia,function = "spi4"; 581*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 582*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 583*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 584*724ba675SRob Herring }; 585*724ba675SRob Herring 586*724ba675SRob Herring /* Apalis UART1 */ 587*724ba675SRob Herring pb1 { /* DCD GPIO */ 588*724ba675SRob Herring nvidia,pins = "pb1"; 589*724ba675SRob Herring nvidia,function = "rsvd2"; 590*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 591*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 592*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 593*724ba675SRob Herring }; 594*724ba675SRob Herring pk7 { /* RI GPIO */ 595*724ba675SRob Herring nvidia,pins = "pk7"; 596*724ba675SRob Herring nvidia,function = "rsvd2"; 597*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 598*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 599*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 600*724ba675SRob Herring }; 601*724ba675SRob Herring uart1-txd-pu0 { 602*724ba675SRob Herring nvidia,pins = "pu0"; 603*724ba675SRob Herring nvidia,function = "uarta"; 604*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 605*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 606*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 607*724ba675SRob Herring }; 608*724ba675SRob Herring uart1-rxd-pu1 { 609*724ba675SRob Herring nvidia,pins = "pu1"; 610*724ba675SRob Herring nvidia,function = "uarta"; 611*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 612*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 613*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 614*724ba675SRob Herring }; 615*724ba675SRob Herring uart1-cts-n-pu2 { 616*724ba675SRob Herring nvidia,pins = "pu2"; 617*724ba675SRob Herring nvidia,function = "uarta"; 618*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 619*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 620*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 621*724ba675SRob Herring }; 622*724ba675SRob Herring uart1-rts-n-pu3 { 623*724ba675SRob Herring nvidia,pins = "pu3"; 624*724ba675SRob Herring nvidia,function = "uarta"; 625*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 626*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 627*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 628*724ba675SRob Herring }; 629*724ba675SRob Herring uart3-cts-n-pa1 { /* DSR GPIO */ 630*724ba675SRob Herring nvidia,pins = "uart3_cts_n_pa1"; 631*724ba675SRob Herring nvidia,function = "gmi"; 632*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 633*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 634*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 635*724ba675SRob Herring }; 636*724ba675SRob Herring uart3-rts-n-pc0 { /* DTR GPIO */ 637*724ba675SRob Herring nvidia,pins = "uart3_rts_n_pc0"; 638*724ba675SRob Herring nvidia,function = "gmi"; 639*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 640*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 641*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 642*724ba675SRob Herring }; 643*724ba675SRob Herring 644*724ba675SRob Herring /* Apalis UART2 */ 645*724ba675SRob Herring uart2-txd-pc2 { 646*724ba675SRob Herring nvidia,pins = "uart2_txd_pc2"; 647*724ba675SRob Herring nvidia,function = "irda"; 648*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 649*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 650*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 651*724ba675SRob Herring }; 652*724ba675SRob Herring uart2-rxd-pc3 { 653*724ba675SRob Herring nvidia,pins = "uart2_rxd_pc3"; 654*724ba675SRob Herring nvidia,function = "irda"; 655*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 656*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 657*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 658*724ba675SRob Herring }; 659*724ba675SRob Herring uart2-cts-n-pj5 { 660*724ba675SRob Herring nvidia,pins = "uart2_cts_n_pj5"; 661*724ba675SRob Herring nvidia,function = "uartb"; 662*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 663*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 664*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 665*724ba675SRob Herring }; 666*724ba675SRob Herring uart2-rts-n-pj6 { 667*724ba675SRob Herring nvidia,pins = "uart2_rts_n_pj6"; 668*724ba675SRob Herring nvidia,function = "uartb"; 669*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 670*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 671*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 672*724ba675SRob Herring }; 673*724ba675SRob Herring 674*724ba675SRob Herring /* Apalis UART3 */ 675*724ba675SRob Herring uart3-txd-pw6 { 676*724ba675SRob Herring nvidia,pins = "uart3_txd_pw6"; 677*724ba675SRob Herring nvidia,function = "uartc"; 678*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 679*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 680*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 681*724ba675SRob Herring }; 682*724ba675SRob Herring uart3-rxd-pw7 { 683*724ba675SRob Herring nvidia,pins = "uart3_rxd_pw7"; 684*724ba675SRob Herring nvidia,function = "uartc"; 685*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 686*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 687*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 688*724ba675SRob Herring }; 689*724ba675SRob Herring 690*724ba675SRob Herring /* Apalis UART4 */ 691*724ba675SRob Herring uart4-rxd-pb0 { 692*724ba675SRob Herring nvidia,pins = "pb0"; 693*724ba675SRob Herring nvidia,function = "uartd"; 694*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 695*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 696*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 697*724ba675SRob Herring }; 698*724ba675SRob Herring uart4-txd-pj7 { 699*724ba675SRob Herring nvidia,pins = "pj7"; 700*724ba675SRob Herring nvidia,function = "uartd"; 701*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 702*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 703*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 704*724ba675SRob Herring }; 705*724ba675SRob Herring 706*724ba675SRob Herring /* Apalis USBH_EN */ 707*724ba675SRob Herring gen2-i2c-sda-pt6 { 708*724ba675SRob Herring nvidia,pins = "gen2_i2c_sda_pt6"; 709*724ba675SRob Herring nvidia,function = "rsvd2"; 710*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 711*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 712*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 713*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 714*724ba675SRob Herring }; 715*724ba675SRob Herring 716*724ba675SRob Herring /* Apalis USBH_OC# */ 717*724ba675SRob Herring pbb0 { 718*724ba675SRob Herring nvidia,pins = "pbb0"; 719*724ba675SRob Herring nvidia,function = "vgp6"; 720*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 721*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 722*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 723*724ba675SRob Herring }; 724*724ba675SRob Herring 725*724ba675SRob Herring /* Apalis USBO1_EN */ 726*724ba675SRob Herring gen2-i2c-scl-pt5 { 727*724ba675SRob Herring nvidia,pins = "gen2_i2c_scl_pt5"; 728*724ba675SRob Herring nvidia,function = "rsvd2"; 729*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 730*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 731*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 732*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 733*724ba675SRob Herring }; 734*724ba675SRob Herring 735*724ba675SRob Herring /* Apalis USBO1_OC# */ 736*724ba675SRob Herring pbb4 { 737*724ba675SRob Herring nvidia,pins = "pbb4"; 738*724ba675SRob Herring nvidia,function = "vgp4"; 739*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 740*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 741*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 742*724ba675SRob Herring }; 743*724ba675SRob Herring 744*724ba675SRob Herring /* Apalis WAKE1_MICO */ 745*724ba675SRob Herring pex-wake-n-pdd3 { 746*724ba675SRob Herring nvidia,pins = "pex_wake_n_pdd3"; 747*724ba675SRob Herring nvidia,function = "rsvd2"; 748*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 749*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 750*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 751*724ba675SRob Herring }; 752*724ba675SRob Herring 753*724ba675SRob Herring /* CORE_PWR_REQ */ 754*724ba675SRob Herring core-pwr-req { 755*724ba675SRob Herring nvidia,pins = "core_pwr_req"; 756*724ba675SRob Herring nvidia,function = "pwron"; 757*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 758*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 759*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 760*724ba675SRob Herring }; 761*724ba675SRob Herring 762*724ba675SRob Herring /* CPU_PWR_REQ */ 763*724ba675SRob Herring cpu-pwr-req { 764*724ba675SRob Herring nvidia,pins = "cpu_pwr_req"; 765*724ba675SRob Herring nvidia,function = "cpu"; 766*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 767*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 768*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 769*724ba675SRob Herring }; 770*724ba675SRob Herring 771*724ba675SRob Herring /* DVFS */ 772*724ba675SRob Herring dvfs-pwm-px0 { 773*724ba675SRob Herring nvidia,pins = "dvfs_pwm_px0"; 774*724ba675SRob Herring nvidia,function = "cldvfs"; 775*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 776*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 777*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 778*724ba675SRob Herring }; 779*724ba675SRob Herring dvfs-clk-px2 { 780*724ba675SRob Herring nvidia,pins = "dvfs_clk_px2"; 781*724ba675SRob Herring nvidia,function = "cldvfs"; 782*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 783*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 784*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 785*724ba675SRob Herring }; 786*724ba675SRob Herring 787*724ba675SRob Herring /* eMMC */ 788*724ba675SRob Herring sdmmc4-dat0-paa0 { 789*724ba675SRob Herring nvidia,pins = "sdmmc4_dat0_paa0"; 790*724ba675SRob Herring nvidia,function = "sdmmc4"; 791*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 792*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 793*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 794*724ba675SRob Herring }; 795*724ba675SRob Herring sdmmc4-dat1-paa1 { 796*724ba675SRob Herring nvidia,pins = "sdmmc4_dat1_paa1"; 797*724ba675SRob Herring nvidia,function = "sdmmc4"; 798*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 799*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 800*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 801*724ba675SRob Herring }; 802*724ba675SRob Herring sdmmc4-dat2-paa2 { 803*724ba675SRob Herring nvidia,pins = "sdmmc4_dat2_paa2"; 804*724ba675SRob Herring nvidia,function = "sdmmc4"; 805*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 806*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 807*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 808*724ba675SRob Herring }; 809*724ba675SRob Herring sdmmc4-dat3-paa3 { 810*724ba675SRob Herring nvidia,pins = "sdmmc4_dat3_paa3"; 811*724ba675SRob Herring nvidia,function = "sdmmc4"; 812*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 813*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 814*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 815*724ba675SRob Herring }; 816*724ba675SRob Herring sdmmc4-dat4-paa4 { 817*724ba675SRob Herring nvidia,pins = "sdmmc4_dat4_paa4"; 818*724ba675SRob Herring nvidia,function = "sdmmc4"; 819*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 820*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 821*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 822*724ba675SRob Herring }; 823*724ba675SRob Herring sdmmc4-dat5-paa5 { 824*724ba675SRob Herring nvidia,pins = "sdmmc4_dat5_paa5"; 825*724ba675SRob Herring nvidia,function = "sdmmc4"; 826*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 827*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 828*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 829*724ba675SRob Herring }; 830*724ba675SRob Herring sdmmc4-dat6-paa6 { 831*724ba675SRob Herring nvidia,pins = "sdmmc4_dat6_paa6"; 832*724ba675SRob Herring nvidia,function = "sdmmc4"; 833*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 834*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 835*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 836*724ba675SRob Herring }; 837*724ba675SRob Herring sdmmc4-dat7-paa7 { 838*724ba675SRob Herring nvidia,pins = "sdmmc4_dat7_paa7"; 839*724ba675SRob Herring nvidia,function = "sdmmc4"; 840*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 841*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 842*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 843*724ba675SRob Herring }; 844*724ba675SRob Herring sdmmc4-clk-pcc4 { 845*724ba675SRob Herring nvidia,pins = "sdmmc4_clk_pcc4"; 846*724ba675SRob Herring nvidia,function = "sdmmc4"; 847*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 848*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 849*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 850*724ba675SRob Herring }; 851*724ba675SRob Herring sdmmc4-cmd-pt7 { 852*724ba675SRob Herring nvidia,pins = "sdmmc4_cmd_pt7"; 853*724ba675SRob Herring nvidia,function = "sdmmc4"; 854*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 855*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 856*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 857*724ba675SRob Herring }; 858*724ba675SRob Herring 859*724ba675SRob Herring /* JTAG_RTCK */ 860*724ba675SRob Herring jtag-rtck { 861*724ba675SRob Herring nvidia,pins = "jtag_rtck"; 862*724ba675SRob Herring nvidia,function = "rtck"; 863*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 864*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 865*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 866*724ba675SRob Herring }; 867*724ba675SRob Herring 868*724ba675SRob Herring /* LAN_DEV_OFF# */ 869*724ba675SRob Herring ulpi-data5-po6 { 870*724ba675SRob Herring nvidia,pins = "ulpi_data5_po6"; 871*724ba675SRob Herring nvidia,function = "ulpi"; 872*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 873*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 874*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 875*724ba675SRob Herring }; 876*724ba675SRob Herring 877*724ba675SRob Herring /* LAN_RESET# */ 878*724ba675SRob Herring kb-row10-ps2 { 879*724ba675SRob Herring nvidia,pins = "kb_row10_ps2"; 880*724ba675SRob Herring nvidia,function = "rsvd2"; 881*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 882*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 883*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 884*724ba675SRob Herring }; 885*724ba675SRob Herring 886*724ba675SRob Herring /* LAN_WAKE# */ 887*724ba675SRob Herring ulpi-data4-po5 { 888*724ba675SRob Herring nvidia,pins = "ulpi_data4_po5"; 889*724ba675SRob Herring nvidia,function = "ulpi"; 890*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 891*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 892*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 893*724ba675SRob Herring }; 894*724ba675SRob Herring 895*724ba675SRob Herring /* MCU_INT1# */ 896*724ba675SRob Herring pk2 { 897*724ba675SRob Herring nvidia,pins = "pk2"; 898*724ba675SRob Herring nvidia,function = "rsvd1"; 899*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 900*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 901*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 902*724ba675SRob Herring }; 903*724ba675SRob Herring 904*724ba675SRob Herring /* MCU_INT2# */ 905*724ba675SRob Herring pj2 { 906*724ba675SRob Herring nvidia,pins = "pj2"; 907*724ba675SRob Herring nvidia,function = "rsvd1"; 908*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 909*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 910*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 911*724ba675SRob Herring }; 912*724ba675SRob Herring 913*724ba675SRob Herring /* MCU_INT3# */ 914*724ba675SRob Herring pi5 { 915*724ba675SRob Herring nvidia,pins = "pi5"; 916*724ba675SRob Herring nvidia,function = "rsvd2"; 917*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 918*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 919*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 920*724ba675SRob Herring }; 921*724ba675SRob Herring 922*724ba675SRob Herring /* MCU_INT4# */ 923*724ba675SRob Herring pj0 { 924*724ba675SRob Herring nvidia,pins = "pj0"; 925*724ba675SRob Herring nvidia,function = "rsvd1"; 926*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 927*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 928*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 929*724ba675SRob Herring }; 930*724ba675SRob Herring 931*724ba675SRob Herring /* MCU_RESET */ 932*724ba675SRob Herring pbb6 { 933*724ba675SRob Herring nvidia,pins = "pbb6"; 934*724ba675SRob Herring nvidia,function = "rsvd2"; 935*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 936*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 937*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 938*724ba675SRob Herring }; 939*724ba675SRob Herring 940*724ba675SRob Herring /* MCU SPI */ 941*724ba675SRob Herring gpio-x4-aud-px4 { 942*724ba675SRob Herring nvidia,pins = "gpio_x4_aud_px4"; 943*724ba675SRob Herring nvidia,function = "spi2"; 944*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 945*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 946*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 947*724ba675SRob Herring }; 948*724ba675SRob Herring gpio-x5-aud-px5 { 949*724ba675SRob Herring nvidia,pins = "gpio_x5_aud_px5"; 950*724ba675SRob Herring nvidia,function = "spi2"; 951*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 952*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 953*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 954*724ba675SRob Herring }; 955*724ba675SRob Herring gpio-x6-aud-px6 { /* MCU_CS */ 956*724ba675SRob Herring nvidia,pins = "gpio_x6_aud_px6"; 957*724ba675SRob Herring nvidia,function = "spi2"; 958*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 959*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 960*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 961*724ba675SRob Herring }; 962*724ba675SRob Herring gpio-x7-aud-px7 { 963*724ba675SRob Herring nvidia,pins = "gpio_x7_aud_px7"; 964*724ba675SRob Herring nvidia,function = "spi2"; 965*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 966*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 967*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 968*724ba675SRob Herring }; 969*724ba675SRob Herring gpio-w2-aud-pw2 { /* MCU_CSEZP */ 970*724ba675SRob Herring nvidia,pins = "gpio_w2_aud_pw2"; 971*724ba675SRob Herring nvidia,function = "spi2"; 972*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 973*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 974*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 975*724ba675SRob Herring }; 976*724ba675SRob Herring 977*724ba675SRob Herring /* PMIC_CLK_32K */ 978*724ba675SRob Herring clk-32k-in { 979*724ba675SRob Herring nvidia,pins = "clk_32k_in"; 980*724ba675SRob Herring nvidia,function = "clk"; 981*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 982*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 983*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 984*724ba675SRob Herring }; 985*724ba675SRob Herring 986*724ba675SRob Herring /* PMIC_CPU_OC_INT */ 987*724ba675SRob Herring clk-32k-out-pa0 { 988*724ba675SRob Herring nvidia,pins = "clk_32k_out_pa0"; 989*724ba675SRob Herring nvidia,function = "soc"; 990*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 991*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 992*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 993*724ba675SRob Herring }; 994*724ba675SRob Herring 995*724ba675SRob Herring /* PWR_I2C */ 996*724ba675SRob Herring pwr-i2c-scl-pz6 { 997*724ba675SRob Herring nvidia,pins = "pwr_i2c_scl_pz6"; 998*724ba675SRob Herring nvidia,function = "i2cpwr"; 999*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1000*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1001*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1002*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 1003*724ba675SRob Herring }; 1004*724ba675SRob Herring pwr-i2c-sda-pz7 { 1005*724ba675SRob Herring nvidia,pins = "pwr_i2c_sda_pz7"; 1006*724ba675SRob Herring nvidia,function = "i2cpwr"; 1007*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1008*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1009*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1010*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 1011*724ba675SRob Herring }; 1012*724ba675SRob Herring 1013*724ba675SRob Herring /* PWR_INT_N */ 1014*724ba675SRob Herring pwr-int-n { 1015*724ba675SRob Herring nvidia,pins = "pwr_int_n"; 1016*724ba675SRob Herring nvidia,function = "pmi"; 1017*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1018*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1019*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1020*724ba675SRob Herring }; 1021*724ba675SRob Herring 1022*724ba675SRob Herring /* RESET_MOCI_CTRL */ 1023*724ba675SRob Herring pu4 { 1024*724ba675SRob Herring nvidia,pins = "pu4"; 1025*724ba675SRob Herring nvidia,function = "gmi"; 1026*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1027*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1028*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1029*724ba675SRob Herring }; 1030*724ba675SRob Herring 1031*724ba675SRob Herring /* RESET_OUT_N */ 1032*724ba675SRob Herring reset-out-n { 1033*724ba675SRob Herring nvidia,pins = "reset_out_n"; 1034*724ba675SRob Herring nvidia,function = "reset_out_n"; 1035*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1036*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1037*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1038*724ba675SRob Herring }; 1039*724ba675SRob Herring 1040*724ba675SRob Herring /* SHIFT_CTRL_DIR_IN */ 1041*724ba675SRob Herring kb-row0-pr0 { 1042*724ba675SRob Herring nvidia,pins = "kb_row0_pr0"; 1043*724ba675SRob Herring nvidia,function = "rsvd2"; 1044*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1045*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1046*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1047*724ba675SRob Herring }; 1048*724ba675SRob Herring kb-row1-pr1 { 1049*724ba675SRob Herring nvidia,pins = "kb_row1_pr1"; 1050*724ba675SRob Herring nvidia,function = "rsvd2"; 1051*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1052*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1053*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1054*724ba675SRob Herring }; 1055*724ba675SRob Herring 1056*724ba675SRob Herring /* Configure level-shifter as output for HDA */ 1057*724ba675SRob Herring kb-row11-ps3 { 1058*724ba675SRob Herring nvidia,pins = "kb_row11_ps3"; 1059*724ba675SRob Herring nvidia,function = "rsvd2"; 1060*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1061*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1062*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1063*724ba675SRob Herring }; 1064*724ba675SRob Herring 1065*724ba675SRob Herring /* SHIFT_CTRL_DIR_OUT */ 1066*724ba675SRob Herring kb-col5-pq5 { 1067*724ba675SRob Herring nvidia,pins = "kb_col5_pq5"; 1068*724ba675SRob Herring nvidia,function = "rsvd2"; 1069*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1070*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1071*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1072*724ba675SRob Herring }; 1073*724ba675SRob Herring kb-col6-pq6 { 1074*724ba675SRob Herring nvidia,pins = "kb_col6_pq6"; 1075*724ba675SRob Herring nvidia,function = "rsvd2"; 1076*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1077*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1078*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1079*724ba675SRob Herring }; 1080*724ba675SRob Herring kb-col7-pq7 { 1081*724ba675SRob Herring nvidia,pins = "kb_col7_pq7"; 1082*724ba675SRob Herring nvidia,function = "rsvd2"; 1083*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1084*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1085*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1086*724ba675SRob Herring }; 1087*724ba675SRob Herring 1088*724ba675SRob Herring /* SHIFT_CTRL_OE */ 1089*724ba675SRob Herring kb-col0-pq0 { 1090*724ba675SRob Herring nvidia,pins = "kb_col0_pq0"; 1091*724ba675SRob Herring nvidia,function = "rsvd2"; 1092*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1093*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1094*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1095*724ba675SRob Herring }; 1096*724ba675SRob Herring kb-col1-pq1 { 1097*724ba675SRob Herring nvidia,pins = "kb_col1_pq1"; 1098*724ba675SRob Herring nvidia,function = "rsvd2"; 1099*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1100*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1101*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1102*724ba675SRob Herring }; 1103*724ba675SRob Herring kb-col2-pq2 { 1104*724ba675SRob Herring nvidia,pins = "kb_col2_pq2"; 1105*724ba675SRob Herring nvidia,function = "rsvd2"; 1106*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1107*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1108*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1109*724ba675SRob Herring }; 1110*724ba675SRob Herring kb-col4-pq4 { 1111*724ba675SRob Herring nvidia,pins = "kb_col4_pq4"; 1112*724ba675SRob Herring nvidia,function = "kbc"; 1113*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1114*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1115*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1116*724ba675SRob Herring }; 1117*724ba675SRob Herring kb-row2-pr2 { 1118*724ba675SRob Herring nvidia,pins = "kb_row2_pr2"; 1119*724ba675SRob Herring nvidia,function = "rsvd2"; 1120*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1121*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1122*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1123*724ba675SRob Herring }; 1124*724ba675SRob Herring 1125*724ba675SRob Herring /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */ 1126*724ba675SRob Herring pi6 { 1127*724ba675SRob Herring nvidia,pins = "pi6"; 1128*724ba675SRob Herring nvidia,function = "rsvd1"; 1129*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1130*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1131*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1132*724ba675SRob Herring }; 1133*724ba675SRob Herring 1134*724ba675SRob Herring /* TOUCH_INT */ 1135*724ba675SRob Herring gpio-w3-aud-pw3 { 1136*724ba675SRob Herring nvidia,pins = "gpio_w3_aud_pw3"; 1137*724ba675SRob Herring nvidia,function = "spi6"; 1138*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1139*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1140*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1141*724ba675SRob Herring }; 1142*724ba675SRob Herring 1143*724ba675SRob Herring pc7 { /* NC */ 1144*724ba675SRob Herring nvidia,pins = "pc7"; 1145*724ba675SRob Herring nvidia,function = "rsvd1"; 1146*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1147*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1148*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1149*724ba675SRob Herring }; 1150*724ba675SRob Herring pg0 { /* NC */ 1151*724ba675SRob Herring nvidia,pins = "pg0"; 1152*724ba675SRob Herring nvidia,function = "rsvd1"; 1153*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1154*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1155*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1156*724ba675SRob Herring }; 1157*724ba675SRob Herring pg1 { /* NC */ 1158*724ba675SRob Herring nvidia,pins = "pg1"; 1159*724ba675SRob Herring nvidia,function = "rsvd1"; 1160*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1161*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1162*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1163*724ba675SRob Herring }; 1164*724ba675SRob Herring pg2 { /* NC */ 1165*724ba675SRob Herring nvidia,pins = "pg2"; 1166*724ba675SRob Herring nvidia,function = "rsvd1"; 1167*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1168*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1169*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1170*724ba675SRob Herring }; 1171*724ba675SRob Herring pg3 { /* NC */ 1172*724ba675SRob Herring nvidia,pins = "pg3"; 1173*724ba675SRob Herring nvidia,function = "rsvd1"; 1174*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1175*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1176*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1177*724ba675SRob Herring }; 1178*724ba675SRob Herring pg4 { /* NC */ 1179*724ba675SRob Herring nvidia,pins = "pg4"; 1180*724ba675SRob Herring nvidia,function = "rsvd1"; 1181*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1182*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1183*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1184*724ba675SRob Herring }; 1185*724ba675SRob Herring ph4 { /* NC */ 1186*724ba675SRob Herring nvidia,pins = "ph4"; 1187*724ba675SRob Herring nvidia,function = "rsvd2"; 1188*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1189*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1190*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1191*724ba675SRob Herring }; 1192*724ba675SRob Herring ph5 { /* NC */ 1193*724ba675SRob Herring nvidia,pins = "ph5"; 1194*724ba675SRob Herring nvidia,function = "rsvd2"; 1195*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1196*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1197*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1198*724ba675SRob Herring }; 1199*724ba675SRob Herring ph6 { /* NC */ 1200*724ba675SRob Herring nvidia,pins = "ph6"; 1201*724ba675SRob Herring nvidia,function = "gmi"; 1202*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1203*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1204*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1205*724ba675SRob Herring }; 1206*724ba675SRob Herring ph7 { /* NC */ 1207*724ba675SRob Herring nvidia,pins = "ph7"; 1208*724ba675SRob Herring nvidia,function = "gmi"; 1209*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1210*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1211*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1212*724ba675SRob Herring }; 1213*724ba675SRob Herring pi0 { /* NC */ 1214*724ba675SRob Herring nvidia,pins = "pi0"; 1215*724ba675SRob Herring nvidia,function = "rsvd1"; 1216*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1217*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1218*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1219*724ba675SRob Herring }; 1220*724ba675SRob Herring pi1 { /* NC */ 1221*724ba675SRob Herring nvidia,pins = "pi1"; 1222*724ba675SRob Herring nvidia,function = "rsvd1"; 1223*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1224*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1225*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1226*724ba675SRob Herring }; 1227*724ba675SRob Herring pi2 { /* NC */ 1228*724ba675SRob Herring nvidia,pins = "pi2"; 1229*724ba675SRob Herring nvidia,function = "rsvd4"; 1230*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1231*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1232*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1233*724ba675SRob Herring }; 1234*724ba675SRob Herring pi4 { /* NC */ 1235*724ba675SRob Herring nvidia,pins = "pi4"; 1236*724ba675SRob Herring nvidia,function = "gmi"; 1237*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1238*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1239*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1240*724ba675SRob Herring }; 1241*724ba675SRob Herring pi7 { /* NC */ 1242*724ba675SRob Herring nvidia,pins = "pi7"; 1243*724ba675SRob Herring nvidia,function = "rsvd1"; 1244*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1245*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1246*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1247*724ba675SRob Herring }; 1248*724ba675SRob Herring pk0 { /* NC */ 1249*724ba675SRob Herring nvidia,pins = "pk0"; 1250*724ba675SRob Herring nvidia,function = "rsvd1"; 1251*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1252*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1253*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1254*724ba675SRob Herring }; 1255*724ba675SRob Herring pk1 { /* NC */ 1256*724ba675SRob Herring nvidia,pins = "pk1"; 1257*724ba675SRob Herring nvidia,function = "rsvd4"; 1258*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1259*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1260*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1261*724ba675SRob Herring }; 1262*724ba675SRob Herring pk3 { /* NC */ 1263*724ba675SRob Herring nvidia,pins = "pk3"; 1264*724ba675SRob Herring nvidia,function = "gmi"; 1265*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1266*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1267*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1268*724ba675SRob Herring }; 1269*724ba675SRob Herring pk4 { /* NC */ 1270*724ba675SRob Herring nvidia,pins = "pk4"; 1271*724ba675SRob Herring nvidia,function = "rsvd2"; 1272*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1273*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1274*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1275*724ba675SRob Herring }; 1276*724ba675SRob Herring dap1-fs-pn0 { /* NC */ 1277*724ba675SRob Herring nvidia,pins = "dap1_fs_pn0"; 1278*724ba675SRob Herring nvidia,function = "rsvd4"; 1279*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1280*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1281*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1282*724ba675SRob Herring }; 1283*724ba675SRob Herring dap1-din-pn1 { /* NC */ 1284*724ba675SRob Herring nvidia,pins = "dap1_din_pn1"; 1285*724ba675SRob Herring nvidia,function = "rsvd4"; 1286*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1287*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1288*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1289*724ba675SRob Herring }; 1290*724ba675SRob Herring dap1-sclk-pn3 { /* NC */ 1291*724ba675SRob Herring nvidia,pins = "dap1_sclk_pn3"; 1292*724ba675SRob Herring nvidia,function = "rsvd4"; 1293*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1294*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1295*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1296*724ba675SRob Herring }; 1297*724ba675SRob Herring ulpi-data7-po0 { /* NC */ 1298*724ba675SRob Herring nvidia,pins = "ulpi_data7_po0"; 1299*724ba675SRob Herring nvidia,function = "ulpi"; 1300*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1301*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1302*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1303*724ba675SRob Herring }; 1304*724ba675SRob Herring ulpi-data0-po1 { /* NC */ 1305*724ba675SRob Herring nvidia,pins = "ulpi_data0_po1"; 1306*724ba675SRob Herring nvidia,function = "ulpi"; 1307*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1308*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1309*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1310*724ba675SRob Herring }; 1311*724ba675SRob Herring ulpi-data1-po2 { /* NC */ 1312*724ba675SRob Herring nvidia,pins = "ulpi_data1_po2"; 1313*724ba675SRob Herring nvidia,function = "ulpi"; 1314*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1315*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1316*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1317*724ba675SRob Herring }; 1318*724ba675SRob Herring ulpi-data2-po3 { /* NC */ 1319*724ba675SRob Herring nvidia,pins = "ulpi_data2_po3"; 1320*724ba675SRob Herring nvidia,function = "ulpi"; 1321*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1322*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1323*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1324*724ba675SRob Herring }; 1325*724ba675SRob Herring ulpi-data3-po4 { /* NC */ 1326*724ba675SRob Herring nvidia,pins = "ulpi_data3_po4"; 1327*724ba675SRob Herring nvidia,function = "ulpi"; 1328*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1329*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1330*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1331*724ba675SRob Herring }; 1332*724ba675SRob Herring ulpi-data6-po7 { /* NC */ 1333*724ba675SRob Herring nvidia,pins = "ulpi_data6_po7"; 1334*724ba675SRob Herring nvidia,function = "ulpi"; 1335*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1336*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1337*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1338*724ba675SRob Herring }; 1339*724ba675SRob Herring dap4-fs-pp4 { /* NC */ 1340*724ba675SRob Herring nvidia,pins = "dap4_fs_pp4"; 1341*724ba675SRob Herring nvidia,function = "rsvd4"; 1342*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1343*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1344*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1345*724ba675SRob Herring }; 1346*724ba675SRob Herring dap4-din-pp5 { /* NC */ 1347*724ba675SRob Herring nvidia,pins = "dap4_din_pp5"; 1348*724ba675SRob Herring nvidia,function = "rsvd3"; 1349*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1350*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1351*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1352*724ba675SRob Herring }; 1353*724ba675SRob Herring dap4-dout-pp6 { /* NC */ 1354*724ba675SRob Herring nvidia,pins = "dap4_dout_pp6"; 1355*724ba675SRob Herring nvidia,function = "rsvd4"; 1356*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1357*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1358*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1359*724ba675SRob Herring }; 1360*724ba675SRob Herring dap4-sclk-pp7 { /* NC */ 1361*724ba675SRob Herring nvidia,pins = "dap4_sclk_pp7"; 1362*724ba675SRob Herring nvidia,function = "rsvd3"; 1363*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1364*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1365*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1366*724ba675SRob Herring }; 1367*724ba675SRob Herring kb-col3-pq3 { /* NC */ 1368*724ba675SRob Herring nvidia,pins = "kb_col3_pq3"; 1369*724ba675SRob Herring nvidia,function = "kbc"; 1370*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1371*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1372*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1373*724ba675SRob Herring }; 1374*724ba675SRob Herring kb-row3-pr3 { /* NC */ 1375*724ba675SRob Herring nvidia,pins = "kb_row3_pr3"; 1376*724ba675SRob Herring nvidia,function = "kbc"; 1377*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1378*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1379*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1380*724ba675SRob Herring }; 1381*724ba675SRob Herring kb-row4-pr4 { /* NC */ 1382*724ba675SRob Herring nvidia,pins = "kb_row4_pr4"; 1383*724ba675SRob Herring nvidia,function = "rsvd3"; 1384*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1385*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1386*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1387*724ba675SRob Herring }; 1388*724ba675SRob Herring kb-row5-pr5 { /* NC */ 1389*724ba675SRob Herring nvidia,pins = "kb_row5_pr5"; 1390*724ba675SRob Herring nvidia,function = "rsvd3"; 1391*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1392*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1393*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1394*724ba675SRob Herring }; 1395*724ba675SRob Herring kb-row6-pr6 { /* NC */ 1396*724ba675SRob Herring nvidia,pins = "kb_row6_pr6"; 1397*724ba675SRob Herring nvidia,function = "kbc"; 1398*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1399*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1400*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1401*724ba675SRob Herring }; 1402*724ba675SRob Herring kb-row7-pr7 { /* NC */ 1403*724ba675SRob Herring nvidia,pins = "kb_row7_pr7"; 1404*724ba675SRob Herring nvidia,function = "rsvd2"; 1405*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1406*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1407*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1408*724ba675SRob Herring }; 1409*724ba675SRob Herring kb-row8-ps0 { /* NC */ 1410*724ba675SRob Herring nvidia,pins = "kb_row8_ps0"; 1411*724ba675SRob Herring nvidia,function = "rsvd2"; 1412*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1413*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1414*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1415*724ba675SRob Herring }; 1416*724ba675SRob Herring kb-row9-ps1 { /* NC */ 1417*724ba675SRob Herring nvidia,pins = "kb_row9_ps1"; 1418*724ba675SRob Herring nvidia,function = "rsvd2"; 1419*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1420*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1421*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1422*724ba675SRob Herring }; 1423*724ba675SRob Herring kb-row12-ps4 { /* NC */ 1424*724ba675SRob Herring nvidia,pins = "kb_row12_ps4"; 1425*724ba675SRob Herring nvidia,function = "rsvd2"; 1426*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1427*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1428*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1429*724ba675SRob Herring }; 1430*724ba675SRob Herring kb-row13-ps5 { /* NC */ 1431*724ba675SRob Herring nvidia,pins = "kb_row13_ps5"; 1432*724ba675SRob Herring nvidia,function = "rsvd2"; 1433*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1434*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1435*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1436*724ba675SRob Herring }; 1437*724ba675SRob Herring kb-row14-ps6 { /* NC */ 1438*724ba675SRob Herring nvidia,pins = "kb_row14_ps6"; 1439*724ba675SRob Herring nvidia,function = "rsvd2"; 1440*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1441*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1442*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1443*724ba675SRob Herring }; 1444*724ba675SRob Herring kb-row15-ps7 { /* NC */ 1445*724ba675SRob Herring nvidia,pins = "kb_row15_ps7"; 1446*724ba675SRob Herring nvidia,function = "rsvd3"; 1447*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1448*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1449*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1450*724ba675SRob Herring }; 1451*724ba675SRob Herring kb-row16-pt0 { /* NC */ 1452*724ba675SRob Herring nvidia,pins = "kb_row16_pt0"; 1453*724ba675SRob Herring nvidia,function = "rsvd2"; 1454*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1455*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1456*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1457*724ba675SRob Herring }; 1458*724ba675SRob Herring kb-row17-pt1 { /* NC */ 1459*724ba675SRob Herring nvidia,pins = "kb_row17_pt1"; 1460*724ba675SRob Herring nvidia,function = "rsvd2"; 1461*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1462*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1463*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1464*724ba675SRob Herring }; 1465*724ba675SRob Herring pu5 { /* NC */ 1466*724ba675SRob Herring nvidia,pins = "pu5"; 1467*724ba675SRob Herring nvidia,function = "gmi"; 1468*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1469*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1470*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1471*724ba675SRob Herring }; 1472*724ba675SRob Herring /* 1473*724ba675SRob Herring * PCB Version Indication: V1.2 and later have GPIO_PV0 1474*724ba675SRob Herring * wired to GND, was NC before 1475*724ba675SRob Herring */ 1476*724ba675SRob Herring pv0 { 1477*724ba675SRob Herring nvidia,pins = "pv0"; 1478*724ba675SRob Herring nvidia,function = "rsvd1"; 1479*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1480*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1481*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1482*724ba675SRob Herring }; 1483*724ba675SRob Herring pv1 { /* NC */ 1484*724ba675SRob Herring nvidia,pins = "pv1"; 1485*724ba675SRob Herring nvidia,function = "rsvd1"; 1486*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1487*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1488*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1489*724ba675SRob Herring }; 1490*724ba675SRob Herring gpio-x1-aud-px1 { /* NC */ 1491*724ba675SRob Herring nvidia,pins = "gpio_x1_aud_px1"; 1492*724ba675SRob Herring nvidia,function = "rsvd2"; 1493*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1494*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1495*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1496*724ba675SRob Herring }; 1497*724ba675SRob Herring gpio-x3-aud-px3 { /* NC */ 1498*724ba675SRob Herring nvidia,pins = "gpio_x3_aud_px3"; 1499*724ba675SRob Herring nvidia,function = "rsvd4"; 1500*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1501*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1502*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1503*724ba675SRob Herring }; 1504*724ba675SRob Herring pbb7 { /* NC */ 1505*724ba675SRob Herring nvidia,pins = "pbb7"; 1506*724ba675SRob Herring nvidia,function = "rsvd2"; 1507*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1508*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1509*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1510*724ba675SRob Herring }; 1511*724ba675SRob Herring pcc1 { /* NC */ 1512*724ba675SRob Herring nvidia,pins = "pcc1"; 1513*724ba675SRob Herring nvidia,function = "rsvd2"; 1514*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1515*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1516*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1517*724ba675SRob Herring }; 1518*724ba675SRob Herring pcc2 { /* NC */ 1519*724ba675SRob Herring nvidia,pins = "pcc2"; 1520*724ba675SRob Herring nvidia,function = "rsvd2"; 1521*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1522*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1523*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1524*724ba675SRob Herring }; 1525*724ba675SRob Herring clk3-req-pee1 { /* NC */ 1526*724ba675SRob Herring nvidia,pins = "clk3_req_pee1"; 1527*724ba675SRob Herring nvidia,function = "rsvd2"; 1528*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1529*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1530*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1531*724ba675SRob Herring }; 1532*724ba675SRob Herring dap-mclk1-req-pee2 { /* NC */ 1533*724ba675SRob Herring nvidia,pins = "dap_mclk1_req_pee2"; 1534*724ba675SRob Herring nvidia,function = "rsvd4"; 1535*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1536*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1537*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1538*724ba675SRob Herring }; 1539*724ba675SRob Herring /* 1540*724ba675SRob Herring * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output 1541*724ba675SRob Herring * driver enabled aka not tristated and input driver 1542*724ba675SRob Herring * enabled as well as it features some magic properties 1543*724ba675SRob Herring * even though the external loopback is disabled and the 1544*724ba675SRob Herring * internal loopback used as per 1545*724ba675SRob Herring * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 1546*724ba675SRob Herring * bits being set to 0xfffd according to the TRM! 1547*724ba675SRob Herring */ 1548*724ba675SRob Herring sdmmc3-clk-lb-out-pee4 { /* NC */ 1549*724ba675SRob Herring nvidia,pins = "sdmmc3_clk_lb_out_pee4"; 1550*724ba675SRob Herring nvidia,function = "sdmmc3"; 1551*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1552*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1553*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1554*724ba675SRob Herring }; 1555*724ba675SRob Herring }; 1556*724ba675SRob Herring }; 1557*724ba675SRob Herring 1558*724ba675SRob Herring serial@70006040 { 1559*724ba675SRob Herring compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; 1560*724ba675SRob Herring /delete-property/ reg-shift; 1561*724ba675SRob Herring }; 1562*724ba675SRob Herring 1563*724ba675SRob Herring serial@70006200 { 1564*724ba675SRob Herring compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; 1565*724ba675SRob Herring /delete-property/ reg-shift; 1566*724ba675SRob Herring }; 1567*724ba675SRob Herring 1568*724ba675SRob Herring serial@70006300 { 1569*724ba675SRob Herring compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; 1570*724ba675SRob Herring /delete-property/ reg-shift; 1571*724ba675SRob Herring }; 1572*724ba675SRob Herring 1573*724ba675SRob Herring hdmi_ddc: i2c@7000c700 { 1574*724ba675SRob Herring clock-frequency = <10000>; 1575*724ba675SRob Herring }; 1576*724ba675SRob Herring 1577*724ba675SRob Herring /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ 1578*724ba675SRob Herring i2c@7000d000 { 1579*724ba675SRob Herring status = "okay"; 1580*724ba675SRob Herring clock-frequency = <400000>; 1581*724ba675SRob Herring 1582*724ba675SRob Herring /* SGTL5000 audio codec */ 1583*724ba675SRob Herring sgtl5000: codec@a { 1584*724ba675SRob Herring compatible = "fsl,sgtl5000"; 1585*724ba675SRob Herring reg = <0x0a>; 1586*724ba675SRob Herring #sound-dai-cells = <0>; 1587*724ba675SRob Herring VDDA-supply = <®_module_3v3_audio>; 1588*724ba675SRob Herring VDDD-supply = <®_1v8_vddio>; 1589*724ba675SRob Herring VDDIO-supply = <®_1v8_vddio>; 1590*724ba675SRob Herring clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; 1591*724ba675SRob Herring }; 1592*724ba675SRob Herring 1593*724ba675SRob Herring pmic: pmic@40 { 1594*724ba675SRob Herring compatible = "ams,as3722"; 1595*724ba675SRob Herring reg = <0x40>; 1596*724ba675SRob Herring interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 1597*724ba675SRob Herring ams,system-power-controller; 1598*724ba675SRob Herring #interrupt-cells = <2>; 1599*724ba675SRob Herring interrupt-controller; 1600*724ba675SRob Herring gpio-controller; 1601*724ba675SRob Herring #gpio-cells = <2>; 1602*724ba675SRob Herring pinctrl-names = "default"; 1603*724ba675SRob Herring pinctrl-0 = <&as3722_default>; 1604*724ba675SRob Herring 1605*724ba675SRob Herring as3722_default: pinmux { 1606*724ba675SRob Herring gpio0-1-3-4-5-6 { 1607*724ba675SRob Herring pins = "gpio0", "gpio1", "gpio3", 1608*724ba675SRob Herring "gpio4", "gpio5", "gpio6"; 1609*724ba675SRob Herring bias-high-impedance; 1610*724ba675SRob Herring }; 1611*724ba675SRob Herring 1612*724ba675SRob Herring gpio2-7 { 1613*724ba675SRob Herring pins = "gpio2", /* PWR_EN_+V3.3 */ 1614*724ba675SRob Herring "gpio7"; /* +V1.6_LPO */ 1615*724ba675SRob Herring function = "gpio"; 1616*724ba675SRob Herring bias-pull-up; 1617*724ba675SRob Herring }; 1618*724ba675SRob Herring }; 1619*724ba675SRob Herring 1620*724ba675SRob Herring regulators { 1621*724ba675SRob Herring vsup-sd2-supply = <®_module_3v3>; 1622*724ba675SRob Herring vsup-sd3-supply = <®_module_3v3>; 1623*724ba675SRob Herring vsup-sd4-supply = <®_module_3v3>; 1624*724ba675SRob Herring vsup-sd5-supply = <®_module_3v3>; 1625*724ba675SRob Herring vin-ldo0-supply = <®_1v35_vddio_ddr>; 1626*724ba675SRob Herring vin-ldo1-6-supply = <®_module_3v3>; 1627*724ba675SRob Herring vin-ldo2-5-7-supply = <®_1v8_vddio>; 1628*724ba675SRob Herring vin-ldo3-4-supply = <®_module_3v3>; 1629*724ba675SRob Herring vin-ldo9-10-supply = <®_module_3v3>; 1630*724ba675SRob Herring vin-ldo11-supply = <®_module_3v3>; 1631*724ba675SRob Herring 1632*724ba675SRob Herring reg_vdd_cpu: sd0 { 1633*724ba675SRob Herring regulator-name = "+VDD_CPU_AP"; 1634*724ba675SRob Herring regulator-min-microvolt = <700000>; 1635*724ba675SRob Herring regulator-max-microvolt = <1400000>; 1636*724ba675SRob Herring regulator-min-microamp = <3500000>; 1637*724ba675SRob Herring regulator-max-microamp = <3500000>; 1638*724ba675SRob Herring regulator-always-on; 1639*724ba675SRob Herring regulator-boot-on; 1640*724ba675SRob Herring ams,ext-control = <2>; 1641*724ba675SRob Herring }; 1642*724ba675SRob Herring 1643*724ba675SRob Herring sd1 { 1644*724ba675SRob Herring regulator-name = "+VDD_CORE"; 1645*724ba675SRob Herring regulator-min-microvolt = <700000>; 1646*724ba675SRob Herring regulator-max-microvolt = <1350000>; 1647*724ba675SRob Herring regulator-min-microamp = <2500000>; 1648*724ba675SRob Herring regulator-max-microamp = <4000000>; 1649*724ba675SRob Herring regulator-always-on; 1650*724ba675SRob Herring regulator-boot-on; 1651*724ba675SRob Herring ams,ext-control = <1>; 1652*724ba675SRob Herring }; 1653*724ba675SRob Herring 1654*724ba675SRob Herring reg_1v35_vddio_ddr: sd2 { 1655*724ba675SRob Herring regulator-name = 1656*724ba675SRob Herring "+V1.35_VDDIO_DDR(sd2)"; 1657*724ba675SRob Herring regulator-min-microvolt = <1350000>; 1658*724ba675SRob Herring regulator-max-microvolt = <1350000>; 1659*724ba675SRob Herring regulator-always-on; 1660*724ba675SRob Herring regulator-boot-on; 1661*724ba675SRob Herring }; 1662*724ba675SRob Herring 1663*724ba675SRob Herring sd3 { 1664*724ba675SRob Herring regulator-name = 1665*724ba675SRob Herring "+V1.35_VDDIO_DDR(sd3)"; 1666*724ba675SRob Herring regulator-min-microvolt = <1350000>; 1667*724ba675SRob Herring regulator-max-microvolt = <1350000>; 1668*724ba675SRob Herring regulator-always-on; 1669*724ba675SRob Herring regulator-boot-on; 1670*724ba675SRob Herring }; 1671*724ba675SRob Herring 1672*724ba675SRob Herring reg_1v05_vdd: sd4 { 1673*724ba675SRob Herring regulator-name = "+V1.05"; 1674*724ba675SRob Herring regulator-min-microvolt = <1050000>; 1675*724ba675SRob Herring regulator-max-microvolt = <1050000>; 1676*724ba675SRob Herring }; 1677*724ba675SRob Herring 1678*724ba675SRob Herring reg_1v8_vddio: sd5 { 1679*724ba675SRob Herring regulator-name = "+V1.8"; 1680*724ba675SRob Herring regulator-min-microvolt = <1800000>; 1681*724ba675SRob Herring regulator-max-microvolt = <1800000>; 1682*724ba675SRob Herring regulator-boot-on; 1683*724ba675SRob Herring regulator-always-on; 1684*724ba675SRob Herring }; 1685*724ba675SRob Herring 1686*724ba675SRob Herring reg_vdd_gpu: sd6 { 1687*724ba675SRob Herring regulator-name = "+VDD_GPU_AP"; 1688*724ba675SRob Herring regulator-min-microvolt = <650000>; 1689*724ba675SRob Herring regulator-max-microvolt = <1200000>; 1690*724ba675SRob Herring regulator-min-microamp = <3500000>; 1691*724ba675SRob Herring regulator-max-microamp = <3500000>; 1692*724ba675SRob Herring regulator-boot-on; 1693*724ba675SRob Herring regulator-always-on; 1694*724ba675SRob Herring }; 1695*724ba675SRob Herring 1696*724ba675SRob Herring reg_1v05_avdd: ldo0 { 1697*724ba675SRob Herring regulator-name = "+V1.05_AVDD"; 1698*724ba675SRob Herring regulator-min-microvolt = <1050000>; 1699*724ba675SRob Herring regulator-max-microvolt = <1050000>; 1700*724ba675SRob Herring regulator-boot-on; 1701*724ba675SRob Herring regulator-always-on; 1702*724ba675SRob Herring ams,ext-control = <1>; 1703*724ba675SRob Herring }; 1704*724ba675SRob Herring 1705*724ba675SRob Herring vddio_sdmmc1: ldo1 { 1706*724ba675SRob Herring regulator-name = "VDDIO_SDMMC1"; 1707*724ba675SRob Herring regulator-min-microvolt = <1800000>; 1708*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1709*724ba675SRob Herring }; 1710*724ba675SRob Herring 1711*724ba675SRob Herring ldo2 { 1712*724ba675SRob Herring regulator-name = "+V1.2"; 1713*724ba675SRob Herring regulator-min-microvolt = <1200000>; 1714*724ba675SRob Herring regulator-max-microvolt = <1200000>; 1715*724ba675SRob Herring regulator-boot-on; 1716*724ba675SRob Herring regulator-always-on; 1717*724ba675SRob Herring }; 1718*724ba675SRob Herring 1719*724ba675SRob Herring ldo3 { 1720*724ba675SRob Herring regulator-name = "+V1.05_RTC"; 1721*724ba675SRob Herring regulator-min-microvolt = <1000000>; 1722*724ba675SRob Herring regulator-max-microvolt = <1000000>; 1723*724ba675SRob Herring regulator-boot-on; 1724*724ba675SRob Herring regulator-always-on; 1725*724ba675SRob Herring ams,enable-tracking; 1726*724ba675SRob Herring }; 1727*724ba675SRob Herring 1728*724ba675SRob Herring /* 1.8V for LVDS, 3.3V for eDP */ 1729*724ba675SRob Herring ldo4 { 1730*724ba675SRob Herring regulator-name = "AVDD_LVDS0_PLL"; 1731*724ba675SRob Herring regulator-min-microvolt = <1800000>; 1732*724ba675SRob Herring regulator-max-microvolt = <1800000>; 1733*724ba675SRob Herring }; 1734*724ba675SRob Herring 1735*724ba675SRob Herring /* LDO5 not used */ 1736*724ba675SRob Herring 1737*724ba675SRob Herring vddio_sdmmc3: ldo6 { 1738*724ba675SRob Herring regulator-name = "VDDIO_SDMMC3"; 1739*724ba675SRob Herring regulator-min-microvolt = <1800000>; 1740*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1741*724ba675SRob Herring }; 1742*724ba675SRob Herring 1743*724ba675SRob Herring /* LDO7 not used */ 1744*724ba675SRob Herring 1745*724ba675SRob Herring ldo9 { 1746*724ba675SRob Herring regulator-name = "+V3.3_ETH(ldo9)"; 1747*724ba675SRob Herring regulator-min-microvolt = <3300000>; 1748*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1749*724ba675SRob Herring regulator-always-on; 1750*724ba675SRob Herring }; 1751*724ba675SRob Herring 1752*724ba675SRob Herring ldo10 { 1753*724ba675SRob Herring regulator-name = "+V3.3_ETH(ldo10)"; 1754*724ba675SRob Herring regulator-min-microvolt = <3300000>; 1755*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1756*724ba675SRob Herring regulator-always-on; 1757*724ba675SRob Herring }; 1758*724ba675SRob Herring 1759*724ba675SRob Herring ldo11 { 1760*724ba675SRob Herring regulator-name = "+V1.8_VPP_FUSE"; 1761*724ba675SRob Herring regulator-min-microvolt = <1800000>; 1762*724ba675SRob Herring regulator-max-microvolt = <1800000>; 1763*724ba675SRob Herring }; 1764*724ba675SRob Herring }; 1765*724ba675SRob Herring }; 1766*724ba675SRob Herring 1767*724ba675SRob Herring /* 1768*724ba675SRob Herring * TMP451 temperature sensor 1769*724ba675SRob Herring * Note: THERM_N directly connected to AS3722 PMIC THERM 1770*724ba675SRob Herring */ 1771*724ba675SRob Herring temp-sensor@4c { 1772*724ba675SRob Herring compatible = "ti,tmp451"; 1773*724ba675SRob Herring reg = <0x4c>; 1774*724ba675SRob Herring interrupt-parent = <&gpio>; 1775*724ba675SRob Herring interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_EDGE_FALLING>; 1776*724ba675SRob Herring #thermal-sensor-cells = <1>; 1777*724ba675SRob Herring vcc-supply = <®_module_3v3>; 1778*724ba675SRob Herring }; 1779*724ba675SRob Herring }; 1780*724ba675SRob Herring 1781*724ba675SRob Herring /* SPI2: MCU SPI */ 1782*724ba675SRob Herring spi@7000d600 { 1783*724ba675SRob Herring status = "okay"; 1784*724ba675SRob Herring spi-max-frequency = <25000000>; 1785*724ba675SRob Herring }; 1786*724ba675SRob Herring 1787*724ba675SRob Herring pmc@7000e400 { 1788*724ba675SRob Herring nvidia,invert-interrupt; 1789*724ba675SRob Herring nvidia,suspend-mode = <1>; 1790*724ba675SRob Herring nvidia,cpu-pwr-good-time = <500>; 1791*724ba675SRob Herring nvidia,cpu-pwr-off-time = <300>; 1792*724ba675SRob Herring nvidia,core-pwr-good-time = <641 3845>; 1793*724ba675SRob Herring nvidia,core-pwr-off-time = <61036>; 1794*724ba675SRob Herring nvidia,core-power-req-active-high; 1795*724ba675SRob Herring nvidia,sys-clock-req-active-high; 1796*724ba675SRob Herring 1797*724ba675SRob Herring /* Set power_off bit in ResetControl register of AS3722 PMIC */ 1798*724ba675SRob Herring i2c-thermtrip { 1799*724ba675SRob Herring nvidia,i2c-controller-id = <4>; 1800*724ba675SRob Herring nvidia,bus-addr = <0x40>; 1801*724ba675SRob Herring nvidia,reg-addr = <0x36>; 1802*724ba675SRob Herring nvidia,reg-data = <0x2>; 1803*724ba675SRob Herring }; 1804*724ba675SRob Herring }; 1805*724ba675SRob Herring 1806*724ba675SRob Herring sata@70020000 { 1807*724ba675SRob Herring phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; 1808*724ba675SRob Herring phy-names = "sata-0"; 1809*724ba675SRob Herring avdd-supply = <®_1v05_vdd>; 1810*724ba675SRob Herring hvdd-supply = <®_module_3v3>; 1811*724ba675SRob Herring vddio-supply = <®_1v05_vdd>; 1812*724ba675SRob Herring }; 1813*724ba675SRob Herring 1814*724ba675SRob Herring usb@70090000 { 1815*724ba675SRob Herring /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */ 1816*724ba675SRob Herring phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, 1817*724ba675SRob Herring <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, 1818*724ba675SRob Herring <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, 1819*724ba675SRob Herring <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, 1820*724ba675SRob Herring <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; 1821*724ba675SRob Herring phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; 1822*724ba675SRob Herring 1823*724ba675SRob Herring avddio-pex-supply = <®_1v05_vdd>; 1824*724ba675SRob Herring avdd-pll-erefe-supply = <®_1v05_avdd>; 1825*724ba675SRob Herring avdd-pll-utmip-supply = <®_1v8_vddio>; 1826*724ba675SRob Herring avdd-usb-ss-pll-supply = <®_1v05_vdd>; 1827*724ba675SRob Herring avdd-usb-supply = <®_module_3v3>; 1828*724ba675SRob Herring dvddio-pex-supply = <®_1v05_vdd>; 1829*724ba675SRob Herring hvdd-usb-ss-pll-e-supply = <®_module_3v3>; 1830*724ba675SRob Herring hvdd-usb-ss-supply = <®_module_3v3>; 1831*724ba675SRob Herring }; 1832*724ba675SRob Herring 1833*724ba675SRob Herring padctl@7009f000 { 1834*724ba675SRob Herring avdd-pll-utmip-supply = <®_1v8_vddio>; 1835*724ba675SRob Herring avdd-pll-erefe-supply = <®_1v05_avdd>; 1836*724ba675SRob Herring avdd-pex-pll-supply = <®_1v05_vdd>; 1837*724ba675SRob Herring hvdd-pex-pll-e-supply = <®_module_3v3>; 1838*724ba675SRob Herring 1839*724ba675SRob Herring pads { 1840*724ba675SRob Herring usb2 { 1841*724ba675SRob Herring status = "okay"; 1842*724ba675SRob Herring 1843*724ba675SRob Herring lanes { 1844*724ba675SRob Herring usb2-0 { 1845*724ba675SRob Herring status = "okay"; 1846*724ba675SRob Herring nvidia,function = "xusb"; 1847*724ba675SRob Herring }; 1848*724ba675SRob Herring 1849*724ba675SRob Herring usb2-1 { 1850*724ba675SRob Herring status = "okay"; 1851*724ba675SRob Herring nvidia,function = "xusb"; 1852*724ba675SRob Herring }; 1853*724ba675SRob Herring 1854*724ba675SRob Herring usb2-2 { 1855*724ba675SRob Herring status = "okay"; 1856*724ba675SRob Herring nvidia,function = "xusb"; 1857*724ba675SRob Herring }; 1858*724ba675SRob Herring }; 1859*724ba675SRob Herring }; 1860*724ba675SRob Herring 1861*724ba675SRob Herring pcie { 1862*724ba675SRob Herring status = "okay"; 1863*724ba675SRob Herring 1864*724ba675SRob Herring lanes { 1865*724ba675SRob Herring pcie-0 { 1866*724ba675SRob Herring status = "okay"; 1867*724ba675SRob Herring nvidia,function = "usb3-ss"; 1868*724ba675SRob Herring }; 1869*724ba675SRob Herring 1870*724ba675SRob Herring pcie-1 { 1871*724ba675SRob Herring status = "okay"; 1872*724ba675SRob Herring nvidia,function = "usb3-ss"; 1873*724ba675SRob Herring }; 1874*724ba675SRob Herring 1875*724ba675SRob Herring pcie-2 { 1876*724ba675SRob Herring status = "okay"; 1877*724ba675SRob Herring nvidia,function = "pcie"; 1878*724ba675SRob Herring }; 1879*724ba675SRob Herring 1880*724ba675SRob Herring pcie-3 { 1881*724ba675SRob Herring status = "okay"; 1882*724ba675SRob Herring nvidia,function = "pcie"; 1883*724ba675SRob Herring }; 1884*724ba675SRob Herring 1885*724ba675SRob Herring pcie-4 { 1886*724ba675SRob Herring status = "okay"; 1887*724ba675SRob Herring nvidia,function = "pcie"; 1888*724ba675SRob Herring }; 1889*724ba675SRob Herring }; 1890*724ba675SRob Herring }; 1891*724ba675SRob Herring 1892*724ba675SRob Herring sata { 1893*724ba675SRob Herring status = "okay"; 1894*724ba675SRob Herring 1895*724ba675SRob Herring lanes { 1896*724ba675SRob Herring sata-0 { 1897*724ba675SRob Herring status = "okay"; 1898*724ba675SRob Herring nvidia,function = "sata"; 1899*724ba675SRob Herring }; 1900*724ba675SRob Herring }; 1901*724ba675SRob Herring }; 1902*724ba675SRob Herring }; 1903*724ba675SRob Herring 1904*724ba675SRob Herring ports { 1905*724ba675SRob Herring /* USBO1 */ 1906*724ba675SRob Herring usb2-0 { 1907*724ba675SRob Herring status = "okay"; 1908*724ba675SRob Herring mode = "otg"; 1909*724ba675SRob Herring usb-role-switch; 1910*724ba675SRob Herring vbus-supply = <®_usbo1_vbus>; 1911*724ba675SRob Herring }; 1912*724ba675SRob Herring 1913*724ba675SRob Herring /* USBH2 */ 1914*724ba675SRob Herring usb2-1 { 1915*724ba675SRob Herring status = "okay"; 1916*724ba675SRob Herring mode = "host"; 1917*724ba675SRob Herring vbus-supply = <®_usbh_vbus>; 1918*724ba675SRob Herring }; 1919*724ba675SRob Herring 1920*724ba675SRob Herring /* USBH4 */ 1921*724ba675SRob Herring usb2-2 { 1922*724ba675SRob Herring status = "okay"; 1923*724ba675SRob Herring mode = "host"; 1924*724ba675SRob Herring vbus-supply = <®_usbh_vbus>; 1925*724ba675SRob Herring }; 1926*724ba675SRob Herring 1927*724ba675SRob Herring usb3-0 { 1928*724ba675SRob Herring status = "okay"; 1929*724ba675SRob Herring nvidia,usb2-companion = <2>; 1930*724ba675SRob Herring vbus-supply = <®_usbh_vbus>; 1931*724ba675SRob Herring }; 1932*724ba675SRob Herring 1933*724ba675SRob Herring usb3-1 { 1934*724ba675SRob Herring status = "okay"; 1935*724ba675SRob Herring nvidia,usb2-companion = <0>; 1936*724ba675SRob Herring vbus-supply = <®_usbo1_vbus>; 1937*724ba675SRob Herring }; 1938*724ba675SRob Herring }; 1939*724ba675SRob Herring }; 1940*724ba675SRob Herring 1941*724ba675SRob Herring /* eMMC */ 1942*724ba675SRob Herring mmc@700b0600 { 1943*724ba675SRob Herring status = "okay"; 1944*724ba675SRob Herring bus-width = <8>; 1945*724ba675SRob Herring non-removable; 1946*724ba675SRob Herring vmmc-supply = <®_module_3v3>; /* VCC */ 1947*724ba675SRob Herring vqmmc-supply = <®_1v8_vddio>; /* VCCQ */ 1948*724ba675SRob Herring mmc-ddr-1_8v; 1949*724ba675SRob Herring }; 1950*724ba675SRob Herring 1951*724ba675SRob Herring /* CPU DFLL clock */ 1952*724ba675SRob Herring clock@70110000 { 1953*724ba675SRob Herring status = "okay"; 1954*724ba675SRob Herring nvidia,i2c-fs-rate = <400000>; 1955*724ba675SRob Herring vdd-cpu-supply = <®_vdd_cpu>; 1956*724ba675SRob Herring }; 1957*724ba675SRob Herring 1958*724ba675SRob Herring ahub@70300000 { 1959*724ba675SRob Herring i2s@70301200 { 1960*724ba675SRob Herring status = "okay"; 1961*724ba675SRob Herring }; 1962*724ba675SRob Herring }; 1963*724ba675SRob Herring 1964*724ba675SRob Herring cpus { 1965*724ba675SRob Herring cpu@0 { 1966*724ba675SRob Herring vdd-cpu-supply = <®_vdd_cpu>; 1967*724ba675SRob Herring }; 1968*724ba675SRob Herring }; 1969*724ba675SRob Herring 1970*724ba675SRob Herring clk32k_in: osc3 { 1971*724ba675SRob Herring compatible = "fixed-clock"; 1972*724ba675SRob Herring #clock-cells = <0>; 1973*724ba675SRob Herring clock-frequency = <32768>; 1974*724ba675SRob Herring }; 1975*724ba675SRob Herring 1976*724ba675SRob Herring reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { 1977*724ba675SRob Herring compatible = "regulator-fixed"; 1978*724ba675SRob Herring regulator-name = "+V1.05_AVDD_HDMI_PLL"; 1979*724ba675SRob Herring regulator-min-microvolt = <1050000>; 1980*724ba675SRob Herring regulator-max-microvolt = <1050000>; 1981*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; 1982*724ba675SRob Herring vin-supply = <®_1v05_vdd>; 1983*724ba675SRob Herring }; 1984*724ba675SRob Herring 1985*724ba675SRob Herring reg_3v3_mxm: regulator-3v3-mxm { 1986*724ba675SRob Herring compatible = "regulator-fixed"; 1987*724ba675SRob Herring regulator-name = "+V3.3_MXM"; 1988*724ba675SRob Herring regulator-min-microvolt = <3300000>; 1989*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1990*724ba675SRob Herring regulator-always-on; 1991*724ba675SRob Herring regulator-boot-on; 1992*724ba675SRob Herring }; 1993*724ba675SRob Herring 1994*724ba675SRob Herring reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { 1995*724ba675SRob Herring compatible = "regulator-fixed"; 1996*724ba675SRob Herring regulator-name = "+V3.3_AVDD_HDMI"; 1997*724ba675SRob Herring regulator-min-microvolt = <3300000>; 1998*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1999*724ba675SRob Herring vin-supply = <®_1v05_vdd>; 2000*724ba675SRob Herring }; 2001*724ba675SRob Herring 2002*724ba675SRob Herring reg_module_3v3: regulator-module-3v3 { 2003*724ba675SRob Herring compatible = "regulator-fixed"; 2004*724ba675SRob Herring regulator-name = "+V3.3"; 2005*724ba675SRob Herring regulator-min-microvolt = <3300000>; 2006*724ba675SRob Herring regulator-max-microvolt = <3300000>; 2007*724ba675SRob Herring regulator-always-on; 2008*724ba675SRob Herring regulator-boot-on; 2009*724ba675SRob Herring /* PWR_EN_+V3.3 */ 2010*724ba675SRob Herring gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; 2011*724ba675SRob Herring enable-active-high; 2012*724ba675SRob Herring vin-supply = <®_3v3_mxm>; 2013*724ba675SRob Herring }; 2014*724ba675SRob Herring 2015*724ba675SRob Herring reg_module_3v3_audio: regulator-module-3v3-audio { 2016*724ba675SRob Herring compatible = "regulator-fixed"; 2017*724ba675SRob Herring regulator-name = "+V3.3_AUDIO_AVDD_S"; 2018*724ba675SRob Herring regulator-min-microvolt = <3300000>; 2019*724ba675SRob Herring regulator-max-microvolt = <3300000>; 2020*724ba675SRob Herring regulator-always-on; 2021*724ba675SRob Herring }; 2022*724ba675SRob Herring 2023*724ba675SRob Herring sound { 2024*724ba675SRob Herring compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", 2025*724ba675SRob Herring "nvidia,tegra-audio-sgtl5000"; 2026*724ba675SRob Herring nvidia,model = "Toradex Apalis TK1"; 2027*724ba675SRob Herring nvidia,audio-routing = 2028*724ba675SRob Herring "Headphone Jack", "HP_OUT", 2029*724ba675SRob Herring "LINE_IN", "Line In Jack", 2030*724ba675SRob Herring "MIC_IN", "Mic Jack"; 2031*724ba675SRob Herring nvidia,i2s-controller = <&tegra_i2s2>; 2032*724ba675SRob Herring nvidia,audio-codec = <&sgtl5000>; 2033*724ba675SRob Herring clocks = <&tegra_car TEGRA124_CLK_PLL_A>, 2034*724ba675SRob Herring <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, 2035*724ba675SRob Herring <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 2036*724ba675SRob Herring clock-names = "pll_a", "pll_a_out0", "mclk"; 2037*724ba675SRob Herring 2038*724ba675SRob Herring assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, 2039*724ba675SRob Herring <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 2040*724ba675SRob Herring 2041*724ba675SRob Herring assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, 2042*724ba675SRob Herring <&tegra_car TEGRA124_CLK_EXTERN1>; 2043*724ba675SRob Herring }; 2044*724ba675SRob Herring 2045*724ba675SRob Herring thermal-zones { 2046*724ba675SRob Herring cpu-thermal { 2047*724ba675SRob Herring trips { 2048*724ba675SRob Herring cpu-shutdown-trip { 2049*724ba675SRob Herring temperature = <101000>; 2050*724ba675SRob Herring hysteresis = <0>; 2051*724ba675SRob Herring type = "critical"; 2052*724ba675SRob Herring }; 2053*724ba675SRob Herring }; 2054*724ba675SRob Herring }; 2055*724ba675SRob Herring 2056*724ba675SRob Herring mem-thermal { 2057*724ba675SRob Herring trips { 2058*724ba675SRob Herring mem-shutdown-trip { 2059*724ba675SRob Herring temperature = <101000>; 2060*724ba675SRob Herring hysteresis = <0>; 2061*724ba675SRob Herring type = "critical"; 2062*724ba675SRob Herring }; 2063*724ba675SRob Herring }; 2064*724ba675SRob Herring }; 2065*724ba675SRob Herring 2066*724ba675SRob Herring gpu-thermal { 2067*724ba675SRob Herring trips { 2068*724ba675SRob Herring gpu-shutdown-trip { 2069*724ba675SRob Herring temperature = <101000>; 2070*724ba675SRob Herring hysteresis = <0>; 2071*724ba675SRob Herring type = "critical"; 2072*724ba675SRob Herring }; 2073*724ba675SRob Herring }; 2074*724ba675SRob Herring }; 2075*724ba675SRob Herring }; 2076*724ba675SRob Herring}; 2077