1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring#include <dt-bindings/clock/tegra114-car.h> 3*724ba675SRob Herring#include <dt-bindings/gpio/tegra-gpio.h> 4*724ba675SRob Herring#include <dt-bindings/memory/tegra114-mc.h> 5*724ba675SRob Herring#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 7*724ba675SRob Herring#include <dt-bindings/soc/tegra-pmc.h> 8*724ba675SRob Herring 9*724ba675SRob Herring/ { 10*724ba675SRob Herring compatible = "nvidia,tegra114"; 11*724ba675SRob Herring interrupt-parent = <&lic>; 12*724ba675SRob Herring #address-cells = <1>; 13*724ba675SRob Herring #size-cells = <1>; 14*724ba675SRob Herring 15*724ba675SRob Herring memory@80000000 { 16*724ba675SRob Herring device_type = "memory"; 17*724ba675SRob Herring reg = <0x80000000 0x0>; 18*724ba675SRob Herring }; 19*724ba675SRob Herring 20*724ba675SRob Herring sram@40000000 { 21*724ba675SRob Herring compatible = "mmio-sram"; 22*724ba675SRob Herring reg = <0x40000000 0x40000>; 23*724ba675SRob Herring #address-cells = <1>; 24*724ba675SRob Herring #size-cells = <1>; 25*724ba675SRob Herring ranges = <0 0x40000000 0x40000>; 26*724ba675SRob Herring 27*724ba675SRob Herring vde_pool: sram@400 { 28*724ba675SRob Herring reg = <0x400 0x3fc00>; 29*724ba675SRob Herring pool; 30*724ba675SRob Herring }; 31*724ba675SRob Herring }; 32*724ba675SRob Herring 33*724ba675SRob Herring host1x@50000000 { 34*724ba675SRob Herring compatible = "nvidia,tegra114-host1x"; 35*724ba675SRob Herring reg = <0x50000000 0x00028000>; 36*724ba675SRob Herring interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 37*724ba675SRob Herring <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 38*724ba675SRob Herring interrupt-names = "syncpt", "host1x"; 39*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_HOST1X>; 40*724ba675SRob Herring clock-names = "host1x"; 41*724ba675SRob Herring resets = <&tegra_car 28>, <&mc TEGRA114_MC_RESET_HC>; 42*724ba675SRob Herring reset-names = "host1x", "mc"; 43*724ba675SRob Herring iommus = <&mc TEGRA_SWGROUP_HC>; 44*724ba675SRob Herring 45*724ba675SRob Herring #address-cells = <1>; 46*724ba675SRob Herring #size-cells = <1>; 47*724ba675SRob Herring 48*724ba675SRob Herring ranges = <0x54000000 0x54000000 0x01000000>; 49*724ba675SRob Herring 50*724ba675SRob Herring gr2d@54140000 { 51*724ba675SRob Herring compatible = "nvidia,tegra114-gr2d"; 52*724ba675SRob Herring reg = <0x54140000 0x00040000>; 53*724ba675SRob Herring interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 54*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_GR2D>; 55*724ba675SRob Herring resets = <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>; 56*724ba675SRob Herring reset-names = "2d", "mc"; 57*724ba675SRob Herring 58*724ba675SRob Herring iommus = <&mc TEGRA_SWGROUP_G2>; 59*724ba675SRob Herring }; 60*724ba675SRob Herring 61*724ba675SRob Herring gr3d@54180000 { 62*724ba675SRob Herring compatible = "nvidia,tegra114-gr3d"; 63*724ba675SRob Herring reg = <0x54180000 0x00040000>; 64*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_GR3D>; 65*724ba675SRob Herring resets = <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>; 66*724ba675SRob Herring reset-names = "3d", "mc"; 67*724ba675SRob Herring 68*724ba675SRob Herring iommus = <&mc TEGRA_SWGROUP_NV>; 69*724ba675SRob Herring }; 70*724ba675SRob Herring 71*724ba675SRob Herring dc@54200000 { 72*724ba675SRob Herring compatible = "nvidia,tegra114-dc"; 73*724ba675SRob Herring reg = <0x54200000 0x00040000>; 74*724ba675SRob Herring interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 75*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_DISP1>, 76*724ba675SRob Herring <&tegra_car TEGRA114_CLK_PLL_P>; 77*724ba675SRob Herring clock-names = "dc", "parent"; 78*724ba675SRob Herring resets = <&tegra_car 27>; 79*724ba675SRob Herring reset-names = "dc"; 80*724ba675SRob Herring 81*724ba675SRob Herring iommus = <&mc TEGRA_SWGROUP_DC>; 82*724ba675SRob Herring 83*724ba675SRob Herring nvidia,head = <0>; 84*724ba675SRob Herring 85*724ba675SRob Herring rgb { 86*724ba675SRob Herring status = "disabled"; 87*724ba675SRob Herring }; 88*724ba675SRob Herring }; 89*724ba675SRob Herring 90*724ba675SRob Herring dc@54240000 { 91*724ba675SRob Herring compatible = "nvidia,tegra114-dc"; 92*724ba675SRob Herring reg = <0x54240000 0x00040000>; 93*724ba675SRob Herring interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 94*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_DISP2>, 95*724ba675SRob Herring <&tegra_car TEGRA114_CLK_PLL_P>; 96*724ba675SRob Herring clock-names = "dc", "parent"; 97*724ba675SRob Herring resets = <&tegra_car 26>; 98*724ba675SRob Herring reset-names = "dc"; 99*724ba675SRob Herring 100*724ba675SRob Herring iommus = <&mc TEGRA_SWGROUP_DCB>; 101*724ba675SRob Herring 102*724ba675SRob Herring nvidia,head = <1>; 103*724ba675SRob Herring 104*724ba675SRob Herring rgb { 105*724ba675SRob Herring status = "disabled"; 106*724ba675SRob Herring }; 107*724ba675SRob Herring }; 108*724ba675SRob Herring 109*724ba675SRob Herring hdmi@54280000 { 110*724ba675SRob Herring compatible = "nvidia,tegra114-hdmi"; 111*724ba675SRob Herring reg = <0x54280000 0x00040000>; 112*724ba675SRob Herring interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 113*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_HDMI>, 114*724ba675SRob Herring <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; 115*724ba675SRob Herring clock-names = "hdmi", "parent"; 116*724ba675SRob Herring resets = <&tegra_car 51>; 117*724ba675SRob Herring reset-names = "hdmi"; 118*724ba675SRob Herring status = "disabled"; 119*724ba675SRob Herring }; 120*724ba675SRob Herring 121*724ba675SRob Herring dsia: dsi@54300000 { 122*724ba675SRob Herring compatible = "nvidia,tegra114-dsi"; 123*724ba675SRob Herring reg = <0x54300000 0x00040000>; 124*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_DSIA>, 125*724ba675SRob Herring <&tegra_car TEGRA114_CLK_DSIALP>, 126*724ba675SRob Herring <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; 127*724ba675SRob Herring clock-names = "dsi", "lp", "parent"; 128*724ba675SRob Herring resets = <&tegra_car 48>; 129*724ba675SRob Herring reset-names = "dsi"; 130*724ba675SRob Herring nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ 131*724ba675SRob Herring status = "disabled"; 132*724ba675SRob Herring 133*724ba675SRob Herring #address-cells = <1>; 134*724ba675SRob Herring #size-cells = <0>; 135*724ba675SRob Herring }; 136*724ba675SRob Herring 137*724ba675SRob Herring dsib: dsi@54400000 { 138*724ba675SRob Herring compatible = "nvidia,tegra114-dsi"; 139*724ba675SRob Herring reg = <0x54400000 0x00040000>; 140*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_DSIB>, 141*724ba675SRob Herring <&tegra_car TEGRA114_CLK_DSIBLP>, 142*724ba675SRob Herring <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; 143*724ba675SRob Herring clock-names = "dsi", "lp", "parent"; 144*724ba675SRob Herring resets = <&tegra_car 82>; 145*724ba675SRob Herring reset-names = "dsi"; 146*724ba675SRob Herring nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ 147*724ba675SRob Herring status = "disabled"; 148*724ba675SRob Herring 149*724ba675SRob Herring #address-cells = <1>; 150*724ba675SRob Herring #size-cells = <0>; 151*724ba675SRob Herring }; 152*724ba675SRob Herring }; 153*724ba675SRob Herring 154*724ba675SRob Herring gic: interrupt-controller@50041000 { 155*724ba675SRob Herring compatible = "arm,cortex-a15-gic"; 156*724ba675SRob Herring #interrupt-cells = <3>; 157*724ba675SRob Herring interrupt-controller; 158*724ba675SRob Herring reg = <0x50041000 0x1000>, 159*724ba675SRob Herring <0x50042000 0x1000>, 160*724ba675SRob Herring <0x50044000 0x2000>, 161*724ba675SRob Herring <0x50046000 0x2000>; 162*724ba675SRob Herring interrupts = <GIC_PPI 9 163*724ba675SRob Herring (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 164*724ba675SRob Herring interrupt-parent = <&gic>; 165*724ba675SRob Herring }; 166*724ba675SRob Herring 167*724ba675SRob Herring lic: interrupt-controller@60004000 { 168*724ba675SRob Herring compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr"; 169*724ba675SRob Herring reg = <0x60004000 0x100>, 170*724ba675SRob Herring <0x60004100 0x50>, 171*724ba675SRob Herring <0x60004200 0x50>, 172*724ba675SRob Herring <0x60004300 0x50>, 173*724ba675SRob Herring <0x60004400 0x50>; 174*724ba675SRob Herring interrupt-controller; 175*724ba675SRob Herring #interrupt-cells = <3>; 176*724ba675SRob Herring interrupt-parent = <&gic>; 177*724ba675SRob Herring }; 178*724ba675SRob Herring 179*724ba675SRob Herring timer@60005000 { 180*724ba675SRob Herring compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer"; 181*724ba675SRob Herring reg = <0x60005000 0x400>; 182*724ba675SRob Herring interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 183*724ba675SRob Herring <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 184*724ba675SRob Herring <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 185*724ba675SRob Herring <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 186*724ba675SRob Herring <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 187*724ba675SRob Herring <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 188*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_TIMER>; 189*724ba675SRob Herring }; 190*724ba675SRob Herring 191*724ba675SRob Herring tegra_car: clock@60006000 { 192*724ba675SRob Herring compatible = "nvidia,tegra114-car"; 193*724ba675SRob Herring reg = <0x60006000 0x1000>; 194*724ba675SRob Herring #clock-cells = <1>; 195*724ba675SRob Herring #reset-cells = <1>; 196*724ba675SRob Herring }; 197*724ba675SRob Herring 198*724ba675SRob Herring flow-controller@60007000 { 199*724ba675SRob Herring compatible = "nvidia,tegra114-flowctrl"; 200*724ba675SRob Herring reg = <0x60007000 0x1000>; 201*724ba675SRob Herring }; 202*724ba675SRob Herring 203*724ba675SRob Herring apbdma: dma@6000a000 { 204*724ba675SRob Herring compatible = "nvidia,tegra114-apbdma"; 205*724ba675SRob Herring reg = <0x6000a000 0x1400>; 206*724ba675SRob Herring interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 207*724ba675SRob Herring <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 208*724ba675SRob Herring <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 209*724ba675SRob Herring <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 210*724ba675SRob Herring <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 211*724ba675SRob Herring <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 212*724ba675SRob Herring <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 213*724ba675SRob Herring <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 214*724ba675SRob Herring <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 215*724ba675SRob Herring <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 216*724ba675SRob Herring <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 217*724ba675SRob Herring <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 218*724ba675SRob Herring <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 219*724ba675SRob Herring <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 220*724ba675SRob Herring <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 221*724ba675SRob Herring <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 222*724ba675SRob Herring <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 223*724ba675SRob Herring <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 224*724ba675SRob Herring <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 225*724ba675SRob Herring <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 226*724ba675SRob Herring <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 227*724ba675SRob Herring <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 228*724ba675SRob Herring <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 229*724ba675SRob Herring <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 230*724ba675SRob Herring <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 231*724ba675SRob Herring <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 232*724ba675SRob Herring <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 233*724ba675SRob Herring <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 234*724ba675SRob Herring <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 235*724ba675SRob Herring <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 236*724ba675SRob Herring <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 237*724ba675SRob Herring <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 238*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_APBDMA>; 239*724ba675SRob Herring resets = <&tegra_car 34>; 240*724ba675SRob Herring reset-names = "dma"; 241*724ba675SRob Herring #dma-cells = <1>; 242*724ba675SRob Herring }; 243*724ba675SRob Herring 244*724ba675SRob Herring ahb: ahb@6000c000 { 245*724ba675SRob Herring compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; 246*724ba675SRob Herring reg = <0x6000c000 0x150>; 247*724ba675SRob Herring }; 248*724ba675SRob Herring 249*724ba675SRob Herring gpio: gpio@6000d000 { 250*724ba675SRob Herring compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; 251*724ba675SRob Herring reg = <0x6000d000 0x1000>; 252*724ba675SRob Herring interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 253*724ba675SRob Herring <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 254*724ba675SRob Herring <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 255*724ba675SRob Herring <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 256*724ba675SRob Herring <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 257*724ba675SRob Herring <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 258*724ba675SRob Herring <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 259*724ba675SRob Herring <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 260*724ba675SRob Herring #gpio-cells = <2>; 261*724ba675SRob Herring gpio-controller; 262*724ba675SRob Herring #interrupt-cells = <2>; 263*724ba675SRob Herring interrupt-controller; 264*724ba675SRob Herring gpio-ranges = <&pinmux 0 0 246>; 265*724ba675SRob Herring }; 266*724ba675SRob Herring 267*724ba675SRob Herring vde@6001a000 { 268*724ba675SRob Herring compatible = "nvidia,tegra114-vde"; 269*724ba675SRob Herring reg = <0x6001a000 0x1000>, /* Syntax Engine */ 270*724ba675SRob Herring <0x6001b000 0x1000>, /* Video Bitstream Engine */ 271*724ba675SRob Herring <0x6001c000 0x100>, /* Macroblock Engine */ 272*724ba675SRob Herring <0x6001c200 0x100>, /* Post-processing Engine */ 273*724ba675SRob Herring <0x6001c400 0x100>, /* Motion Compensation Engine */ 274*724ba675SRob Herring <0x6001c600 0x100>, /* Transform Engine */ 275*724ba675SRob Herring <0x6001c800 0x100>, /* Pixel prediction block */ 276*724ba675SRob Herring <0x6001ca00 0x100>, /* Video DMA */ 277*724ba675SRob Herring <0x6001d800 0x400>; /* Video frame controls */ 278*724ba675SRob Herring reg-names = "sxe", "bsev", "mbe", "ppe", "mce", 279*724ba675SRob Herring "tfe", "ppb", "vdma", "frameid"; 280*724ba675SRob Herring iram = <&vde_pool>; /* IRAM region */ 281*724ba675SRob Herring interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ 282*724ba675SRob Herring <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ 283*724ba675SRob Herring <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ 284*724ba675SRob Herring interrupt-names = "sync-token", "bsev", "sxe"; 285*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_VDE>; 286*724ba675SRob Herring reset-names = "vde", "mc"; 287*724ba675SRob Herring resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>; 288*724ba675SRob Herring iommus = <&mc TEGRA_SWGROUP_VDE>; 289*724ba675SRob Herring }; 290*724ba675SRob Herring 291*724ba675SRob Herring apbmisc@70000800 { 292*724ba675SRob Herring compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; 293*724ba675SRob Herring reg = <0x70000800 0x64>, /* Chip revision */ 294*724ba675SRob Herring <0x70000008 0x04>; /* Strapping options */ 295*724ba675SRob Herring }; 296*724ba675SRob Herring 297*724ba675SRob Herring pinmux: pinmux@70000868 { 298*724ba675SRob Herring compatible = "nvidia,tegra114-pinmux"; 299*724ba675SRob Herring reg = <0x70000868 0x148>, /* Pad control registers */ 300*724ba675SRob Herring <0x70003000 0x40c>; /* Mux registers */ 301*724ba675SRob Herring }; 302*724ba675SRob Herring 303*724ba675SRob Herring /* 304*724ba675SRob Herring * There are two serial driver i.e. 8250 based simple serial 305*724ba675SRob Herring * driver and APB DMA based serial driver for higher baudrate 306*724ba675SRob Herring * and performace. To enable the 8250 based driver, the compatible 307*724ba675SRob Herring * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable 308*724ba675SRob Herring * the APB DMA based serial driver, the compatible is 309*724ba675SRob Herring * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". 310*724ba675SRob Herring */ 311*724ba675SRob Herring uarta: serial@70006000 { 312*724ba675SRob Herring compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 313*724ba675SRob Herring reg = <0x70006000 0x40>; 314*724ba675SRob Herring reg-shift = <2>; 315*724ba675SRob Herring interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 316*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_UARTA>; 317*724ba675SRob Herring resets = <&tegra_car 6>; 318*724ba675SRob Herring reset-names = "serial"; 319*724ba675SRob Herring dmas = <&apbdma 8>, <&apbdma 8>; 320*724ba675SRob Herring dma-names = "rx", "tx"; 321*724ba675SRob Herring status = "disabled"; 322*724ba675SRob Herring }; 323*724ba675SRob Herring 324*724ba675SRob Herring uartb: serial@70006040 { 325*724ba675SRob Herring compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 326*724ba675SRob Herring reg = <0x70006040 0x40>; 327*724ba675SRob Herring reg-shift = <2>; 328*724ba675SRob Herring interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 329*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_UARTB>; 330*724ba675SRob Herring resets = <&tegra_car 7>; 331*724ba675SRob Herring reset-names = "serial"; 332*724ba675SRob Herring dmas = <&apbdma 9>, <&apbdma 9>; 333*724ba675SRob Herring dma-names = "rx", "tx"; 334*724ba675SRob Herring status = "disabled"; 335*724ba675SRob Herring }; 336*724ba675SRob Herring 337*724ba675SRob Herring uartc: serial@70006200 { 338*724ba675SRob Herring compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 339*724ba675SRob Herring reg = <0x70006200 0x100>; 340*724ba675SRob Herring reg-shift = <2>; 341*724ba675SRob Herring interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 342*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_UARTC>; 343*724ba675SRob Herring resets = <&tegra_car 55>; 344*724ba675SRob Herring reset-names = "serial"; 345*724ba675SRob Herring dmas = <&apbdma 10>, <&apbdma 10>; 346*724ba675SRob Herring dma-names = "rx", "tx"; 347*724ba675SRob Herring status = "disabled"; 348*724ba675SRob Herring }; 349*724ba675SRob Herring 350*724ba675SRob Herring uartd: serial@70006300 { 351*724ba675SRob Herring compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 352*724ba675SRob Herring reg = <0x70006300 0x100>; 353*724ba675SRob Herring reg-shift = <2>; 354*724ba675SRob Herring interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 355*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_UARTD>; 356*724ba675SRob Herring resets = <&tegra_car 65>; 357*724ba675SRob Herring reset-names = "serial"; 358*724ba675SRob Herring dmas = <&apbdma 19>, <&apbdma 19>; 359*724ba675SRob Herring dma-names = "rx", "tx"; 360*724ba675SRob Herring status = "disabled"; 361*724ba675SRob Herring }; 362*724ba675SRob Herring 363*724ba675SRob Herring pwm: pwm@7000a000 { 364*724ba675SRob Herring compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; 365*724ba675SRob Herring reg = <0x7000a000 0x100>; 366*724ba675SRob Herring #pwm-cells = <2>; 367*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_PWM>; 368*724ba675SRob Herring resets = <&tegra_car 17>; 369*724ba675SRob Herring reset-names = "pwm"; 370*724ba675SRob Herring status = "disabled"; 371*724ba675SRob Herring }; 372*724ba675SRob Herring 373*724ba675SRob Herring i2c@7000c000 { 374*724ba675SRob Herring compatible = "nvidia,tegra114-i2c"; 375*724ba675SRob Herring reg = <0x7000c000 0x100>; 376*724ba675SRob Herring interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 377*724ba675SRob Herring #address-cells = <1>; 378*724ba675SRob Herring #size-cells = <0>; 379*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_I2C1>; 380*724ba675SRob Herring clock-names = "div-clk"; 381*724ba675SRob Herring resets = <&tegra_car 12>; 382*724ba675SRob Herring reset-names = "i2c"; 383*724ba675SRob Herring dmas = <&apbdma 21>, <&apbdma 21>; 384*724ba675SRob Herring dma-names = "rx", "tx"; 385*724ba675SRob Herring status = "disabled"; 386*724ba675SRob Herring }; 387*724ba675SRob Herring 388*724ba675SRob Herring i2c@7000c400 { 389*724ba675SRob Herring compatible = "nvidia,tegra114-i2c"; 390*724ba675SRob Herring reg = <0x7000c400 0x100>; 391*724ba675SRob Herring interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 392*724ba675SRob Herring #address-cells = <1>; 393*724ba675SRob Herring #size-cells = <0>; 394*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_I2C2>; 395*724ba675SRob Herring clock-names = "div-clk"; 396*724ba675SRob Herring resets = <&tegra_car 54>; 397*724ba675SRob Herring reset-names = "i2c"; 398*724ba675SRob Herring dmas = <&apbdma 22>, <&apbdma 22>; 399*724ba675SRob Herring dma-names = "rx", "tx"; 400*724ba675SRob Herring status = "disabled"; 401*724ba675SRob Herring }; 402*724ba675SRob Herring 403*724ba675SRob Herring i2c@7000c500 { 404*724ba675SRob Herring compatible = "nvidia,tegra114-i2c"; 405*724ba675SRob Herring reg = <0x7000c500 0x100>; 406*724ba675SRob Herring interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 407*724ba675SRob Herring #address-cells = <1>; 408*724ba675SRob Herring #size-cells = <0>; 409*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_I2C3>; 410*724ba675SRob Herring clock-names = "div-clk"; 411*724ba675SRob Herring resets = <&tegra_car 67>; 412*724ba675SRob Herring reset-names = "i2c"; 413*724ba675SRob Herring dmas = <&apbdma 23>, <&apbdma 23>; 414*724ba675SRob Herring dma-names = "rx", "tx"; 415*724ba675SRob Herring status = "disabled"; 416*724ba675SRob Herring }; 417*724ba675SRob Herring 418*724ba675SRob Herring i2c@7000c700 { 419*724ba675SRob Herring compatible = "nvidia,tegra114-i2c"; 420*724ba675SRob Herring reg = <0x7000c700 0x100>; 421*724ba675SRob Herring interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 422*724ba675SRob Herring #address-cells = <1>; 423*724ba675SRob Herring #size-cells = <0>; 424*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_I2C4>; 425*724ba675SRob Herring clock-names = "div-clk"; 426*724ba675SRob Herring resets = <&tegra_car 103>; 427*724ba675SRob Herring reset-names = "i2c"; 428*724ba675SRob Herring dmas = <&apbdma 26>, <&apbdma 26>; 429*724ba675SRob Herring dma-names = "rx", "tx"; 430*724ba675SRob Herring status = "disabled"; 431*724ba675SRob Herring }; 432*724ba675SRob Herring 433*724ba675SRob Herring i2c@7000d000 { 434*724ba675SRob Herring compatible = "nvidia,tegra114-i2c"; 435*724ba675SRob Herring reg = <0x7000d000 0x100>; 436*724ba675SRob Herring interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 437*724ba675SRob Herring #address-cells = <1>; 438*724ba675SRob Herring #size-cells = <0>; 439*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_I2C5>; 440*724ba675SRob Herring clock-names = "div-clk"; 441*724ba675SRob Herring resets = <&tegra_car 47>; 442*724ba675SRob Herring reset-names = "i2c"; 443*724ba675SRob Herring dmas = <&apbdma 24>, <&apbdma 24>; 444*724ba675SRob Herring dma-names = "rx", "tx"; 445*724ba675SRob Herring status = "disabled"; 446*724ba675SRob Herring }; 447*724ba675SRob Herring 448*724ba675SRob Herring spi@7000d400 { 449*724ba675SRob Herring compatible = "nvidia,tegra114-spi"; 450*724ba675SRob Herring reg = <0x7000d400 0x200>; 451*724ba675SRob Herring interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 452*724ba675SRob Herring #address-cells = <1>; 453*724ba675SRob Herring #size-cells = <0>; 454*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_SBC1>; 455*724ba675SRob Herring clock-names = "spi"; 456*724ba675SRob Herring resets = <&tegra_car 41>; 457*724ba675SRob Herring reset-names = "spi"; 458*724ba675SRob Herring dmas = <&apbdma 15>, <&apbdma 15>; 459*724ba675SRob Herring dma-names = "rx", "tx"; 460*724ba675SRob Herring status = "disabled"; 461*724ba675SRob Herring }; 462*724ba675SRob Herring 463*724ba675SRob Herring spi@7000d600 { 464*724ba675SRob Herring compatible = "nvidia,tegra114-spi"; 465*724ba675SRob Herring reg = <0x7000d600 0x200>; 466*724ba675SRob Herring interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 467*724ba675SRob Herring #address-cells = <1>; 468*724ba675SRob Herring #size-cells = <0>; 469*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_SBC2>; 470*724ba675SRob Herring clock-names = "spi"; 471*724ba675SRob Herring resets = <&tegra_car 44>; 472*724ba675SRob Herring reset-names = "spi"; 473*724ba675SRob Herring dmas = <&apbdma 16>, <&apbdma 16>; 474*724ba675SRob Herring dma-names = "rx", "tx"; 475*724ba675SRob Herring status = "disabled"; 476*724ba675SRob Herring }; 477*724ba675SRob Herring 478*724ba675SRob Herring spi@7000d800 { 479*724ba675SRob Herring compatible = "nvidia,tegra114-spi"; 480*724ba675SRob Herring reg = <0x7000d800 0x200>; 481*724ba675SRob Herring interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 482*724ba675SRob Herring #address-cells = <1>; 483*724ba675SRob Herring #size-cells = <0>; 484*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_SBC3>; 485*724ba675SRob Herring clock-names = "spi"; 486*724ba675SRob Herring resets = <&tegra_car 46>; 487*724ba675SRob Herring reset-names = "spi"; 488*724ba675SRob Herring dmas = <&apbdma 17>, <&apbdma 17>; 489*724ba675SRob Herring dma-names = "rx", "tx"; 490*724ba675SRob Herring status = "disabled"; 491*724ba675SRob Herring }; 492*724ba675SRob Herring 493*724ba675SRob Herring spi@7000da00 { 494*724ba675SRob Herring compatible = "nvidia,tegra114-spi"; 495*724ba675SRob Herring reg = <0x7000da00 0x200>; 496*724ba675SRob Herring interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 497*724ba675SRob Herring #address-cells = <1>; 498*724ba675SRob Herring #size-cells = <0>; 499*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_SBC4>; 500*724ba675SRob Herring clock-names = "spi"; 501*724ba675SRob Herring resets = <&tegra_car 68>; 502*724ba675SRob Herring reset-names = "spi"; 503*724ba675SRob Herring dmas = <&apbdma 18>, <&apbdma 18>; 504*724ba675SRob Herring dma-names = "rx", "tx"; 505*724ba675SRob Herring status = "disabled"; 506*724ba675SRob Herring }; 507*724ba675SRob Herring 508*724ba675SRob Herring spi@7000dc00 { 509*724ba675SRob Herring compatible = "nvidia,tegra114-spi"; 510*724ba675SRob Herring reg = <0x7000dc00 0x200>; 511*724ba675SRob Herring interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 512*724ba675SRob Herring #address-cells = <1>; 513*724ba675SRob Herring #size-cells = <0>; 514*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_SBC5>; 515*724ba675SRob Herring clock-names = "spi"; 516*724ba675SRob Herring resets = <&tegra_car 104>; 517*724ba675SRob Herring reset-names = "spi"; 518*724ba675SRob Herring dmas = <&apbdma 27>, <&apbdma 27>; 519*724ba675SRob Herring dma-names = "rx", "tx"; 520*724ba675SRob Herring status = "disabled"; 521*724ba675SRob Herring }; 522*724ba675SRob Herring 523*724ba675SRob Herring spi@7000de00 { 524*724ba675SRob Herring compatible = "nvidia,tegra114-spi"; 525*724ba675SRob Herring reg = <0x7000de00 0x200>; 526*724ba675SRob Herring interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 527*724ba675SRob Herring #address-cells = <1>; 528*724ba675SRob Herring #size-cells = <0>; 529*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_SBC6>; 530*724ba675SRob Herring clock-names = "spi"; 531*724ba675SRob Herring resets = <&tegra_car 105>; 532*724ba675SRob Herring reset-names = "spi"; 533*724ba675SRob Herring dmas = <&apbdma 28>, <&apbdma 28>; 534*724ba675SRob Herring dma-names = "rx", "tx"; 535*724ba675SRob Herring status = "disabled"; 536*724ba675SRob Herring }; 537*724ba675SRob Herring 538*724ba675SRob Herring rtc@7000e000 { 539*724ba675SRob Herring compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; 540*724ba675SRob Herring reg = <0x7000e000 0x100>; 541*724ba675SRob Herring interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 542*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_RTC>; 543*724ba675SRob Herring }; 544*724ba675SRob Herring 545*724ba675SRob Herring kbc@7000e200 { 546*724ba675SRob Herring compatible = "nvidia,tegra114-kbc"; 547*724ba675SRob Herring reg = <0x7000e200 0x100>; 548*724ba675SRob Herring interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 549*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_KBC>; 550*724ba675SRob Herring resets = <&tegra_car 36>; 551*724ba675SRob Herring reset-names = "kbc"; 552*724ba675SRob Herring status = "disabled"; 553*724ba675SRob Herring }; 554*724ba675SRob Herring 555*724ba675SRob Herring tegra_pmc: pmc@7000e400 { 556*724ba675SRob Herring compatible = "nvidia,tegra114-pmc"; 557*724ba675SRob Herring reg = <0x7000e400 0x400>; 558*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; 559*724ba675SRob Herring clock-names = "pclk", "clk32k_in"; 560*724ba675SRob Herring #clock-cells = <1>; 561*724ba675SRob Herring }; 562*724ba675SRob Herring 563*724ba675SRob Herring fuse@7000f800 { 564*724ba675SRob Herring compatible = "nvidia,tegra114-efuse"; 565*724ba675SRob Herring reg = <0x7000f800 0x400>; 566*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_FUSE>; 567*724ba675SRob Herring clock-names = "fuse"; 568*724ba675SRob Herring resets = <&tegra_car 39>; 569*724ba675SRob Herring reset-names = "fuse"; 570*724ba675SRob Herring }; 571*724ba675SRob Herring 572*724ba675SRob Herring mc: memory-controller@70019000 { 573*724ba675SRob Herring compatible = "nvidia,tegra114-mc"; 574*724ba675SRob Herring reg = <0x70019000 0x1000>; 575*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_MC>; 576*724ba675SRob Herring clock-names = "mc"; 577*724ba675SRob Herring 578*724ba675SRob Herring interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 579*724ba675SRob Herring 580*724ba675SRob Herring #reset-cells = <1>; 581*724ba675SRob Herring #iommu-cells = <1>; 582*724ba675SRob Herring }; 583*724ba675SRob Herring 584*724ba675SRob Herring ahub@70080000 { 585*724ba675SRob Herring compatible = "nvidia,tegra114-ahub"; 586*724ba675SRob Herring reg = <0x70080000 0x200>, 587*724ba675SRob Herring <0x70080200 0x100>, 588*724ba675SRob Herring <0x70081000 0x200>; 589*724ba675SRob Herring interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 590*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, 591*724ba675SRob Herring <&tegra_car TEGRA114_CLK_APBIF>; 592*724ba675SRob Herring clock-names = "d_audio", "apbif"; 593*724ba675SRob Herring resets = <&tegra_car 106>, /* d_audio */ 594*724ba675SRob Herring <&tegra_car 107>, /* apbif */ 595*724ba675SRob Herring <&tegra_car 30>, /* i2s0 */ 596*724ba675SRob Herring <&tegra_car 11>, /* i2s1 */ 597*724ba675SRob Herring <&tegra_car 18>, /* i2s2 */ 598*724ba675SRob Herring <&tegra_car 101>, /* i2s3 */ 599*724ba675SRob Herring <&tegra_car 102>, /* i2s4 */ 600*724ba675SRob Herring <&tegra_car 108>, /* dam0 */ 601*724ba675SRob Herring <&tegra_car 109>, /* dam1 */ 602*724ba675SRob Herring <&tegra_car 110>, /* dam2 */ 603*724ba675SRob Herring <&tegra_car 10>, /* spdif */ 604*724ba675SRob Herring <&tegra_car 153>, /* amx */ 605*724ba675SRob Herring <&tegra_car 154>; /* adx */ 606*724ba675SRob Herring reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 607*724ba675SRob Herring "i2s3", "i2s4", "dam0", "dam1", "dam2", 608*724ba675SRob Herring "spdif", "amx", "adx"; 609*724ba675SRob Herring dmas = <&apbdma 1>, <&apbdma 1>, 610*724ba675SRob Herring <&apbdma 2>, <&apbdma 2>, 611*724ba675SRob Herring <&apbdma 3>, <&apbdma 3>, 612*724ba675SRob Herring <&apbdma 4>, <&apbdma 4>, 613*724ba675SRob Herring <&apbdma 6>, <&apbdma 6>, 614*724ba675SRob Herring <&apbdma 7>, <&apbdma 7>, 615*724ba675SRob Herring <&apbdma 12>, <&apbdma 12>, 616*724ba675SRob Herring <&apbdma 13>, <&apbdma 13>, 617*724ba675SRob Herring <&apbdma 14>, <&apbdma 14>, 618*724ba675SRob Herring <&apbdma 29>, <&apbdma 29>; 619*724ba675SRob Herring dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 620*724ba675SRob Herring "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 621*724ba675SRob Herring "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 622*724ba675SRob Herring "rx9", "tx9"; 623*724ba675SRob Herring ranges; 624*724ba675SRob Herring #address-cells = <1>; 625*724ba675SRob Herring #size-cells = <1>; 626*724ba675SRob Herring 627*724ba675SRob Herring tegra_i2s0: i2s@70080300 { 628*724ba675SRob Herring compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 629*724ba675SRob Herring reg = <0x70080300 0x100>; 630*724ba675SRob Herring nvidia,ahub-cif-ids = <4 4>; 631*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_I2S0>; 632*724ba675SRob Herring resets = <&tegra_car 30>; 633*724ba675SRob Herring reset-names = "i2s"; 634*724ba675SRob Herring status = "disabled"; 635*724ba675SRob Herring }; 636*724ba675SRob Herring 637*724ba675SRob Herring tegra_i2s1: i2s@70080400 { 638*724ba675SRob Herring compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 639*724ba675SRob Herring reg = <0x70080400 0x100>; 640*724ba675SRob Herring nvidia,ahub-cif-ids = <5 5>; 641*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_I2S1>; 642*724ba675SRob Herring resets = <&tegra_car 11>; 643*724ba675SRob Herring reset-names = "i2s"; 644*724ba675SRob Herring status = "disabled"; 645*724ba675SRob Herring }; 646*724ba675SRob Herring 647*724ba675SRob Herring tegra_i2s2: i2s@70080500 { 648*724ba675SRob Herring compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 649*724ba675SRob Herring reg = <0x70080500 0x100>; 650*724ba675SRob Herring nvidia,ahub-cif-ids = <6 6>; 651*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_I2S2>; 652*724ba675SRob Herring resets = <&tegra_car 18>; 653*724ba675SRob Herring reset-names = "i2s"; 654*724ba675SRob Herring status = "disabled"; 655*724ba675SRob Herring }; 656*724ba675SRob Herring 657*724ba675SRob Herring tegra_i2s3: i2s@70080600 { 658*724ba675SRob Herring compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 659*724ba675SRob Herring reg = <0x70080600 0x100>; 660*724ba675SRob Herring nvidia,ahub-cif-ids = <7 7>; 661*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_I2S3>; 662*724ba675SRob Herring resets = <&tegra_car 101>; 663*724ba675SRob Herring reset-names = "i2s"; 664*724ba675SRob Herring status = "disabled"; 665*724ba675SRob Herring }; 666*724ba675SRob Herring 667*724ba675SRob Herring tegra_i2s4: i2s@70080700 { 668*724ba675SRob Herring compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 669*724ba675SRob Herring reg = <0x70080700 0x100>; 670*724ba675SRob Herring nvidia,ahub-cif-ids = <8 8>; 671*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_I2S4>; 672*724ba675SRob Herring resets = <&tegra_car 102>; 673*724ba675SRob Herring reset-names = "i2s"; 674*724ba675SRob Herring status = "disabled"; 675*724ba675SRob Herring }; 676*724ba675SRob Herring }; 677*724ba675SRob Herring 678*724ba675SRob Herring mipi: mipi@700e3000 { 679*724ba675SRob Herring compatible = "nvidia,tegra114-mipi"; 680*724ba675SRob Herring reg = <0x700e3000 0x100>; 681*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; 682*724ba675SRob Herring #nvidia,mipi-calibrate-cells = <1>; 683*724ba675SRob Herring }; 684*724ba675SRob Herring 685*724ba675SRob Herring mmc@78000000 { 686*724ba675SRob Herring compatible = "nvidia,tegra114-sdhci"; 687*724ba675SRob Herring reg = <0x78000000 0x200>; 688*724ba675SRob Herring interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 689*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; 690*724ba675SRob Herring clock-names = "sdhci"; 691*724ba675SRob Herring resets = <&tegra_car 14>; 692*724ba675SRob Herring reset-names = "sdhci"; 693*724ba675SRob Herring status = "disabled"; 694*724ba675SRob Herring }; 695*724ba675SRob Herring 696*724ba675SRob Herring mmc@78000200 { 697*724ba675SRob Herring compatible = "nvidia,tegra114-sdhci"; 698*724ba675SRob Herring reg = <0x78000200 0x200>; 699*724ba675SRob Herring interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 700*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; 701*724ba675SRob Herring clock-names = "sdhci"; 702*724ba675SRob Herring resets = <&tegra_car 9>; 703*724ba675SRob Herring reset-names = "sdhci"; 704*724ba675SRob Herring status = "disabled"; 705*724ba675SRob Herring }; 706*724ba675SRob Herring 707*724ba675SRob Herring mmc@78000400 { 708*724ba675SRob Herring compatible = "nvidia,tegra114-sdhci"; 709*724ba675SRob Herring reg = <0x78000400 0x200>; 710*724ba675SRob Herring interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 711*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; 712*724ba675SRob Herring clock-names = "sdhci"; 713*724ba675SRob Herring resets = <&tegra_car 69>; 714*724ba675SRob Herring reset-names = "sdhci"; 715*724ba675SRob Herring status = "disabled"; 716*724ba675SRob Herring }; 717*724ba675SRob Herring 718*724ba675SRob Herring mmc@78000600 { 719*724ba675SRob Herring compatible = "nvidia,tegra114-sdhci"; 720*724ba675SRob Herring reg = <0x78000600 0x200>; 721*724ba675SRob Herring interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 722*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; 723*724ba675SRob Herring clock-names = "sdhci"; 724*724ba675SRob Herring resets = <&tegra_car 15>; 725*724ba675SRob Herring reset-names = "sdhci"; 726*724ba675SRob Herring status = "disabled"; 727*724ba675SRob Herring }; 728*724ba675SRob Herring 729*724ba675SRob Herring usb@7d000000 { 730*724ba675SRob Herring compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci"; 731*724ba675SRob Herring reg = <0x7d000000 0x4000>; 732*724ba675SRob Herring interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 733*724ba675SRob Herring phy_type = "utmi"; 734*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_USBD>; 735*724ba675SRob Herring resets = <&tegra_car 22>; 736*724ba675SRob Herring reset-names = "usb"; 737*724ba675SRob Herring nvidia,phy = <&phy1>; 738*724ba675SRob Herring status = "disabled"; 739*724ba675SRob Herring }; 740*724ba675SRob Herring 741*724ba675SRob Herring phy1: usb-phy@7d000000 { 742*724ba675SRob Herring compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; 743*724ba675SRob Herring reg = <0x7d000000 0x4000>, 744*724ba675SRob Herring <0x7d000000 0x4000>; 745*724ba675SRob Herring interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 746*724ba675SRob Herring phy_type = "utmi"; 747*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_USBD>, 748*724ba675SRob Herring <&tegra_car TEGRA114_CLK_PLL_U>, 749*724ba675SRob Herring <&tegra_car TEGRA114_CLK_USBD>; 750*724ba675SRob Herring clock-names = "reg", "pll_u", "utmi-pads"; 751*724ba675SRob Herring resets = <&tegra_car 22>, <&tegra_car 22>; 752*724ba675SRob Herring reset-names = "usb", "utmi-pads"; 753*724ba675SRob Herring #phy-cells = <0>; 754*724ba675SRob Herring nvidia,hssync-start-delay = <0>; 755*724ba675SRob Herring nvidia,idle-wait-delay = <17>; 756*724ba675SRob Herring nvidia,elastic-limit = <16>; 757*724ba675SRob Herring nvidia,term-range-adj = <6>; 758*724ba675SRob Herring nvidia,xcvr-setup = <9>; 759*724ba675SRob Herring nvidia,xcvr-lsfslew = <0>; 760*724ba675SRob Herring nvidia,xcvr-lsrslew = <3>; 761*724ba675SRob Herring nvidia,hssquelch-level = <2>; 762*724ba675SRob Herring nvidia,hsdiscon-level = <5>; 763*724ba675SRob Herring nvidia,xcvr-hsslew = <12>; 764*724ba675SRob Herring nvidia,has-utmi-pad-registers; 765*724ba675SRob Herring nvidia,pmc = <&tegra_pmc 0>; 766*724ba675SRob Herring status = "disabled"; 767*724ba675SRob Herring }; 768*724ba675SRob Herring 769*724ba675SRob Herring usb@7d008000 { 770*724ba675SRob Herring compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci"; 771*724ba675SRob Herring reg = <0x7d008000 0x4000>; 772*724ba675SRob Herring interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 773*724ba675SRob Herring phy_type = "utmi"; 774*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_USB3>; 775*724ba675SRob Herring resets = <&tegra_car 59>; 776*724ba675SRob Herring reset-names = "usb"; 777*724ba675SRob Herring nvidia,phy = <&phy3>; 778*724ba675SRob Herring status = "disabled"; 779*724ba675SRob Herring }; 780*724ba675SRob Herring 781*724ba675SRob Herring phy3: usb-phy@7d008000 { 782*724ba675SRob Herring compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; 783*724ba675SRob Herring reg = <0x7d008000 0x4000>, 784*724ba675SRob Herring <0x7d000000 0x4000>; 785*724ba675SRob Herring interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 786*724ba675SRob Herring phy_type = "utmi"; 787*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_USB3>, 788*724ba675SRob Herring <&tegra_car TEGRA114_CLK_PLL_U>, 789*724ba675SRob Herring <&tegra_car TEGRA114_CLK_USBD>; 790*724ba675SRob Herring clock-names = "reg", "pll_u", "utmi-pads"; 791*724ba675SRob Herring resets = <&tegra_car 59>, <&tegra_car 22>; 792*724ba675SRob Herring reset-names = "usb", "utmi-pads"; 793*724ba675SRob Herring #phy-cells = <0>; 794*724ba675SRob Herring nvidia,hssync-start-delay = <0>; 795*724ba675SRob Herring nvidia,idle-wait-delay = <17>; 796*724ba675SRob Herring nvidia,elastic-limit = <16>; 797*724ba675SRob Herring nvidia,term-range-adj = <6>; 798*724ba675SRob Herring nvidia,xcvr-setup = <9>; 799*724ba675SRob Herring nvidia,xcvr-lsfslew = <0>; 800*724ba675SRob Herring nvidia,xcvr-lsrslew = <3>; 801*724ba675SRob Herring nvidia,hssquelch-level = <2>; 802*724ba675SRob Herring nvidia,hsdiscon-level = <5>; 803*724ba675SRob Herring nvidia,xcvr-hsslew = <12>; 804*724ba675SRob Herring nvidia,pmc = <&tegra_pmc 2>; 805*724ba675SRob Herring status = "disabled"; 806*724ba675SRob Herring }; 807*724ba675SRob Herring 808*724ba675SRob Herring cpus { 809*724ba675SRob Herring #address-cells = <1>; 810*724ba675SRob Herring #size-cells = <0>; 811*724ba675SRob Herring 812*724ba675SRob Herring cpu@0 { 813*724ba675SRob Herring device_type = "cpu"; 814*724ba675SRob Herring compatible = "arm,cortex-a15"; 815*724ba675SRob Herring reg = <0>; 816*724ba675SRob Herring }; 817*724ba675SRob Herring 818*724ba675SRob Herring cpu@1 { 819*724ba675SRob Herring device_type = "cpu"; 820*724ba675SRob Herring compatible = "arm,cortex-a15"; 821*724ba675SRob Herring reg = <1>; 822*724ba675SRob Herring }; 823*724ba675SRob Herring 824*724ba675SRob Herring cpu@2 { 825*724ba675SRob Herring device_type = "cpu"; 826*724ba675SRob Herring compatible = "arm,cortex-a15"; 827*724ba675SRob Herring reg = <2>; 828*724ba675SRob Herring }; 829*724ba675SRob Herring 830*724ba675SRob Herring cpu@3 { 831*724ba675SRob Herring device_type = "cpu"; 832*724ba675SRob Herring compatible = "arm,cortex-a15"; 833*724ba675SRob Herring reg = <3>; 834*724ba675SRob Herring }; 835*724ba675SRob Herring }; 836*724ba675SRob Herring 837*724ba675SRob Herring timer { 838*724ba675SRob Herring compatible = "arm,armv7-timer"; 839*724ba675SRob Herring interrupts = 840*724ba675SRob Herring <GIC_PPI 13 841*724ba675SRob Herring (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 842*724ba675SRob Herring <GIC_PPI 14 843*724ba675SRob Herring (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 844*724ba675SRob Herring <GIC_PPI 11 845*724ba675SRob Herring (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 846*724ba675SRob Herring <GIC_PPI 10 847*724ba675SRob Herring (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 848*724ba675SRob Herring interrupt-parent = <&gic>; 849*724ba675SRob Herring }; 850*724ba675SRob Herring}; 851