1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-or-later 2*724ba675SRob Herring/* 3*724ba675SRob Herring * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC 4*724ba675SRob Herring * applies to AT91SAM9G45, AT91SAM9M10, 5*724ba675SRob Herring * AT91SAM9G46, AT91SAM9M11 SoC 6*724ba675SRob Herring * 7*724ba675SRob Herring * Copyright (C) 2011 Atmel, 8*724ba675SRob Herring * 2011 Nicolas Ferre <nicolas.ferre@atmel.com> 9*724ba675SRob Herring */ 10*724ba675SRob Herring 11*724ba675SRob Herring#include <dt-bindings/dma/at91.h> 12*724ba675SRob Herring#include <dt-bindings/pinctrl/at91.h> 13*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 14*724ba675SRob Herring#include <dt-bindings/gpio/gpio.h> 15*724ba675SRob Herring#include <dt-bindings/clock/at91.h> 16*724ba675SRob Herring#include <dt-bindings/mfd/at91-usart.h> 17*724ba675SRob Herring 18*724ba675SRob Herring/ { 19*724ba675SRob Herring #address-cells = <1>; 20*724ba675SRob Herring #size-cells = <1>; 21*724ba675SRob Herring model = "Atmel AT91SAM9G45 family SoC"; 22*724ba675SRob Herring compatible = "atmel,at91sam9g45"; 23*724ba675SRob Herring interrupt-parent = <&aic>; 24*724ba675SRob Herring 25*724ba675SRob Herring aliases { 26*724ba675SRob Herring serial0 = &dbgu; 27*724ba675SRob Herring serial1 = &usart0; 28*724ba675SRob Herring serial2 = &usart1; 29*724ba675SRob Herring serial3 = &usart2; 30*724ba675SRob Herring serial4 = &usart3; 31*724ba675SRob Herring gpio0 = &pioA; 32*724ba675SRob Herring gpio1 = &pioB; 33*724ba675SRob Herring gpio2 = &pioC; 34*724ba675SRob Herring gpio3 = &pioD; 35*724ba675SRob Herring gpio4 = &pioE; 36*724ba675SRob Herring tcb0 = &tcb0; 37*724ba675SRob Herring tcb1 = &tcb1; 38*724ba675SRob Herring i2c0 = &i2c0; 39*724ba675SRob Herring i2c1 = &i2c1; 40*724ba675SRob Herring ssc0 = &ssc0; 41*724ba675SRob Herring ssc1 = &ssc1; 42*724ba675SRob Herring pwm0 = &pwm0; 43*724ba675SRob Herring }; 44*724ba675SRob Herring cpus { 45*724ba675SRob Herring #address-cells = <1>; 46*724ba675SRob Herring #size-cells = <0>; 47*724ba675SRob Herring 48*724ba675SRob Herring cpu@0 { 49*724ba675SRob Herring compatible = "arm,arm926ej-s"; 50*724ba675SRob Herring device_type = "cpu"; 51*724ba675SRob Herring reg = <0>; 52*724ba675SRob Herring }; 53*724ba675SRob Herring }; 54*724ba675SRob Herring 55*724ba675SRob Herring memory@70000000 { 56*724ba675SRob Herring device_type = "memory"; 57*724ba675SRob Herring reg = <0x70000000 0x10000000>; 58*724ba675SRob Herring }; 59*724ba675SRob Herring 60*724ba675SRob Herring clocks { 61*724ba675SRob Herring slow_xtal: slow_xtal { 62*724ba675SRob Herring compatible = "fixed-clock"; 63*724ba675SRob Herring #clock-cells = <0>; 64*724ba675SRob Herring clock-frequency = <0>; 65*724ba675SRob Herring }; 66*724ba675SRob Herring 67*724ba675SRob Herring main_xtal: main_xtal { 68*724ba675SRob Herring compatible = "fixed-clock"; 69*724ba675SRob Herring #clock-cells = <0>; 70*724ba675SRob Herring clock-frequency = <0>; 71*724ba675SRob Herring }; 72*724ba675SRob Herring 73*724ba675SRob Herring adc_op_clk: adc_op_clk { 74*724ba675SRob Herring compatible = "fixed-clock"; 75*724ba675SRob Herring #clock-cells = <0>; 76*724ba675SRob Herring clock-frequency = <300000>; 77*724ba675SRob Herring }; 78*724ba675SRob Herring }; 79*724ba675SRob Herring 80*724ba675SRob Herring sram: sram@300000 { 81*724ba675SRob Herring compatible = "mmio-sram"; 82*724ba675SRob Herring reg = <0x00300000 0x10000>; 83*724ba675SRob Herring #address-cells = <1>; 84*724ba675SRob Herring #size-cells = <1>; 85*724ba675SRob Herring ranges = <0 0x00300000 0x10000>; 86*724ba675SRob Herring }; 87*724ba675SRob Herring 88*724ba675SRob Herring ahb { 89*724ba675SRob Herring compatible = "simple-bus"; 90*724ba675SRob Herring #address-cells = <1>; 91*724ba675SRob Herring #size-cells = <1>; 92*724ba675SRob Herring ranges; 93*724ba675SRob Herring 94*724ba675SRob Herring apb { 95*724ba675SRob Herring compatible = "simple-bus"; 96*724ba675SRob Herring #address-cells = <1>; 97*724ba675SRob Herring #size-cells = <1>; 98*724ba675SRob Herring ranges; 99*724ba675SRob Herring 100*724ba675SRob Herring aic: interrupt-controller@fffff000 { 101*724ba675SRob Herring #interrupt-cells = <3>; 102*724ba675SRob Herring compatible = "atmel,at91rm9200-aic"; 103*724ba675SRob Herring interrupt-controller; 104*724ba675SRob Herring reg = <0xfffff000 0x200>; 105*724ba675SRob Herring atmel,external-irqs = <31>; 106*724ba675SRob Herring }; 107*724ba675SRob Herring 108*724ba675SRob Herring ramc0: ramc@ffffe400 { 109*724ba675SRob Herring compatible = "atmel,at91sam9g45-ddramc"; 110*724ba675SRob Herring reg = <0xffffe400 0x200>; 111*724ba675SRob Herring clocks = <&pmc PMC_TYPE_SYSTEM 2>; 112*724ba675SRob Herring clock-names = "ddrck"; 113*724ba675SRob Herring }; 114*724ba675SRob Herring 115*724ba675SRob Herring ramc1: ramc@ffffe600 { 116*724ba675SRob Herring compatible = "atmel,at91sam9g45-ddramc"; 117*724ba675SRob Herring reg = <0xffffe600 0x200>; 118*724ba675SRob Herring clocks = <&pmc PMC_TYPE_SYSTEM 2>; 119*724ba675SRob Herring clock-names = "ddrck"; 120*724ba675SRob Herring }; 121*724ba675SRob Herring 122*724ba675SRob Herring smc: smc@ffffe800 { 123*724ba675SRob Herring compatible = "atmel,at91sam9260-smc", "syscon"; 124*724ba675SRob Herring reg = <0xffffe800 0x200>; 125*724ba675SRob Herring }; 126*724ba675SRob Herring 127*724ba675SRob Herring matrix: matrix@ffffea00 { 128*724ba675SRob Herring compatible = "atmel,at91sam9g45-matrix", "syscon"; 129*724ba675SRob Herring reg = <0xffffea00 0x200>; 130*724ba675SRob Herring }; 131*724ba675SRob Herring 132*724ba675SRob Herring pmc: clock-controller@fffffc00 { 133*724ba675SRob Herring compatible = "atmel,at91sam9g45-pmc", "syscon"; 134*724ba675SRob Herring reg = <0xfffffc00 0x100>; 135*724ba675SRob Herring interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 136*724ba675SRob Herring #clock-cells = <2>; 137*724ba675SRob Herring clocks = <&clk32k>, <&main_xtal>; 138*724ba675SRob Herring clock-names = "slow_clk", "main_xtal"; 139*724ba675SRob Herring }; 140*724ba675SRob Herring 141*724ba675SRob Herring reset-controller@fffffd00 { 142*724ba675SRob Herring compatible = "atmel,at91sam9g45-rstc"; 143*724ba675SRob Herring reg = <0xfffffd00 0x10>; 144*724ba675SRob Herring clocks = <&clk32k>; 145*724ba675SRob Herring }; 146*724ba675SRob Herring 147*724ba675SRob Herring pit: timer@fffffd30 { 148*724ba675SRob Herring compatible = "atmel,at91sam9260-pit"; 149*724ba675SRob Herring reg = <0xfffffd30 0xf>; 150*724ba675SRob Herring interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 151*724ba675SRob Herring clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 152*724ba675SRob Herring }; 153*724ba675SRob Herring 154*724ba675SRob Herring 155a4bd03e7SArnd Bergmann poweroff@fffffd10 { 156*724ba675SRob Herring compatible = "atmel,at91sam9rl-shdwc"; 157*724ba675SRob Herring reg = <0xfffffd10 0x10>; 158*724ba675SRob Herring clocks = <&clk32k>; 159*724ba675SRob Herring }; 160*724ba675SRob Herring 161*724ba675SRob Herring tcb0: timer@fff7c000 { 162*724ba675SRob Herring compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; 163*724ba675SRob Herring #address-cells = <1>; 164*724ba675SRob Herring #size-cells = <0>; 165*724ba675SRob Herring reg = <0xfff7c000 0x100>; 166*724ba675SRob Herring interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; 167*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; 168*724ba675SRob Herring clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 169*724ba675SRob Herring }; 170*724ba675SRob Herring 171*724ba675SRob Herring tcb1: timer@fffd4000 { 172*724ba675SRob Herring compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; 173*724ba675SRob Herring #address-cells = <1>; 174*724ba675SRob Herring #size-cells = <0>; 175*724ba675SRob Herring reg = <0xfffd4000 0x100>; 176*724ba675SRob Herring interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; 177*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; 178*724ba675SRob Herring clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 179*724ba675SRob Herring }; 180*724ba675SRob Herring 181*724ba675SRob Herring dma: dma-controller@ffffec00 { 182*724ba675SRob Herring compatible = "atmel,at91sam9g45-dma"; 183*724ba675SRob Herring reg = <0xffffec00 0x200>; 184*724ba675SRob Herring interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; 185*724ba675SRob Herring #dma-cells = <2>; 186*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 187*724ba675SRob Herring clock-names = "dma_clk"; 188*724ba675SRob Herring }; 189*724ba675SRob Herring 190*724ba675SRob Herring pinctrl@fffff200 { 191*724ba675SRob Herring #address-cells = <1>; 192*724ba675SRob Herring #size-cells = <1>; 193*724ba675SRob Herring compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; 194*724ba675SRob Herring ranges = <0xfffff200 0xfffff200 0xa00>; 195*724ba675SRob Herring 196*724ba675SRob Herring atmel,mux-mask = < 197*724ba675SRob Herring /* A B */ 198*724ba675SRob Herring 0xffffffff 0xffc003ff /* pioA */ 199*724ba675SRob Herring 0xffffffff 0x800f8f00 /* pioB */ 200*724ba675SRob Herring 0xffffffff 0x00000e00 /* pioC */ 201*724ba675SRob Herring 0xffffffff 0xff0c1381 /* pioD */ 202*724ba675SRob Herring 0xffffffff 0x81ffff81 /* pioE */ 203*724ba675SRob Herring >; 204*724ba675SRob Herring 205*724ba675SRob Herring /* shared pinctrl settings */ 206*724ba675SRob Herring ac97 { 207*724ba675SRob Herring pinctrl_ac97: ac97-0 { 208*724ba675SRob Herring atmel,pins = 209*724ba675SRob Herring <AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* AC97RX */ 210*724ba675SRob Herring AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* AC97TX */ 211*724ba675SRob Herring AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* AC97FS */ 212*724ba675SRob Herring AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* AC97CK */ 213*724ba675SRob Herring }; 214*724ba675SRob Herring }; 215*724ba675SRob Herring 216*724ba675SRob Herring adc0 { 217*724ba675SRob Herring pinctrl_adc0_adtrg: adc0_adtrg { 218*724ba675SRob Herring atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; 219*724ba675SRob Herring }; 220*724ba675SRob Herring pinctrl_adc0_ad0: adc0_ad0 { 221*724ba675SRob Herring atmel,pins = <AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 222*724ba675SRob Herring }; 223*724ba675SRob Herring pinctrl_adc0_ad1: adc0_ad1 { 224*724ba675SRob Herring atmel,pins = <AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 225*724ba675SRob Herring }; 226*724ba675SRob Herring pinctrl_adc0_ad2: adc0_ad2 { 227*724ba675SRob Herring atmel,pins = <AT91_PIOD 22 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 228*724ba675SRob Herring }; 229*724ba675SRob Herring pinctrl_adc0_ad3: adc0_ad3 { 230*724ba675SRob Herring atmel,pins = <AT91_PIOD 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 231*724ba675SRob Herring }; 232*724ba675SRob Herring pinctrl_adc0_ad4: adc0_ad4 { 233*724ba675SRob Herring atmel,pins = <AT91_PIOD 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 234*724ba675SRob Herring }; 235*724ba675SRob Herring pinctrl_adc0_ad5: adc0_ad5 { 236*724ba675SRob Herring atmel,pins = <AT91_PIOD 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 237*724ba675SRob Herring }; 238*724ba675SRob Herring pinctrl_adc0_ad6: adc0_ad6 { 239*724ba675SRob Herring atmel,pins = <AT91_PIOD 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 240*724ba675SRob Herring }; 241*724ba675SRob Herring pinctrl_adc0_ad7: adc0_ad7 { 242*724ba675SRob Herring atmel,pins = <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 243*724ba675SRob Herring }; 244*724ba675SRob Herring }; 245*724ba675SRob Herring 246*724ba675SRob Herring dbgu { 247*724ba675SRob Herring pinctrl_dbgu: dbgu-0 { 248*724ba675SRob Herring atmel,pins = 249*724ba675SRob Herring <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 250*724ba675SRob Herring AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; 251*724ba675SRob Herring }; 252*724ba675SRob Herring }; 253*724ba675SRob Herring 254*724ba675SRob Herring i2c0 { 255*724ba675SRob Herring pinctrl_i2c0: i2c0-0 { 256*724ba675SRob Herring atmel,pins = 257*724ba675SRob Herring <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A TWCK0 */ 258*724ba675SRob Herring AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */ 259*724ba675SRob Herring }; 260*724ba675SRob Herring }; 261*724ba675SRob Herring 262*724ba675SRob Herring i2c1 { 263*724ba675SRob Herring pinctrl_i2c1: i2c1-0 { 264*724ba675SRob Herring atmel,pins = 265*724ba675SRob Herring <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A TWCK1 */ 266*724ba675SRob Herring AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */ 267*724ba675SRob Herring }; 268*724ba675SRob Herring }; 269*724ba675SRob Herring 270*724ba675SRob Herring isi { 271*724ba675SRob Herring pinctrl_isi_data_0_7: isi-0-data-0-7 { 272*724ba675SRob Herring atmel,pins = 273*724ba675SRob Herring <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */ 274*724ba675SRob Herring AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */ 275*724ba675SRob Herring AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */ 276*724ba675SRob Herring AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */ 277*724ba675SRob Herring AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */ 278*724ba675SRob Herring AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */ 279*724ba675SRob Herring AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */ 280*724ba675SRob Herring AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */ 281*724ba675SRob Herring AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */ 282*724ba675SRob Herring AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */ 283*724ba675SRob Herring AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */ 284*724ba675SRob Herring }; 285*724ba675SRob Herring 286*724ba675SRob Herring pinctrl_isi_data_8_9: isi-0-data-8-9 { 287*724ba675SRob Herring atmel,pins = 288*724ba675SRob Herring <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */ 289*724ba675SRob Herring AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D9 */ 290*724ba675SRob Herring }; 291*724ba675SRob Herring 292*724ba675SRob Herring pinctrl_isi_data_10_11: isi-0-data-10-11 { 293*724ba675SRob Herring atmel,pins = 294*724ba675SRob Herring <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */ 295*724ba675SRob Herring AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D11 */ 296*724ba675SRob Herring }; 297*724ba675SRob Herring }; 298*724ba675SRob Herring 299*724ba675SRob Herring usart0 { 300*724ba675SRob Herring pinctrl_usart0: usart0-0 { 301*724ba675SRob Herring atmel,pins = 302*724ba675SRob Herring <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 303*724ba675SRob Herring AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 304*724ba675SRob Herring }; 305*724ba675SRob Herring 306*724ba675SRob Herring pinctrl_usart0_rts: usart0_rts-0 { 307*724ba675SRob Herring atmel,pins = 308*724ba675SRob Herring <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */ 309*724ba675SRob Herring }; 310*724ba675SRob Herring 311*724ba675SRob Herring pinctrl_usart0_cts: usart0_cts-0 { 312*724ba675SRob Herring atmel,pins = 313*724ba675SRob Herring <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */ 314*724ba675SRob Herring }; 315*724ba675SRob Herring }; 316*724ba675SRob Herring 317*724ba675SRob Herring usart1 { 318*724ba675SRob Herring pinctrl_usart1: usart1-0 { 319*724ba675SRob Herring atmel,pins = 320*724ba675SRob Herring <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 321*724ba675SRob Herring AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 322*724ba675SRob Herring }; 323*724ba675SRob Herring 324*724ba675SRob Herring pinctrl_usart1_rts: usart1_rts-0 { 325*724ba675SRob Herring atmel,pins = 326*724ba675SRob Herring <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */ 327*724ba675SRob Herring }; 328*724ba675SRob Herring 329*724ba675SRob Herring pinctrl_usart1_cts: usart1_cts-0 { 330*724ba675SRob Herring atmel,pins = 331*724ba675SRob Herring <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */ 332*724ba675SRob Herring }; 333*724ba675SRob Herring }; 334*724ba675SRob Herring 335*724ba675SRob Herring usart2 { 336*724ba675SRob Herring pinctrl_usart2: usart2-0 { 337*724ba675SRob Herring atmel,pins = 338*724ba675SRob Herring <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 339*724ba675SRob Herring AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 340*724ba675SRob Herring }; 341*724ba675SRob Herring 342*724ba675SRob Herring pinctrl_usart2_rts: usart2_rts-0 { 343*724ba675SRob Herring atmel,pins = 344*724ba675SRob Herring <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */ 345*724ba675SRob Herring }; 346*724ba675SRob Herring 347*724ba675SRob Herring pinctrl_usart2_cts: usart2_cts-0 { 348*724ba675SRob Herring atmel,pins = 349*724ba675SRob Herring <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */ 350*724ba675SRob Herring }; 351*724ba675SRob Herring }; 352*724ba675SRob Herring 353*724ba675SRob Herring usart3 { 354*724ba675SRob Herring pinctrl_usart3: usart3-0 { 355*724ba675SRob Herring atmel,pins = 356*724ba675SRob Herring <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 357*724ba675SRob Herring AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 358*724ba675SRob Herring }; 359*724ba675SRob Herring 360*724ba675SRob Herring pinctrl_usart3_rts: usart3_rts-0 { 361*724ba675SRob Herring atmel,pins = 362*724ba675SRob Herring <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */ 363*724ba675SRob Herring }; 364*724ba675SRob Herring 365*724ba675SRob Herring pinctrl_usart3_cts: usart3_cts-0 { 366*724ba675SRob Herring atmel,pins = 367*724ba675SRob Herring <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */ 368*724ba675SRob Herring }; 369*724ba675SRob Herring }; 370*724ba675SRob Herring 371*724ba675SRob Herring nand { 372*724ba675SRob Herring pinctrl_nand_rb: nand-rb-0 { 373*724ba675SRob Herring atmel,pins = 374*724ba675SRob Herring <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; 375*724ba675SRob Herring }; 376*724ba675SRob Herring 377*724ba675SRob Herring pinctrl_nand_cs: nand-cs-0 { 378*724ba675SRob Herring atmel,pins = 379*724ba675SRob Herring <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; 380*724ba675SRob Herring }; 381*724ba675SRob Herring }; 382*724ba675SRob Herring 383*724ba675SRob Herring macb { 384*724ba675SRob Herring pinctrl_macb_rmii: macb_rmii-0 { 385*724ba675SRob Herring atmel,pins = 386*724ba675SRob Herring <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */ 387*724ba675SRob Herring AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */ 388*724ba675SRob Herring AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ 389*724ba675SRob Herring AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ 390*724ba675SRob Herring AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ 391*724ba675SRob Herring AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ 392*724ba675SRob Herring AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */ 393*724ba675SRob Herring AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ 394*724ba675SRob Herring AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */ 395*724ba675SRob Herring AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */ 396*724ba675SRob Herring }; 397*724ba675SRob Herring 398*724ba675SRob Herring pinctrl_macb_rmii_mii: macb_rmii_mii-0 { 399*724ba675SRob Herring atmel,pins = 400*724ba675SRob Herring <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */ 401*724ba675SRob Herring AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */ 402*724ba675SRob Herring AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */ 403*724ba675SRob Herring AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */ 404*724ba675SRob Herring AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ 405*724ba675SRob Herring AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ 406*724ba675SRob Herring AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */ 407*724ba675SRob Herring AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ 408*724ba675SRob Herring }; 409*724ba675SRob Herring }; 410*724ba675SRob Herring 411*724ba675SRob Herring mmc0 { 412*724ba675SRob Herring pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { 413*724ba675SRob Herring atmel,pins = 414*724ba675SRob Herring <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */ 415*724ba675SRob Herring AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ 416*724ba675SRob Herring AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */ 417*724ba675SRob Herring }; 418*724ba675SRob Herring 419*724ba675SRob Herring pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { 420*724ba675SRob Herring atmel,pins = 421*724ba675SRob Herring <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */ 422*724ba675SRob Herring AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */ 423*724ba675SRob Herring AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */ 424*724ba675SRob Herring }; 425*724ba675SRob Herring 426*724ba675SRob Herring pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { 427*724ba675SRob Herring atmel,pins = 428*724ba675SRob Herring <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */ 429*724ba675SRob Herring AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ 430*724ba675SRob Herring AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */ 431*724ba675SRob Herring AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */ 432*724ba675SRob Herring }; 433*724ba675SRob Herring }; 434*724ba675SRob Herring 435*724ba675SRob Herring mmc1 { 436*724ba675SRob Herring pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { 437*724ba675SRob Herring atmel,pins = 438*724ba675SRob Herring <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */ 439*724ba675SRob Herring AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */ 440*724ba675SRob Herring AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */ 441*724ba675SRob Herring }; 442*724ba675SRob Herring 443*724ba675SRob Herring pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { 444*724ba675SRob Herring atmel,pins = 445*724ba675SRob Herring <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */ 446*724ba675SRob Herring AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */ 447*724ba675SRob Herring AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */ 448*724ba675SRob Herring }; 449*724ba675SRob Herring 450*724ba675SRob Herring pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 { 451*724ba675SRob Herring atmel,pins = 452*724ba675SRob Herring <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */ 453*724ba675SRob Herring AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */ 454*724ba675SRob Herring AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */ 455*724ba675SRob Herring AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */ 456*724ba675SRob Herring }; 457*724ba675SRob Herring }; 458*724ba675SRob Herring 459*724ba675SRob Herring ssc0 { 460*724ba675SRob Herring pinctrl_ssc0_tx: ssc0_tx-0 { 461*724ba675SRob Herring atmel,pins = 462*724ba675SRob Herring <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */ 463*724ba675SRob Herring AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */ 464*724ba675SRob Herring AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */ 465*724ba675SRob Herring }; 466*724ba675SRob Herring 467*724ba675SRob Herring pinctrl_ssc0_rx: ssc0_rx-0 { 468*724ba675SRob Herring atmel,pins = 469*724ba675SRob Herring <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */ 470*724ba675SRob Herring AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */ 471*724ba675SRob Herring AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */ 472*724ba675SRob Herring }; 473*724ba675SRob Herring }; 474*724ba675SRob Herring 475*724ba675SRob Herring ssc1 { 476*724ba675SRob Herring pinctrl_ssc1_tx: ssc1_tx-0 { 477*724ba675SRob Herring atmel,pins = 478*724ba675SRob Herring <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */ 479*724ba675SRob Herring AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */ 480*724ba675SRob Herring AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */ 481*724ba675SRob Herring }; 482*724ba675SRob Herring 483*724ba675SRob Herring pinctrl_ssc1_rx: ssc1_rx-0 { 484*724ba675SRob Herring atmel,pins = 485*724ba675SRob Herring <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */ 486*724ba675SRob Herring AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */ 487*724ba675SRob Herring AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */ 488*724ba675SRob Herring }; 489*724ba675SRob Herring }; 490*724ba675SRob Herring 491*724ba675SRob Herring spi0 { 492*724ba675SRob Herring pinctrl_spi0: spi0-0 { 493*724ba675SRob Herring atmel,pins = 494*724ba675SRob Herring <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */ 495*724ba675SRob Herring AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */ 496*724ba675SRob Herring AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */ 497*724ba675SRob Herring }; 498*724ba675SRob Herring }; 499*724ba675SRob Herring 500*724ba675SRob Herring spi1 { 501*724ba675SRob Herring pinctrl_spi1: spi1-0 { 502*724ba675SRob Herring atmel,pins = 503*724ba675SRob Herring <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */ 504*724ba675SRob Herring AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */ 505*724ba675SRob Herring AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */ 506*724ba675SRob Herring }; 507*724ba675SRob Herring }; 508*724ba675SRob Herring 509*724ba675SRob Herring tcb0 { 510*724ba675SRob Herring pinctrl_tcb0_tclk0: tcb0_tclk0-0 { 511*724ba675SRob Herring atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; 512*724ba675SRob Herring }; 513*724ba675SRob Herring 514*724ba675SRob Herring pinctrl_tcb0_tclk1: tcb0_tclk1-0 { 515*724ba675SRob Herring atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; 516*724ba675SRob Herring }; 517*724ba675SRob Herring 518*724ba675SRob Herring pinctrl_tcb0_tclk2: tcb0_tclk2-0 { 519*724ba675SRob Herring atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; 520*724ba675SRob Herring }; 521*724ba675SRob Herring 522*724ba675SRob Herring pinctrl_tcb0_tioa0: tcb0_tioa0-0 { 523*724ba675SRob Herring atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; 524*724ba675SRob Herring }; 525*724ba675SRob Herring 526*724ba675SRob Herring pinctrl_tcb0_tioa1: tcb0_tioa1-0 { 527*724ba675SRob Herring atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; 528*724ba675SRob Herring }; 529*724ba675SRob Herring 530*724ba675SRob Herring pinctrl_tcb0_tioa2: tcb0_tioa2-0 { 531*724ba675SRob Herring atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; 532*724ba675SRob Herring }; 533*724ba675SRob Herring 534*724ba675SRob Herring pinctrl_tcb0_tiob0: tcb0_tiob0-0 { 535*724ba675SRob Herring atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; 536*724ba675SRob Herring }; 537*724ba675SRob Herring 538*724ba675SRob Herring pinctrl_tcb0_tiob1: tcb0_tiob1-0 { 539*724ba675SRob Herring atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; 540*724ba675SRob Herring }; 541*724ba675SRob Herring 542*724ba675SRob Herring pinctrl_tcb0_tiob2: tcb0_tiob2-0 { 543*724ba675SRob Herring atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; 544*724ba675SRob Herring }; 545*724ba675SRob Herring }; 546*724ba675SRob Herring 547*724ba675SRob Herring tcb1 { 548*724ba675SRob Herring pinctrl_tcb1_tclk0: tcb1_tclk0-0 { 549*724ba675SRob Herring atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; 550*724ba675SRob Herring }; 551*724ba675SRob Herring 552*724ba675SRob Herring pinctrl_tcb1_tclk1: tcb1_tclk1-0 { 553*724ba675SRob Herring atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; 554*724ba675SRob Herring }; 555*724ba675SRob Herring 556*724ba675SRob Herring pinctrl_tcb1_tclk2: tcb1_tclk2-0 { 557*724ba675SRob Herring atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; 558*724ba675SRob Herring }; 559*724ba675SRob Herring 560*724ba675SRob Herring pinctrl_tcb1_tioa0: tcb1_tioa0-0 { 561*724ba675SRob Herring atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; 562*724ba675SRob Herring }; 563*724ba675SRob Herring 564*724ba675SRob Herring pinctrl_tcb1_tioa1: tcb1_tioa1-0 { 565*724ba675SRob Herring atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; 566*724ba675SRob Herring }; 567*724ba675SRob Herring 568*724ba675SRob Herring pinctrl_tcb1_tioa2: tcb1_tioa2-0 { 569*724ba675SRob Herring atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; 570*724ba675SRob Herring }; 571*724ba675SRob Herring 572*724ba675SRob Herring pinctrl_tcb1_tiob0: tcb1_tiob0-0 { 573*724ba675SRob Herring atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; 574*724ba675SRob Herring }; 575*724ba675SRob Herring 576*724ba675SRob Herring pinctrl_tcb1_tiob1: tcb1_tiob1-0 { 577*724ba675SRob Herring atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; 578*724ba675SRob Herring }; 579*724ba675SRob Herring 580*724ba675SRob Herring pinctrl_tcb1_tiob2: tcb1_tiob2-0 { 581*724ba675SRob Herring atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; 582*724ba675SRob Herring }; 583*724ba675SRob Herring }; 584*724ba675SRob Herring 585*724ba675SRob Herring fb { 586*724ba675SRob Herring pinctrl_fb: fb-0 { 587*724ba675SRob Herring atmel,pins = 588*724ba675SRob Herring <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */ 589*724ba675SRob Herring AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE2 periph A */ 590*724ba675SRob Herring AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE3 periph A */ 591*724ba675SRob Herring AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE4 periph A */ 592*724ba675SRob Herring AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE5 periph A */ 593*724ba675SRob Herring AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE6 periph A */ 594*724ba675SRob Herring AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE7 periph A */ 595*724ba675SRob Herring AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE8 periph A */ 596*724ba675SRob Herring AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE9 periph A */ 597*724ba675SRob Herring AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE10 periph A */ 598*724ba675SRob Herring AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE11 periph A */ 599*724ba675SRob Herring AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE12 periph A */ 600*724ba675SRob Herring AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE13 periph A */ 601*724ba675SRob Herring AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE14 periph A */ 602*724ba675SRob Herring AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE15 periph A */ 603*724ba675SRob Herring AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE16 periph A */ 604*724ba675SRob Herring AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE17 periph A */ 605*724ba675SRob Herring AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE18 periph A */ 606*724ba675SRob Herring AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE19 periph A */ 607*724ba675SRob Herring AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE20 periph A */ 608*724ba675SRob Herring AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */ 609*724ba675SRob Herring AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE22 periph A */ 610*724ba675SRob Herring AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */ 611*724ba675SRob Herring AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */ 612*724ba675SRob Herring AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */ 613*724ba675SRob Herring AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */ 614*724ba675SRob Herring AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */ 615*724ba675SRob Herring AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */ 616*724ba675SRob Herring AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */ 617*724ba675SRob Herring AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */ 618*724ba675SRob Herring }; 619*724ba675SRob Herring }; 620*724ba675SRob Herring 621*724ba675SRob Herring pioA: gpio@fffff200 { 622*724ba675SRob Herring compatible = "atmel,at91rm9200-gpio"; 623*724ba675SRob Herring reg = <0xfffff200 0x200>; 624*724ba675SRob Herring interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 625*724ba675SRob Herring #gpio-cells = <2>; 626*724ba675SRob Herring gpio-controller; 627*724ba675SRob Herring interrupt-controller; 628*724ba675SRob Herring #interrupt-cells = <2>; 629*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 630*724ba675SRob Herring }; 631*724ba675SRob Herring 632*724ba675SRob Herring pioB: gpio@fffff400 { 633*724ba675SRob Herring compatible = "atmel,at91rm9200-gpio"; 634*724ba675SRob Herring reg = <0xfffff400 0x200>; 635*724ba675SRob Herring interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 636*724ba675SRob Herring #gpio-cells = <2>; 637*724ba675SRob Herring gpio-controller; 638*724ba675SRob Herring interrupt-controller; 639*724ba675SRob Herring #interrupt-cells = <2>; 640*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; 641*724ba675SRob Herring }; 642*724ba675SRob Herring 643*724ba675SRob Herring pioC: gpio@fffff600 { 644*724ba675SRob Herring compatible = "atmel,at91rm9200-gpio"; 645*724ba675SRob Herring reg = <0xfffff600 0x200>; 646*724ba675SRob Herring interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 647*724ba675SRob Herring #gpio-cells = <2>; 648*724ba675SRob Herring gpio-controller; 649*724ba675SRob Herring interrupt-controller; 650*724ba675SRob Herring #interrupt-cells = <2>; 651*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; 652*724ba675SRob Herring }; 653*724ba675SRob Herring 654*724ba675SRob Herring pioD: gpio@fffff800 { 655*724ba675SRob Herring compatible = "atmel,at91rm9200-gpio"; 656*724ba675SRob Herring reg = <0xfffff800 0x200>; 657*724ba675SRob Herring interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; 658*724ba675SRob Herring #gpio-cells = <2>; 659*724ba675SRob Herring gpio-controller; 660*724ba675SRob Herring interrupt-controller; 661*724ba675SRob Herring #interrupt-cells = <2>; 662*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 663*724ba675SRob Herring }; 664*724ba675SRob Herring 665*724ba675SRob Herring pioE: gpio@fffffa00 { 666*724ba675SRob Herring compatible = "atmel,at91rm9200-gpio"; 667*724ba675SRob Herring reg = <0xfffffa00 0x200>; 668*724ba675SRob Herring interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; 669*724ba675SRob Herring #gpio-cells = <2>; 670*724ba675SRob Herring gpio-controller; 671*724ba675SRob Herring interrupt-controller; 672*724ba675SRob Herring #interrupt-cells = <2>; 673*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 674*724ba675SRob Herring }; 675*724ba675SRob Herring }; 676*724ba675SRob Herring 677*724ba675SRob Herring dbgu: serial@ffffee00 { 678*724ba675SRob Herring compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 679*724ba675SRob Herring atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 680*724ba675SRob Herring reg = <0xffffee00 0x200>; 681*724ba675SRob Herring interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 682*724ba675SRob Herring pinctrl-names = "default"; 683*724ba675SRob Herring pinctrl-0 = <&pinctrl_dbgu>; 684*724ba675SRob Herring clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 685*724ba675SRob Herring clock-names = "usart"; 686*724ba675SRob Herring status = "disabled"; 687*724ba675SRob Herring }; 688*724ba675SRob Herring 689*724ba675SRob Herring usart0: serial@fff8c000 { 690*724ba675SRob Herring compatible = "atmel,at91sam9260-usart"; 691*724ba675SRob Herring reg = <0xfff8c000 0x200>; 692*724ba675SRob Herring atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 693*724ba675SRob Herring interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 694*724ba675SRob Herring atmel,use-dma-rx; 695*724ba675SRob Herring atmel,use-dma-tx; 696*724ba675SRob Herring pinctrl-names = "default"; 697*724ba675SRob Herring pinctrl-0 = <&pinctrl_usart0>; 698*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 699*724ba675SRob Herring clock-names = "usart"; 700*724ba675SRob Herring status = "disabled"; 701*724ba675SRob Herring }; 702*724ba675SRob Herring 703*724ba675SRob Herring usart1: serial@fff90000 { 704*724ba675SRob Herring compatible = "atmel,at91sam9260-usart"; 705*724ba675SRob Herring reg = <0xfff90000 0x200>; 706*724ba675SRob Herring atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 707*724ba675SRob Herring interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; 708*724ba675SRob Herring atmel,use-dma-rx; 709*724ba675SRob Herring atmel,use-dma-tx; 710*724ba675SRob Herring pinctrl-names = "default"; 711*724ba675SRob Herring pinctrl-0 = <&pinctrl_usart1>; 712*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 713*724ba675SRob Herring clock-names = "usart"; 714*724ba675SRob Herring status = "disabled"; 715*724ba675SRob Herring }; 716*724ba675SRob Herring 717*724ba675SRob Herring usart2: serial@fff94000 { 718*724ba675SRob Herring compatible = "atmel,at91sam9260-usart"; 719*724ba675SRob Herring reg = <0xfff94000 0x200>; 720*724ba675SRob Herring atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 721*724ba675SRob Herring interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; 722*724ba675SRob Herring atmel,use-dma-rx; 723*724ba675SRob Herring atmel,use-dma-tx; 724*724ba675SRob Herring pinctrl-names = "default"; 725*724ba675SRob Herring pinctrl-0 = <&pinctrl_usart2>; 726*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 727*724ba675SRob Herring clock-names = "usart"; 728*724ba675SRob Herring status = "disabled"; 729*724ba675SRob Herring }; 730*724ba675SRob Herring 731*724ba675SRob Herring usart3: serial@fff98000 { 732*724ba675SRob Herring compatible = "atmel,at91sam9260-usart"; 733*724ba675SRob Herring reg = <0xfff98000 0x200>; 734*724ba675SRob Herring atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 735*724ba675SRob Herring interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>; 736*724ba675SRob Herring atmel,use-dma-rx; 737*724ba675SRob Herring atmel,use-dma-tx; 738*724ba675SRob Herring pinctrl-names = "default"; 739*724ba675SRob Herring pinctrl-0 = <&pinctrl_usart3>; 740*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 741*724ba675SRob Herring clock-names = "usart"; 742*724ba675SRob Herring status = "disabled"; 743*724ba675SRob Herring }; 744*724ba675SRob Herring 745*724ba675SRob Herring macb0: ethernet@fffbc000 { 746*724ba675SRob Herring compatible = "cdns,at91sam9260-macb", "cdns,macb"; 747*724ba675SRob Herring reg = <0xfffbc000 0x100>; 748*724ba675SRob Herring interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; 749*724ba675SRob Herring pinctrl-names = "default"; 750*724ba675SRob Herring pinctrl-0 = <&pinctrl_macb_rmii>; 751*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_PERIPHERAL 25>; 752*724ba675SRob Herring clock-names = "hclk", "pclk"; 753*724ba675SRob Herring status = "disabled"; 754*724ba675SRob Herring }; 755*724ba675SRob Herring 756*724ba675SRob Herring trng@fffcc000 { 757*724ba675SRob Herring compatible = "atmel,at91sam9g45-trng"; 758*724ba675SRob Herring reg = <0xfffcc000 0x100>; 759*724ba675SRob Herring interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; 760*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 761*724ba675SRob Herring }; 762*724ba675SRob Herring 763*724ba675SRob Herring i2c0: i2c@fff84000 { 764*724ba675SRob Herring compatible = "atmel,at91sam9g10-i2c"; 765*724ba675SRob Herring reg = <0xfff84000 0x100>; 766*724ba675SRob Herring interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; 767*724ba675SRob Herring pinctrl-names = "default"; 768*724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c0>; 769*724ba675SRob Herring #address-cells = <1>; 770*724ba675SRob Herring #size-cells = <0>; 771*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 772*724ba675SRob Herring status = "disabled"; 773*724ba675SRob Herring }; 774*724ba675SRob Herring 775*724ba675SRob Herring i2c1: i2c@fff88000 { 776*724ba675SRob Herring compatible = "atmel,at91sam9g10-i2c"; 777*724ba675SRob Herring reg = <0xfff88000 0x100>; 778*724ba675SRob Herring interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; 779*724ba675SRob Herring pinctrl-names = "default"; 780*724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c1>; 781*724ba675SRob Herring #address-cells = <1>; 782*724ba675SRob Herring #size-cells = <0>; 783*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 784*724ba675SRob Herring status = "disabled"; 785*724ba675SRob Herring }; 786*724ba675SRob Herring 787*724ba675SRob Herring ssc0: ssc@fff9c000 { 788*724ba675SRob Herring compatible = "atmel,at91sam9g45-ssc"; 789*724ba675SRob Herring reg = <0xfff9c000 0x4000>; 790*724ba675SRob Herring interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; 791*724ba675SRob Herring pinctrl-names = "default"; 792*724ba675SRob Herring pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 793*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 794*724ba675SRob Herring clock-names = "pclk"; 795*724ba675SRob Herring status = "disabled"; 796*724ba675SRob Herring }; 797*724ba675SRob Herring 798*724ba675SRob Herring ssc1: ssc@fffa0000 { 799*724ba675SRob Herring compatible = "atmel,at91sam9g45-ssc"; 800*724ba675SRob Herring reg = <0xfffa0000 0x4000>; 801*724ba675SRob Herring interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; 802*724ba675SRob Herring pinctrl-names = "default"; 803*724ba675SRob Herring pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 804*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 805*724ba675SRob Herring clock-names = "pclk"; 806*724ba675SRob Herring status = "disabled"; 807*724ba675SRob Herring }; 808*724ba675SRob Herring 809*724ba675SRob Herring ac97: sound@fffac000 { 810*724ba675SRob Herring compatible = "atmel,at91sam9263-ac97c"; 811*724ba675SRob Herring reg = <0xfffac000 0x4000>; 812*724ba675SRob Herring interrupts = <24 IRQ_TYPE_LEVEL_HIGH 4>; 813*724ba675SRob Herring pinctrl-names = "default"; 814*724ba675SRob Herring pinctrl-0 = <&pinctrl_ac97>; 815*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 816*724ba675SRob Herring clock-names = "ac97_clk"; 817*724ba675SRob Herring status = "disabled"; 818*724ba675SRob Herring }; 819*724ba675SRob Herring 820*724ba675SRob Herring adc0: adc@fffb0000 { 821*724ba675SRob Herring compatible = "atmel,at91sam9g45-adc"; 822*724ba675SRob Herring reg = <0xfffb0000 0x100>; 823*724ba675SRob Herring interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 824*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&adc_op_clk>; 825*724ba675SRob Herring clock-names = "adc_clk", "adc_op_clk"; 826*724ba675SRob Herring atmel,adc-channels-used = <0xff>; 827*724ba675SRob Herring atmel,adc-vref = <3300>; 828*724ba675SRob Herring atmel,adc-startup-time = <40>; 829*724ba675SRob Herring }; 830*724ba675SRob Herring 831*724ba675SRob Herring isi@fffb4000 { 832*724ba675SRob Herring compatible = "atmel,at91sam9g45-isi"; 833*724ba675SRob Herring reg = <0xfffb4000 0x4000>; 834*724ba675SRob Herring interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>; 835*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; 836*724ba675SRob Herring clock-names = "isi_clk"; 837*724ba675SRob Herring status = "disabled"; 838*724ba675SRob Herring port { 839*724ba675SRob Herring #address-cells = <1>; 840*724ba675SRob Herring #size-cells = <0>; 841*724ba675SRob Herring }; 842*724ba675SRob Herring }; 843*724ba675SRob Herring 844*724ba675SRob Herring pwm0: pwm@fffb8000 { 845*724ba675SRob Herring compatible = "atmel,at91sam9rl-pwm"; 846*724ba675SRob Herring reg = <0xfffb8000 0x300>; 847*724ba675SRob Herring interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; 848*724ba675SRob Herring #pwm-cells = <3>; 849*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 850*724ba675SRob Herring status = "disabled"; 851*724ba675SRob Herring }; 852*724ba675SRob Herring 853*724ba675SRob Herring mmc0: mmc@fff80000 { 854*724ba675SRob Herring compatible = "atmel,hsmci"; 855*724ba675SRob Herring reg = <0xfff80000 0x600>; 856*724ba675SRob Herring interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 857*724ba675SRob Herring dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; 858*724ba675SRob Herring dma-names = "rxtx"; 859*724ba675SRob Herring #address-cells = <1>; 860*724ba675SRob Herring #size-cells = <0>; 861*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 862*724ba675SRob Herring clock-names = "mci_clk"; 863*724ba675SRob Herring status = "disabled"; 864*724ba675SRob Herring }; 865*724ba675SRob Herring 866*724ba675SRob Herring mmc1: mmc@fffd0000 { 867*724ba675SRob Herring compatible = "atmel,hsmci"; 868*724ba675SRob Herring reg = <0xfffd0000 0x600>; 869*724ba675SRob Herring interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; 870*724ba675SRob Herring dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; 871*724ba675SRob Herring dma-names = "rxtx"; 872*724ba675SRob Herring #address-cells = <1>; 873*724ba675SRob Herring #size-cells = <0>; 874*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 875*724ba675SRob Herring clock-names = "mci_clk"; 876*724ba675SRob Herring status = "disabled"; 877*724ba675SRob Herring }; 878*724ba675SRob Herring 879*724ba675SRob Herring watchdog@fffffd40 { 880*724ba675SRob Herring compatible = "atmel,at91sam9260-wdt"; 881*724ba675SRob Herring reg = <0xfffffd40 0x10>; 882*724ba675SRob Herring interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 883*724ba675SRob Herring clocks = <&clk32k>; 884*724ba675SRob Herring atmel,watchdog-type = "hardware"; 885*724ba675SRob Herring atmel,reset-type = "all"; 886*724ba675SRob Herring atmel,dbg-halt; 887*724ba675SRob Herring status = "disabled"; 888*724ba675SRob Herring }; 889*724ba675SRob Herring 890*724ba675SRob Herring spi0: spi@fffa4000 { 891*724ba675SRob Herring #address-cells = <1>; 892*724ba675SRob Herring #size-cells = <0>; 893*724ba675SRob Herring compatible = "atmel,at91rm9200-spi"; 894*724ba675SRob Herring reg = <0xfffa4000 0x200>; 895*724ba675SRob Herring interrupts = <14 4 3>; 896*724ba675SRob Herring pinctrl-names = "default"; 897*724ba675SRob Herring pinctrl-0 = <&pinctrl_spi0>; 898*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 899*724ba675SRob Herring clock-names = "spi_clk"; 900*724ba675SRob Herring status = "disabled"; 901*724ba675SRob Herring }; 902*724ba675SRob Herring 903*724ba675SRob Herring spi1: spi@fffa8000 { 904*724ba675SRob Herring #address-cells = <1>; 905*724ba675SRob Herring #size-cells = <0>; 906*724ba675SRob Herring compatible = "atmel,at91rm9200-spi"; 907*724ba675SRob Herring reg = <0xfffa8000 0x200>; 908*724ba675SRob Herring interrupts = <15 4 3>; 909*724ba675SRob Herring pinctrl-names = "default"; 910*724ba675SRob Herring pinctrl-0 = <&pinctrl_spi1>; 911*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 912*724ba675SRob Herring clock-names = "spi_clk"; 913*724ba675SRob Herring status = "disabled"; 914*724ba675SRob Herring }; 915*724ba675SRob Herring 916*724ba675SRob Herring usb2: gadget@fff78000 { 917*724ba675SRob Herring compatible = "atmel,at91sam9g45-udc"; 918*724ba675SRob Herring reg = <0x00600000 0x80000 919*724ba675SRob Herring 0xfff78000 0x400>; 920*724ba675SRob Herring interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; 921*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 922*724ba675SRob Herring clock-names = "pclk", "hclk"; 923*724ba675SRob Herring status = "disabled"; 924*724ba675SRob Herring }; 925*724ba675SRob Herring 926*724ba675SRob Herring clk32k: clock-controller@fffffd50 { 927*724ba675SRob Herring compatible = "atmel,at91sam9x5-sckc"; 928*724ba675SRob Herring reg = <0xfffffd50 0x4>; 929*724ba675SRob Herring clocks = <&slow_xtal>; 930*724ba675SRob Herring #clock-cells = <0>; 931*724ba675SRob Herring }; 932*724ba675SRob Herring 933*724ba675SRob Herring rtc@fffffd20 { 934*724ba675SRob Herring compatible = "atmel,at91sam9260-rtt"; 935*724ba675SRob Herring reg = <0xfffffd20 0x10>; 936*724ba675SRob Herring interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 937*724ba675SRob Herring clocks = <&clk32k>; 938*724ba675SRob Herring status = "disabled"; 939*724ba675SRob Herring }; 940*724ba675SRob Herring 941*724ba675SRob Herring rtc@fffffdb0 { 942*724ba675SRob Herring compatible = "atmel,at91rm9200-rtc"; 943*724ba675SRob Herring reg = <0xfffffdb0 0x30>; 944*724ba675SRob Herring interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 945*724ba675SRob Herring clocks = <&clk32k>; 946*724ba675SRob Herring status = "disabled"; 947*724ba675SRob Herring }; 948*724ba675SRob Herring 949*724ba675SRob Herring gpbr: syscon@fffffd60 { 950*724ba675SRob Herring compatible = "atmel,at91sam9260-gpbr", "syscon"; 951*724ba675SRob Herring reg = <0xfffffd60 0x10>; 952*724ba675SRob Herring status = "disabled"; 953*724ba675SRob Herring }; 954*724ba675SRob Herring }; 955*724ba675SRob Herring 956*724ba675SRob Herring fb0: fb@500000 { 957*724ba675SRob Herring compatible = "atmel,at91sam9g45-lcdc"; 958*724ba675SRob Herring reg = <0x00500000 0x1000>; 959*724ba675SRob Herring interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; 960*724ba675SRob Herring pinctrl-names = "default"; 961*724ba675SRob Herring pinctrl-0 = <&pinctrl_fb>; 962*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>; 963*724ba675SRob Herring clock-names = "hclk", "lcdc_clk"; 964*724ba675SRob Herring status = "disabled"; 965*724ba675SRob Herring }; 966*724ba675SRob Herring 967*724ba675SRob Herring usb0: ohci@700000 { 968*724ba675SRob Herring compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 969*724ba675SRob Herring reg = <0x00700000 0x100000>; 970*724ba675SRob Herring interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 971*724ba675SRob Herring clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; 972*724ba675SRob Herring clock-names = "ohci_clk", "hclk", "uhpck"; 973*724ba675SRob Herring status = "disabled"; 974*724ba675SRob Herring }; 975*724ba675SRob Herring 976*724ba675SRob Herring usb1: ehci@800000 { 977*724ba675SRob Herring compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 978*724ba675SRob Herring reg = <0x00800000 0x100000>; 979*724ba675SRob Herring interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 980*724ba675SRob Herring clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; 981*724ba675SRob Herring clock-names = "usb_clk", "ehci_clk"; 982*724ba675SRob Herring status = "disabled"; 983*724ba675SRob Herring }; 984*724ba675SRob Herring 985*724ba675SRob Herring ebi: ebi@10000000 { 986*724ba675SRob Herring compatible = "atmel,at91sam9g45-ebi"; 987*724ba675SRob Herring #address-cells = <2>; 988*724ba675SRob Herring #size-cells = <1>; 989*724ba675SRob Herring atmel,smc = <&smc>; 990*724ba675SRob Herring atmel,matrix = <&matrix>; 991*724ba675SRob Herring reg = <0x10000000 0x80000000>; 992*724ba675SRob Herring ranges = <0x0 0x0 0x10000000 0x10000000 993*724ba675SRob Herring 0x1 0x0 0x20000000 0x10000000 994*724ba675SRob Herring 0x2 0x0 0x30000000 0x10000000 995*724ba675SRob Herring 0x3 0x0 0x40000000 0x10000000 996*724ba675SRob Herring 0x4 0x0 0x50000000 0x10000000 997*724ba675SRob Herring 0x5 0x0 0x60000000 0x10000000>; 998*724ba675SRob Herring clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 999*724ba675SRob Herring status = "disabled"; 1000*724ba675SRob Herring 1001*724ba675SRob Herring nand_controller: nand-controller { 1002*724ba675SRob Herring compatible = "atmel,at91sam9g45-nand-controller"; 1003*724ba675SRob Herring #address-cells = <2>; 1004*724ba675SRob Herring #size-cells = <1>; 1005*724ba675SRob Herring ranges; 1006*724ba675SRob Herring status = "disabled"; 1007*724ba675SRob Herring }; 1008*724ba675SRob Herring }; 1009*724ba675SRob Herring }; 1010*724ba675SRob Herring 1011*724ba675SRob Herring i2c-gpio-0 { 1012*724ba675SRob Herring compatible = "i2c-gpio"; 1013*724ba675SRob Herring gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */ 1014*724ba675SRob Herring &pioA 21 GPIO_ACTIVE_HIGH /* scl */ 1015*724ba675SRob Herring >; 1016*724ba675SRob Herring i2c-gpio,sda-open-drain; 1017*724ba675SRob Herring i2c-gpio,scl-open-drain; 1018*724ba675SRob Herring i2c-gpio,delay-us = <5>; /* ~100 kHz */ 1019*724ba675SRob Herring #address-cells = <1>; 1020*724ba675SRob Herring #size-cells = <0>; 1021*724ba675SRob Herring status = "disabled"; 1022*724ba675SRob Herring }; 1023*724ba675SRob Herring}; 1024