1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring/* 3*724ba675SRob Herring * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 6*724ba675SRob Herring */ 7*724ba675SRob Herring 8*724ba675SRob Herring#include "at91sam9260.dtsi" 9*724ba675SRob Herring 10*724ba675SRob Herring/ { 11*724ba675SRob Herring model = "Atmel AT91SAM9G20 family SoC"; 12*724ba675SRob Herring compatible = "atmel,at91sam9g20"; 13*724ba675SRob Herring 14*724ba675SRob Herring memory@20000000 { 15*724ba675SRob Herring reg = <0x20000000 0x08000000>; 16*724ba675SRob Herring }; 17*724ba675SRob Herring 18*724ba675SRob Herring sram0: sram@2ff000 { 19*724ba675SRob Herring status = "disabled"; 20*724ba675SRob Herring }; 21*724ba675SRob Herring 22*724ba675SRob Herring sram1: sram@2fc000 { 23*724ba675SRob Herring compatible = "mmio-sram"; 24*724ba675SRob Herring reg = <0x002fc000 0x8000>; 25*724ba675SRob Herring #address-cells = <1>; 26*724ba675SRob Herring #size-cells = <1>; 27*724ba675SRob Herring ranges = <0 0x002fc000 0x8000>; 28*724ba675SRob Herring }; 29*724ba675SRob Herring 30*724ba675SRob Herring ahb { 31*724ba675SRob Herring apb { 32*724ba675SRob Herring i2c0: i2c@fffac000 { 33*724ba675SRob Herring compatible = "atmel,at91sam9g20-i2c"; 34*724ba675SRob Herring }; 35*724ba675SRob Herring 36*724ba675SRob Herring ssc0: ssc@fffbc000 { 37*724ba675SRob Herring compatible = "atmel,at91sam9rl-ssc"; 38*724ba675SRob Herring }; 39*724ba675SRob Herring 40*724ba675SRob Herring adc0: adc@fffe0000 { 41*724ba675SRob Herring atmel,adc-startup-time = <40>; 42*724ba675SRob Herring }; 43*724ba675SRob Herring 44*724ba675SRob Herring pmc: clock-controller@fffffc00 { 45*724ba675SRob Herring compatible = "atmel,at91sam9g20-pmc", "atmel,at91sam9260-pmc", "syscon"; 46*724ba675SRob Herring }; 47*724ba675SRob Herring }; 48*724ba675SRob Herring }; 49*724ba675SRob Herring}; 50