1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (c) 2017-2018 MediaTek Inc. 4*724ba675SRob Herring * Author: John Crispin <john@phrozen.org> 5*724ba675SRob Herring * Sean Wang <sean.wang@mediatek.com> 6*724ba675SRob Herring * Ryder Lee <ryder.lee@mediatek.com> 7*724ba675SRob Herring * 8*724ba675SRob Herring */ 9*724ba675SRob Herring 10*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 11*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 12*724ba675SRob Herring#include <dt-bindings/clock/mt2701-clk.h> 13*724ba675SRob Herring#include <dt-bindings/pinctrl/mt7623-pinfunc.h> 14*724ba675SRob Herring#include <dt-bindings/power/mt2701-power.h> 15*724ba675SRob Herring#include <dt-bindings/gpio/gpio.h> 16*724ba675SRob Herring#include <dt-bindings/phy/phy.h> 17*724ba675SRob Herring#include <dt-bindings/reset/mt2701-resets.h> 18*724ba675SRob Herring#include <dt-bindings/thermal/thermal.h> 19*724ba675SRob Herring 20*724ba675SRob Herring/ { 21*724ba675SRob Herring compatible = "mediatek,mt7623"; 22*724ba675SRob Herring interrupt-parent = <&sysirq>; 23*724ba675SRob Herring #address-cells = <2>; 24*724ba675SRob Herring #size-cells = <2>; 25*724ba675SRob Herring 26*724ba675SRob Herring cpu_opp_table: opp-table { 27*724ba675SRob Herring compatible = "operating-points-v2"; 28*724ba675SRob Herring opp-shared; 29*724ba675SRob Herring 30*724ba675SRob Herring opp-98000000 { 31*724ba675SRob Herring opp-hz = /bits/ 64 <98000000>; 32*724ba675SRob Herring opp-microvolt = <1050000>; 33*724ba675SRob Herring }; 34*724ba675SRob Herring 35*724ba675SRob Herring opp-198000000 { 36*724ba675SRob Herring opp-hz = /bits/ 64 <198000000>; 37*724ba675SRob Herring opp-microvolt = <1050000>; 38*724ba675SRob Herring }; 39*724ba675SRob Herring 40*724ba675SRob Herring opp-398000000 { 41*724ba675SRob Herring opp-hz = /bits/ 64 <398000000>; 42*724ba675SRob Herring opp-microvolt = <1050000>; 43*724ba675SRob Herring }; 44*724ba675SRob Herring 45*724ba675SRob Herring opp-598000000 { 46*724ba675SRob Herring opp-hz = /bits/ 64 <598000000>; 47*724ba675SRob Herring opp-microvolt = <1050000>; 48*724ba675SRob Herring }; 49*724ba675SRob Herring 50*724ba675SRob Herring opp-747500000 { 51*724ba675SRob Herring opp-hz = /bits/ 64 <747500000>; 52*724ba675SRob Herring opp-microvolt = <1050000>; 53*724ba675SRob Herring }; 54*724ba675SRob Herring 55*724ba675SRob Herring opp-1040000000 { 56*724ba675SRob Herring opp-hz = /bits/ 64 <1040000000>; 57*724ba675SRob Herring opp-microvolt = <1150000>; 58*724ba675SRob Herring }; 59*724ba675SRob Herring 60*724ba675SRob Herring opp-1196000000 { 61*724ba675SRob Herring opp-hz = /bits/ 64 <1196000000>; 62*724ba675SRob Herring opp-microvolt = <1200000>; 63*724ba675SRob Herring }; 64*724ba675SRob Herring 65*724ba675SRob Herring opp-1300000000 { 66*724ba675SRob Herring opp-hz = /bits/ 64 <1300000000>; 67*724ba675SRob Herring opp-microvolt = <1300000>; 68*724ba675SRob Herring }; 69*724ba675SRob Herring }; 70*724ba675SRob Herring 71*724ba675SRob Herring cpus { 72*724ba675SRob Herring #address-cells = <1>; 73*724ba675SRob Herring #size-cells = <0>; 74*724ba675SRob Herring enable-method = "mediatek,mt6589-smp"; 75*724ba675SRob Herring 76*724ba675SRob Herring cpu0: cpu@0 { 77*724ba675SRob Herring device_type = "cpu"; 78*724ba675SRob Herring compatible = "arm,cortex-a7"; 79*724ba675SRob Herring reg = <0x0>; 80*724ba675SRob Herring clocks = <&infracfg CLK_INFRA_CPUSEL>, 81*724ba675SRob Herring <&apmixedsys CLK_APMIXED_MAINPLL>; 82*724ba675SRob Herring clock-names = "cpu", "intermediate"; 83*724ba675SRob Herring operating-points-v2 = <&cpu_opp_table>; 84*724ba675SRob Herring #cooling-cells = <2>; 85*724ba675SRob Herring clock-frequency = <1300000000>; 86*724ba675SRob Herring }; 87*724ba675SRob Herring 88*724ba675SRob Herring cpu1: cpu@1 { 89*724ba675SRob Herring device_type = "cpu"; 90*724ba675SRob Herring compatible = "arm,cortex-a7"; 91*724ba675SRob Herring reg = <0x1>; 92*724ba675SRob Herring clocks = <&infracfg CLK_INFRA_CPUSEL>, 93*724ba675SRob Herring <&apmixedsys CLK_APMIXED_MAINPLL>; 94*724ba675SRob Herring clock-names = "cpu", "intermediate"; 95*724ba675SRob Herring operating-points-v2 = <&cpu_opp_table>; 96*724ba675SRob Herring #cooling-cells = <2>; 97*724ba675SRob Herring clock-frequency = <1300000000>; 98*724ba675SRob Herring }; 99*724ba675SRob Herring 100*724ba675SRob Herring cpu2: cpu@2 { 101*724ba675SRob Herring device_type = "cpu"; 102*724ba675SRob Herring compatible = "arm,cortex-a7"; 103*724ba675SRob Herring reg = <0x2>; 104*724ba675SRob Herring clocks = <&infracfg CLK_INFRA_CPUSEL>, 105*724ba675SRob Herring <&apmixedsys CLK_APMIXED_MAINPLL>; 106*724ba675SRob Herring clock-names = "cpu", "intermediate"; 107*724ba675SRob Herring operating-points-v2 = <&cpu_opp_table>; 108*724ba675SRob Herring #cooling-cells = <2>; 109*724ba675SRob Herring clock-frequency = <1300000000>; 110*724ba675SRob Herring }; 111*724ba675SRob Herring 112*724ba675SRob Herring cpu3: cpu@3 { 113*724ba675SRob Herring device_type = "cpu"; 114*724ba675SRob Herring compatible = "arm,cortex-a7"; 115*724ba675SRob Herring reg = <0x3>; 116*724ba675SRob Herring clocks = <&infracfg CLK_INFRA_CPUSEL>, 117*724ba675SRob Herring <&apmixedsys CLK_APMIXED_MAINPLL>; 118*724ba675SRob Herring clock-names = "cpu", "intermediate"; 119*724ba675SRob Herring operating-points-v2 = <&cpu_opp_table>; 120*724ba675SRob Herring #cooling-cells = <2>; 121*724ba675SRob Herring clock-frequency = <1300000000>; 122*724ba675SRob Herring }; 123*724ba675SRob Herring }; 124*724ba675SRob Herring 125*724ba675SRob Herring pmu { 126*724ba675SRob Herring compatible = "arm,cortex-a7-pmu"; 127*724ba675SRob Herring interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>, 128*724ba675SRob Herring <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>, 129*724ba675SRob Herring <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>, 130*724ba675SRob Herring <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>; 131*724ba675SRob Herring interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 132*724ba675SRob Herring }; 133*724ba675SRob Herring 134*724ba675SRob Herring system_clk: dummy13m { 135*724ba675SRob Herring compatible = "fixed-clock"; 136*724ba675SRob Herring clock-frequency = <13000000>; 137*724ba675SRob Herring #clock-cells = <0>; 138*724ba675SRob Herring }; 139*724ba675SRob Herring 140*724ba675SRob Herring rtc32k: oscillator-1 { 141*724ba675SRob Herring compatible = "fixed-clock"; 142*724ba675SRob Herring #clock-cells = <0>; 143*724ba675SRob Herring clock-frequency = <32000>; 144*724ba675SRob Herring clock-output-names = "rtc32k"; 145*724ba675SRob Herring }; 146*724ba675SRob Herring 147*724ba675SRob Herring clk26m: oscillator-0 { 148*724ba675SRob Herring compatible = "fixed-clock"; 149*724ba675SRob Herring #clock-cells = <0>; 150*724ba675SRob Herring clock-frequency = <26000000>; 151*724ba675SRob Herring clock-output-names = "clk26m"; 152*724ba675SRob Herring }; 153*724ba675SRob Herring 154*724ba675SRob Herring thermal-zones { 155*724ba675SRob Herring cpu_thermal: cpu-thermal { 156*724ba675SRob Herring polling-delay-passive = <1000>; 157*724ba675SRob Herring polling-delay = <1000>; 158*724ba675SRob Herring 159*724ba675SRob Herring thermal-sensors = <&thermal 0>; 160*724ba675SRob Herring 161*724ba675SRob Herring trips { 162*724ba675SRob Herring cpu_passive: cpu-passive { 163*724ba675SRob Herring temperature = <57000>; 164*724ba675SRob Herring hysteresis = <2000>; 165*724ba675SRob Herring type = "passive"; 166*724ba675SRob Herring }; 167*724ba675SRob Herring 168*724ba675SRob Herring cpu_active: cpu-active { 169*724ba675SRob Herring temperature = <67000>; 170*724ba675SRob Herring hysteresis = <2000>; 171*724ba675SRob Herring type = "active"; 172*724ba675SRob Herring }; 173*724ba675SRob Herring 174*724ba675SRob Herring cpu_hot: cpu-hot { 175*724ba675SRob Herring temperature = <87000>; 176*724ba675SRob Herring hysteresis = <2000>; 177*724ba675SRob Herring type = "hot"; 178*724ba675SRob Herring }; 179*724ba675SRob Herring 180*724ba675SRob Herring cpu-crit { 181*724ba675SRob Herring temperature = <107000>; 182*724ba675SRob Herring hysteresis = <2000>; 183*724ba675SRob Herring type = "critical"; 184*724ba675SRob Herring }; 185*724ba675SRob Herring }; 186*724ba675SRob Herring 187*724ba675SRob Herring cooling-maps { 188*724ba675SRob Herring map0 { 189*724ba675SRob Herring trip = <&cpu_passive>; 190*724ba675SRob Herring cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 191*724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 192*724ba675SRob Herring <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 193*724ba675SRob Herring <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 194*724ba675SRob Herring }; 195*724ba675SRob Herring 196*724ba675SRob Herring map1 { 197*724ba675SRob Herring trip = <&cpu_active>; 198*724ba675SRob Herring cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 199*724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 200*724ba675SRob Herring <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 201*724ba675SRob Herring <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 202*724ba675SRob Herring }; 203*724ba675SRob Herring 204*724ba675SRob Herring map2 { 205*724ba675SRob Herring trip = <&cpu_hot>; 206*724ba675SRob Herring cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 207*724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 208*724ba675SRob Herring <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 209*724ba675SRob Herring <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 210*724ba675SRob Herring }; 211*724ba675SRob Herring }; 212*724ba675SRob Herring }; 213*724ba675SRob Herring }; 214*724ba675SRob Herring 215*724ba675SRob Herring timer { 216*724ba675SRob Herring compatible = "arm,armv7-timer"; 217*724ba675SRob Herring interrupt-parent = <&gic>; 218*724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 219*724ba675SRob Herring <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 220*724ba675SRob Herring <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 221*724ba675SRob Herring <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 222*724ba675SRob Herring clock-frequency = <13000000>; 223*724ba675SRob Herring arm,cpu-registers-not-fw-configured; 224*724ba675SRob Herring }; 225*724ba675SRob Herring 226*724ba675SRob Herring topckgen: syscon@10000000 { 227*724ba675SRob Herring compatible = "mediatek,mt7623-topckgen", 228*724ba675SRob Herring "mediatek,mt2701-topckgen", 229*724ba675SRob Herring "syscon"; 230*724ba675SRob Herring reg = <0 0x10000000 0 0x1000>; 231*724ba675SRob Herring #clock-cells = <1>; 232*724ba675SRob Herring }; 233*724ba675SRob Herring 234*724ba675SRob Herring infracfg: syscon@10001000 { 235*724ba675SRob Herring compatible = "mediatek,mt7623-infracfg", 236*724ba675SRob Herring "mediatek,mt2701-infracfg", 237*724ba675SRob Herring "syscon"; 238*724ba675SRob Herring reg = <0 0x10001000 0 0x1000>; 239*724ba675SRob Herring #clock-cells = <1>; 240*724ba675SRob Herring #reset-cells = <1>; 241*724ba675SRob Herring }; 242*724ba675SRob Herring 243*724ba675SRob Herring pericfg: syscon@10003000 { 244*724ba675SRob Herring compatible = "mediatek,mt7623-pericfg", 245*724ba675SRob Herring "mediatek,mt2701-pericfg", 246*724ba675SRob Herring "syscon"; 247*724ba675SRob Herring reg = <0 0x10003000 0 0x1000>; 248*724ba675SRob Herring #clock-cells = <1>; 249*724ba675SRob Herring #reset-cells = <1>; 250*724ba675SRob Herring }; 251*724ba675SRob Herring 252*724ba675SRob Herring pio: pinctrl@10005000 { 253*724ba675SRob Herring compatible = "mediatek,mt7623-pinctrl"; 254*724ba675SRob Herring reg = <0 0x1000b000 0 0x1000>; 255*724ba675SRob Herring mediatek,pctl-regmap = <&syscfg_pctl_a>; 256*724ba675SRob Herring gpio-controller; 257*724ba675SRob Herring #gpio-cells = <2>; 258*724ba675SRob Herring interrupt-controller; 259*724ba675SRob Herring interrupt-parent = <&gic>; 260*724ba675SRob Herring #interrupt-cells = <2>; 261*724ba675SRob Herring interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 262*724ba675SRob Herring <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 263*724ba675SRob Herring }; 264*724ba675SRob Herring 265*724ba675SRob Herring syscfg_pctl_a: syscfg@10005000 { 266*724ba675SRob Herring compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon"; 267*724ba675SRob Herring reg = <0 0x10005000 0 0x1000>; 268*724ba675SRob Herring }; 269*724ba675SRob Herring 270*724ba675SRob Herring scpsys: power-controller@10006000 { 271*724ba675SRob Herring compatible = "mediatek,mt7623-scpsys", 272*724ba675SRob Herring "mediatek,mt2701-scpsys", 273*724ba675SRob Herring "syscon"; 274*724ba675SRob Herring #power-domain-cells = <1>; 275*724ba675SRob Herring reg = <0 0x10006000 0 0x1000>; 276*724ba675SRob Herring infracfg = <&infracfg>; 277*724ba675SRob Herring clocks = <&topckgen CLK_TOP_MM_SEL>, 278*724ba675SRob Herring <&topckgen CLK_TOP_MFG_SEL>, 279*724ba675SRob Herring <&topckgen CLK_TOP_ETHIF_SEL>; 280*724ba675SRob Herring clock-names = "mm", "mfg", "ethif"; 281*724ba675SRob Herring }; 282*724ba675SRob Herring 283*724ba675SRob Herring watchdog: watchdog@10007000 { 284*724ba675SRob Herring compatible = "mediatek,mt7623-wdt", 285*724ba675SRob Herring "mediatek,mt6589-wdt"; 286*724ba675SRob Herring reg = <0 0x10007000 0 0x100>; 287*724ba675SRob Herring }; 288*724ba675SRob Herring 289*724ba675SRob Herring timer: timer@10008000 { 290*724ba675SRob Herring compatible = "mediatek,mt7623-timer", 291*724ba675SRob Herring "mediatek,mt6577-timer"; 292*724ba675SRob Herring reg = <0 0x10008000 0 0x80>; 293*724ba675SRob Herring interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>; 294*724ba675SRob Herring clocks = <&system_clk>, <&rtc32k>; 295*724ba675SRob Herring clock-names = "system-clk", "rtc-clk"; 296*724ba675SRob Herring }; 297*724ba675SRob Herring 298*724ba675SRob Herring pwrap: pwrap@1000d000 { 299*724ba675SRob Herring compatible = "mediatek,mt7623-pwrap", 300*724ba675SRob Herring "mediatek,mt2701-pwrap"; 301*724ba675SRob Herring reg = <0 0x1000d000 0 0x1000>; 302*724ba675SRob Herring reg-names = "pwrap"; 303*724ba675SRob Herring interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 304*724ba675SRob Herring resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>; 305*724ba675SRob Herring reset-names = "pwrap"; 306*724ba675SRob Herring clocks = <&infracfg CLK_INFRA_PMICSPI>, 307*724ba675SRob Herring <&infracfg CLK_INFRA_PMICWRAP>; 308*724ba675SRob Herring clock-names = "spi", "wrap"; 309*724ba675SRob Herring }; 310*724ba675SRob Herring 311*724ba675SRob Herring cir: cir@10013000 { 312*724ba675SRob Herring compatible = "mediatek,mt7623-cir"; 313*724ba675SRob Herring reg = <0 0x10013000 0 0x1000>; 314*724ba675SRob Herring interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 315*724ba675SRob Herring clocks = <&infracfg CLK_INFRA_IRRX>; 316*724ba675SRob Herring clock-names = "clk"; 317*724ba675SRob Herring status = "disabled"; 318*724ba675SRob Herring }; 319*724ba675SRob Herring 320*724ba675SRob Herring sysirq: interrupt-controller@10200100 { 321*724ba675SRob Herring compatible = "mediatek,mt7623-sysirq", 322*724ba675SRob Herring "mediatek,mt6577-sysirq"; 323*724ba675SRob Herring interrupt-controller; 324*724ba675SRob Herring #interrupt-cells = <3>; 325*724ba675SRob Herring interrupt-parent = <&gic>; 326*724ba675SRob Herring reg = <0 0x10200100 0 0x1c>; 327*724ba675SRob Herring }; 328*724ba675SRob Herring 329*724ba675SRob Herring efuse: efuse@10206000 { 330*724ba675SRob Herring compatible = "mediatek,mt7623-efuse", 331*724ba675SRob Herring "mediatek,mt8173-efuse"; 332*724ba675SRob Herring reg = <0 0x10206000 0 0x1000>; 333*724ba675SRob Herring #address-cells = <1>; 334*724ba675SRob Herring #size-cells = <1>; 335*724ba675SRob Herring thermal_calibration_data: calib@424 { 336*724ba675SRob Herring reg = <0x424 0xc>; 337*724ba675SRob Herring }; 338*724ba675SRob Herring }; 339*724ba675SRob Herring 340*724ba675SRob Herring apmixedsys: syscon@10209000 { 341*724ba675SRob Herring compatible = "mediatek,mt7623-apmixedsys", 342*724ba675SRob Herring "mediatek,mt2701-apmixedsys", 343*724ba675SRob Herring "syscon"; 344*724ba675SRob Herring reg = <0 0x10209000 0 0x1000>; 345*724ba675SRob Herring #clock-cells = <1>; 346*724ba675SRob Herring }; 347*724ba675SRob Herring 348*724ba675SRob Herring rng: rng@1020f000 { 349*724ba675SRob Herring compatible = "mediatek,mt7623-rng"; 350*724ba675SRob Herring reg = <0 0x1020f000 0 0x1000>; 351*724ba675SRob Herring clocks = <&infracfg CLK_INFRA_TRNG>; 352*724ba675SRob Herring clock-names = "rng"; 353*724ba675SRob Herring }; 354*724ba675SRob Herring 355*724ba675SRob Herring gic: interrupt-controller@10211000 { 356*724ba675SRob Herring compatible = "arm,cortex-a7-gic"; 357*724ba675SRob Herring interrupt-controller; 358*724ba675SRob Herring #interrupt-cells = <3>; 359*724ba675SRob Herring interrupt-parent = <&gic>; 360*724ba675SRob Herring reg = <0 0x10211000 0 0x1000>, 361*724ba675SRob Herring <0 0x10212000 0 0x2000>, 362*724ba675SRob Herring <0 0x10214000 0 0x2000>, 363*724ba675SRob Herring <0 0x10216000 0 0x2000>; 364*724ba675SRob Herring }; 365*724ba675SRob Herring 366*724ba675SRob Herring auxadc: adc@11001000 { 367*724ba675SRob Herring compatible = "mediatek,mt7623-auxadc", 368*724ba675SRob Herring "mediatek,mt2701-auxadc"; 369*724ba675SRob Herring reg = <0 0x11001000 0 0x1000>; 370*724ba675SRob Herring clocks = <&pericfg CLK_PERI_AUXADC>; 371*724ba675SRob Herring clock-names = "main"; 372*724ba675SRob Herring #io-channel-cells = <1>; 373*724ba675SRob Herring }; 374*724ba675SRob Herring 375*724ba675SRob Herring uart0: serial@11002000 { 376*724ba675SRob Herring compatible = "mediatek,mt7623-uart", 377*724ba675SRob Herring "mediatek,mt6577-uart"; 378*724ba675SRob Herring reg = <0 0x11002000 0 0x400>; 379*724ba675SRob Herring interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; 380*724ba675SRob Herring clocks = <&pericfg CLK_PERI_UART0_SEL>, 381*724ba675SRob Herring <&pericfg CLK_PERI_UART0>; 382*724ba675SRob Herring clock-names = "baud", "bus"; 383*724ba675SRob Herring status = "disabled"; 384*724ba675SRob Herring }; 385*724ba675SRob Herring 386*724ba675SRob Herring uart1: serial@11003000 { 387*724ba675SRob Herring compatible = "mediatek,mt7623-uart", 388*724ba675SRob Herring "mediatek,mt6577-uart"; 389*724ba675SRob Herring reg = <0 0x11003000 0 0x400>; 390*724ba675SRob Herring interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 391*724ba675SRob Herring clocks = <&pericfg CLK_PERI_UART1_SEL>, 392*724ba675SRob Herring <&pericfg CLK_PERI_UART1>; 393*724ba675SRob Herring clock-names = "baud", "bus"; 394*724ba675SRob Herring status = "disabled"; 395*724ba675SRob Herring }; 396*724ba675SRob Herring 397*724ba675SRob Herring uart2: serial@11004000 { 398*724ba675SRob Herring compatible = "mediatek,mt7623-uart", 399*724ba675SRob Herring "mediatek,mt6577-uart"; 400*724ba675SRob Herring reg = <0 0x11004000 0 0x400>; 401*724ba675SRob Herring interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; 402*724ba675SRob Herring clocks = <&pericfg CLK_PERI_UART2_SEL>, 403*724ba675SRob Herring <&pericfg CLK_PERI_UART2>; 404*724ba675SRob Herring clock-names = "baud", "bus"; 405*724ba675SRob Herring status = "disabled"; 406*724ba675SRob Herring }; 407*724ba675SRob Herring 408*724ba675SRob Herring uart3: serial@11005000 { 409*724ba675SRob Herring compatible = "mediatek,mt7623-uart", 410*724ba675SRob Herring "mediatek,mt6577-uart"; 411*724ba675SRob Herring reg = <0 0x11005000 0 0x400>; 412*724ba675SRob Herring interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; 413*724ba675SRob Herring clocks = <&pericfg CLK_PERI_UART3_SEL>, 414*724ba675SRob Herring <&pericfg CLK_PERI_UART3>; 415*724ba675SRob Herring clock-names = "baud", "bus"; 416*724ba675SRob Herring status = "disabled"; 417*724ba675SRob Herring }; 418*724ba675SRob Herring 419*724ba675SRob Herring pwm: pwm@11006000 { 420*724ba675SRob Herring compatible = "mediatek,mt7623-pwm"; 421*724ba675SRob Herring reg = <0 0x11006000 0 0x1000>; 422*724ba675SRob Herring #pwm-cells = <2>; 423*724ba675SRob Herring clocks = <&topckgen CLK_TOP_PWM_SEL>, 424*724ba675SRob Herring <&pericfg CLK_PERI_PWM>, 425*724ba675SRob Herring <&pericfg CLK_PERI_PWM1>, 426*724ba675SRob Herring <&pericfg CLK_PERI_PWM2>, 427*724ba675SRob Herring <&pericfg CLK_PERI_PWM3>, 428*724ba675SRob Herring <&pericfg CLK_PERI_PWM4>, 429*724ba675SRob Herring <&pericfg CLK_PERI_PWM5>; 430*724ba675SRob Herring clock-names = "top", "main", "pwm1", "pwm2", 431*724ba675SRob Herring "pwm3", "pwm4", "pwm5"; 432*724ba675SRob Herring status = "disabled"; 433*724ba675SRob Herring }; 434*724ba675SRob Herring 435*724ba675SRob Herring i2c0: i2c@11007000 { 436*724ba675SRob Herring compatible = "mediatek,mt7623-i2c", 437*724ba675SRob Herring "mediatek,mt6577-i2c"; 438*724ba675SRob Herring reg = <0 0x11007000 0 0x70>, 439*724ba675SRob Herring <0 0x11000200 0 0x80>; 440*724ba675SRob Herring interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>; 441*724ba675SRob Herring clock-div = <16>; 442*724ba675SRob Herring clocks = <&pericfg CLK_PERI_I2C0>, 443*724ba675SRob Herring <&pericfg CLK_PERI_AP_DMA>; 444*724ba675SRob Herring clock-names = "main", "dma"; 445*724ba675SRob Herring #address-cells = <1>; 446*724ba675SRob Herring #size-cells = <0>; 447*724ba675SRob Herring status = "disabled"; 448*724ba675SRob Herring }; 449*724ba675SRob Herring 450*724ba675SRob Herring i2c1: i2c@11008000 { 451*724ba675SRob Herring compatible = "mediatek,mt7623-i2c", 452*724ba675SRob Herring "mediatek,mt6577-i2c"; 453*724ba675SRob Herring reg = <0 0x11008000 0 0x70>, 454*724ba675SRob Herring <0 0x11000280 0 0x80>; 455*724ba675SRob Herring interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>; 456*724ba675SRob Herring clock-div = <16>; 457*724ba675SRob Herring clocks = <&pericfg CLK_PERI_I2C1>, 458*724ba675SRob Herring <&pericfg CLK_PERI_AP_DMA>; 459*724ba675SRob Herring clock-names = "main", "dma"; 460*724ba675SRob Herring #address-cells = <1>; 461*724ba675SRob Herring #size-cells = <0>; 462*724ba675SRob Herring status = "disabled"; 463*724ba675SRob Herring }; 464*724ba675SRob Herring 465*724ba675SRob Herring i2c2: i2c@11009000 { 466*724ba675SRob Herring compatible = "mediatek,mt7623-i2c", 467*724ba675SRob Herring "mediatek,mt6577-i2c"; 468*724ba675SRob Herring reg = <0 0x11009000 0 0x70>, 469*724ba675SRob Herring <0 0x11000300 0 0x80>; 470*724ba675SRob Herring interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>; 471*724ba675SRob Herring clock-div = <16>; 472*724ba675SRob Herring clocks = <&pericfg CLK_PERI_I2C2>, 473*724ba675SRob Herring <&pericfg CLK_PERI_AP_DMA>; 474*724ba675SRob Herring clock-names = "main", "dma"; 475*724ba675SRob Herring #address-cells = <1>; 476*724ba675SRob Herring #size-cells = <0>; 477*724ba675SRob Herring status = "disabled"; 478*724ba675SRob Herring }; 479*724ba675SRob Herring 480*724ba675SRob Herring spi0: spi@1100a000 { 481*724ba675SRob Herring compatible = "mediatek,mt7623-spi", 482*724ba675SRob Herring "mediatek,mt2701-spi"; 483*724ba675SRob Herring #address-cells = <1>; 484*724ba675SRob Herring #size-cells = <0>; 485*724ba675SRob Herring reg = <0 0x1100a000 0 0x100>; 486*724ba675SRob Herring interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 487*724ba675SRob Herring clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 488*724ba675SRob Herring <&topckgen CLK_TOP_SPI0_SEL>, 489*724ba675SRob Herring <&pericfg CLK_PERI_SPI0>; 490*724ba675SRob Herring clock-names = "parent-clk", "sel-clk", "spi-clk"; 491*724ba675SRob Herring status = "disabled"; 492*724ba675SRob Herring }; 493*724ba675SRob Herring 494*724ba675SRob Herring thermal: thermal@1100b000 { 495*724ba675SRob Herring #thermal-sensor-cells = <1>; 496*724ba675SRob Herring compatible = "mediatek,mt7623-thermal", 497*724ba675SRob Herring "mediatek,mt2701-thermal"; 498*724ba675SRob Herring reg = <0 0x1100b000 0 0x1000>; 499*724ba675SRob Herring interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 500*724ba675SRob Herring clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 501*724ba675SRob Herring clock-names = "therm", "auxadc"; 502*724ba675SRob Herring resets = <&pericfg MT2701_PERI_THERM_SW_RST>; 503*724ba675SRob Herring reset-names = "therm"; 504*724ba675SRob Herring mediatek,auxadc = <&auxadc>; 505*724ba675SRob Herring mediatek,apmixedsys = <&apmixedsys>; 506*724ba675SRob Herring nvmem-cells = <&thermal_calibration_data>; 507*724ba675SRob Herring nvmem-cell-names = "calibration-data"; 508*724ba675SRob Herring }; 509*724ba675SRob Herring 510*724ba675SRob Herring btif: serial@1100c000 { 511*724ba675SRob Herring compatible = "mediatek,mt7623-btif", 512*724ba675SRob Herring "mediatek,mtk-btif"; 513*724ba675SRob Herring reg = <0 0x1100c000 0 0x1000>; 514*724ba675SRob Herring interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_LOW>; 515*724ba675SRob Herring clocks = <&pericfg CLK_PERI_BTIF>; 516*724ba675SRob Herring clock-names = "main"; 517*724ba675SRob Herring reg-shift = <2>; 518*724ba675SRob Herring reg-io-width = <4>; 519*724ba675SRob Herring status = "disabled"; 520*724ba675SRob Herring }; 521*724ba675SRob Herring 522*724ba675SRob Herring nandc: nfi@1100d000 { 523*724ba675SRob Herring compatible = "mediatek,mt7623-nfc", 524*724ba675SRob Herring "mediatek,mt2701-nfc"; 525*724ba675SRob Herring reg = <0 0x1100d000 0 0x1000>; 526*724ba675SRob Herring interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>; 527*724ba675SRob Herring power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; 528*724ba675SRob Herring clocks = <&pericfg CLK_PERI_NFI>, 529*724ba675SRob Herring <&pericfg CLK_PERI_NFI_PAD>; 530*724ba675SRob Herring clock-names = "nfi_clk", "pad_clk"; 531*724ba675SRob Herring status = "disabled"; 532*724ba675SRob Herring ecc-engine = <&bch>; 533*724ba675SRob Herring #address-cells = <1>; 534*724ba675SRob Herring #size-cells = <0>; 535*724ba675SRob Herring }; 536*724ba675SRob Herring 537*724ba675SRob Herring bch: ecc@1100e000 { 538*724ba675SRob Herring compatible = "mediatek,mt7623-ecc", 539*724ba675SRob Herring "mediatek,mt2701-ecc"; 540*724ba675SRob Herring reg = <0 0x1100e000 0 0x1000>; 541*724ba675SRob Herring interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>; 542*724ba675SRob Herring clocks = <&pericfg CLK_PERI_NFI_ECC>; 543*724ba675SRob Herring clock-names = "nfiecc_clk"; 544*724ba675SRob Herring status = "disabled"; 545*724ba675SRob Herring }; 546*724ba675SRob Herring 547*724ba675SRob Herring nor_flash: spi@11014000 { 548*724ba675SRob Herring compatible = "mediatek,mt7623-nor", 549*724ba675SRob Herring "mediatek,mt8173-nor"; 550*724ba675SRob Herring reg = <0 0x11014000 0 0x1000>; 551*724ba675SRob Herring clocks = <&pericfg CLK_PERI_FLASH>, 552*724ba675SRob Herring <&topckgen CLK_TOP_FLASH_SEL>; 553*724ba675SRob Herring clock-names = "spi", "sf"; 554*724ba675SRob Herring #address-cells = <1>; 555*724ba675SRob Herring #size-cells = <0>; 556*724ba675SRob Herring status = "disabled"; 557*724ba675SRob Herring }; 558*724ba675SRob Herring 559*724ba675SRob Herring spi1: spi@11016000 { 560*724ba675SRob Herring compatible = "mediatek,mt7623-spi", 561*724ba675SRob Herring "mediatek,mt2701-spi"; 562*724ba675SRob Herring #address-cells = <1>; 563*724ba675SRob Herring #size-cells = <0>; 564*724ba675SRob Herring reg = <0 0x11016000 0 0x100>; 565*724ba675SRob Herring interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 566*724ba675SRob Herring clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 567*724ba675SRob Herring <&topckgen CLK_TOP_SPI1_SEL>, 568*724ba675SRob Herring <&pericfg CLK_PERI_SPI1>; 569*724ba675SRob Herring clock-names = "parent-clk", "sel-clk", "spi-clk"; 570*724ba675SRob Herring status = "disabled"; 571*724ba675SRob Herring }; 572*724ba675SRob Herring 573*724ba675SRob Herring spi2: spi@11017000 { 574*724ba675SRob Herring compatible = "mediatek,mt7623-spi", 575*724ba675SRob Herring "mediatek,mt2701-spi"; 576*724ba675SRob Herring #address-cells = <1>; 577*724ba675SRob Herring #size-cells = <0>; 578*724ba675SRob Herring reg = <0 0x11017000 0 0x1000>; 579*724ba675SRob Herring interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>; 580*724ba675SRob Herring clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 581*724ba675SRob Herring <&topckgen CLK_TOP_SPI2_SEL>, 582*724ba675SRob Herring <&pericfg CLK_PERI_SPI2>; 583*724ba675SRob Herring clock-names = "parent-clk", "sel-clk", "spi-clk"; 584*724ba675SRob Herring status = "disabled"; 585*724ba675SRob Herring }; 586*724ba675SRob Herring 587*724ba675SRob Herring usb0: usb@11200000 { 588*724ba675SRob Herring compatible = "mediatek,mt7623-musb", 589*724ba675SRob Herring "mediatek,mtk-musb"; 590*724ba675SRob Herring reg = <0 0x11200000 0 0x1000>; 591*724ba675SRob Herring interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>; 592*724ba675SRob Herring interrupt-names = "mc"; 593*724ba675SRob Herring phys = <&u2port2 PHY_TYPE_USB2>; 594*724ba675SRob Herring dr_mode = "otg"; 595*724ba675SRob Herring clocks = <&pericfg CLK_PERI_USB0>, 596*724ba675SRob Herring <&pericfg CLK_PERI_USB0_MCU>, 597*724ba675SRob Herring <&pericfg CLK_PERI_USB_SLV>; 598*724ba675SRob Herring clock-names = "main","mcu","univpll"; 599*724ba675SRob Herring power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; 600*724ba675SRob Herring status = "disabled"; 601*724ba675SRob Herring }; 602*724ba675SRob Herring 603*724ba675SRob Herring u2phy1: t-phy@11210000 { 604*724ba675SRob Herring compatible = "mediatek,mt7623-tphy", 605*724ba675SRob Herring "mediatek,generic-tphy-v1"; 606*724ba675SRob Herring reg = <0 0x11210000 0 0x0800>; 607*724ba675SRob Herring #address-cells = <2>; 608*724ba675SRob Herring #size-cells = <2>; 609*724ba675SRob Herring ranges; 610*724ba675SRob Herring status = "disabled"; 611*724ba675SRob Herring 612*724ba675SRob Herring u2port2: usb-phy@11210800 { 613*724ba675SRob Herring reg = <0 0x11210800 0 0x0100>; 614*724ba675SRob Herring clocks = <&topckgen CLK_TOP_USB_PHY48M>; 615*724ba675SRob Herring clock-names = "ref"; 616*724ba675SRob Herring #phy-cells = <1>; 617*724ba675SRob Herring }; 618*724ba675SRob Herring }; 619*724ba675SRob Herring 620*724ba675SRob Herring audsys: clock-controller@11220000 { 621*724ba675SRob Herring compatible = "mediatek,mt7623-audsys", 622*724ba675SRob Herring "mediatek,mt2701-audsys", 623*724ba675SRob Herring "syscon"; 624*724ba675SRob Herring reg = <0 0x11220000 0 0x2000>; 625*724ba675SRob Herring #clock-cells = <1>; 626*724ba675SRob Herring 627*724ba675SRob Herring afe: audio-controller { 628*724ba675SRob Herring compatible = "mediatek,mt7623-audio", 629*724ba675SRob Herring "mediatek,mt2701-audio"; 630*724ba675SRob Herring interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, 631*724ba675SRob Herring <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 632*724ba675SRob Herring interrupt-names = "afe", "asys"; 633*724ba675SRob Herring power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; 634*724ba675SRob Herring 635*724ba675SRob Herring clocks = <&infracfg CLK_INFRA_AUDIO>, 636*724ba675SRob Herring <&topckgen CLK_TOP_AUD_MUX1_SEL>, 637*724ba675SRob Herring <&topckgen CLK_TOP_AUD_MUX2_SEL>, 638*724ba675SRob Herring <&topckgen CLK_TOP_AUD_48K_TIMING>, 639*724ba675SRob Herring <&topckgen CLK_TOP_AUD_44K_TIMING>, 640*724ba675SRob Herring <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, 641*724ba675SRob Herring <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, 642*724ba675SRob Herring <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, 643*724ba675SRob Herring <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, 644*724ba675SRob Herring <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, 645*724ba675SRob Herring <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, 646*724ba675SRob Herring <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, 647*724ba675SRob Herring <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, 648*724ba675SRob Herring <&topckgen CLK_TOP_AUD_I2S1_MCLK>, 649*724ba675SRob Herring <&topckgen CLK_TOP_AUD_I2S2_MCLK>, 650*724ba675SRob Herring <&topckgen CLK_TOP_AUD_I2S3_MCLK>, 651*724ba675SRob Herring <&topckgen CLK_TOP_AUD_I2S4_MCLK>, 652*724ba675SRob Herring <&audsys CLK_AUD_I2SO1>, 653*724ba675SRob Herring <&audsys CLK_AUD_I2SO2>, 654*724ba675SRob Herring <&audsys CLK_AUD_I2SO3>, 655*724ba675SRob Herring <&audsys CLK_AUD_I2SO4>, 656*724ba675SRob Herring <&audsys CLK_AUD_I2SIN1>, 657*724ba675SRob Herring <&audsys CLK_AUD_I2SIN2>, 658*724ba675SRob Herring <&audsys CLK_AUD_I2SIN3>, 659*724ba675SRob Herring <&audsys CLK_AUD_I2SIN4>, 660*724ba675SRob Herring <&audsys CLK_AUD_ASRCO1>, 661*724ba675SRob Herring <&audsys CLK_AUD_ASRCO2>, 662*724ba675SRob Herring <&audsys CLK_AUD_ASRCO3>, 663*724ba675SRob Herring <&audsys CLK_AUD_ASRCO4>, 664*724ba675SRob Herring <&audsys CLK_AUD_AFE>, 665*724ba675SRob Herring <&audsys CLK_AUD_AFE_CONN>, 666*724ba675SRob Herring <&audsys CLK_AUD_A1SYS>, 667*724ba675SRob Herring <&audsys CLK_AUD_A2SYS>, 668*724ba675SRob Herring <&audsys CLK_AUD_AFE_MRGIF>; 669*724ba675SRob Herring 670*724ba675SRob Herring clock-names = "infra_sys_audio_clk", 671*724ba675SRob Herring "top_audio_mux1_sel", 672*724ba675SRob Herring "top_audio_mux2_sel", 673*724ba675SRob Herring "top_audio_a1sys_hp", 674*724ba675SRob Herring "top_audio_a2sys_hp", 675*724ba675SRob Herring "i2s0_src_sel", 676*724ba675SRob Herring "i2s1_src_sel", 677*724ba675SRob Herring "i2s2_src_sel", 678*724ba675SRob Herring "i2s3_src_sel", 679*724ba675SRob Herring "i2s0_src_div", 680*724ba675SRob Herring "i2s1_src_div", 681*724ba675SRob Herring "i2s2_src_div", 682*724ba675SRob Herring "i2s3_src_div", 683*724ba675SRob Herring "i2s0_mclk_en", 684*724ba675SRob Herring "i2s1_mclk_en", 685*724ba675SRob Herring "i2s2_mclk_en", 686*724ba675SRob Herring "i2s3_mclk_en", 687*724ba675SRob Herring "i2so0_hop_ck", 688*724ba675SRob Herring "i2so1_hop_ck", 689*724ba675SRob Herring "i2so2_hop_ck", 690*724ba675SRob Herring "i2so3_hop_ck", 691*724ba675SRob Herring "i2si0_hop_ck", 692*724ba675SRob Herring "i2si1_hop_ck", 693*724ba675SRob Herring "i2si2_hop_ck", 694*724ba675SRob Herring "i2si3_hop_ck", 695*724ba675SRob Herring "asrc0_out_ck", 696*724ba675SRob Herring "asrc1_out_ck", 697*724ba675SRob Herring "asrc2_out_ck", 698*724ba675SRob Herring "asrc3_out_ck", 699*724ba675SRob Herring "audio_afe_pd", 700*724ba675SRob Herring "audio_afe_conn_pd", 701*724ba675SRob Herring "audio_a1sys_pd", 702*724ba675SRob Herring "audio_a2sys_pd", 703*724ba675SRob Herring "audio_mrgif_pd"; 704*724ba675SRob Herring 705*724ba675SRob Herring assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, 706*724ba675SRob Herring <&topckgen CLK_TOP_AUD_MUX2_SEL>, 707*724ba675SRob Herring <&topckgen CLK_TOP_AUD_MUX1_DIV>, 708*724ba675SRob Herring <&topckgen CLK_TOP_AUD_MUX2_DIV>; 709*724ba675SRob Herring assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, 710*724ba675SRob Herring <&topckgen CLK_TOP_AUD2PLL_90M>; 711*724ba675SRob Herring assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; 712*724ba675SRob Herring }; 713*724ba675SRob Herring }; 714*724ba675SRob Herring 715*724ba675SRob Herring mmc0: mmc@11230000 { 716*724ba675SRob Herring compatible = "mediatek,mt7623-mmc", 717*724ba675SRob Herring "mediatek,mt2701-mmc"; 718*724ba675SRob Herring reg = <0 0x11230000 0 0x1000>; 719*724ba675SRob Herring interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>; 720*724ba675SRob Herring clocks = <&pericfg CLK_PERI_MSDC30_0>, 721*724ba675SRob Herring <&topckgen CLK_TOP_MSDC30_0_SEL>; 722*724ba675SRob Herring clock-names = "source", "hclk"; 723*724ba675SRob Herring status = "disabled"; 724*724ba675SRob Herring }; 725*724ba675SRob Herring 726*724ba675SRob Herring mmc1: mmc@11240000 { 727*724ba675SRob Herring compatible = "mediatek,mt7623-mmc", 728*724ba675SRob Herring "mediatek,mt2701-mmc"; 729*724ba675SRob Herring reg = <0 0x11240000 0 0x1000>; 730*724ba675SRob Herring interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>; 731*724ba675SRob Herring clocks = <&pericfg CLK_PERI_MSDC30_1>, 732*724ba675SRob Herring <&topckgen CLK_TOP_MSDC30_1_SEL>; 733*724ba675SRob Herring clock-names = "source", "hclk"; 734*724ba675SRob Herring status = "disabled"; 735*724ba675SRob Herring }; 736*724ba675SRob Herring 737*724ba675SRob Herring vdecsys: syscon@16000000 { 738*724ba675SRob Herring compatible = "mediatek,mt7623-vdecsys", 739*724ba675SRob Herring "mediatek,mt2701-vdecsys", 740*724ba675SRob Herring "syscon"; 741*724ba675SRob Herring reg = <0 0x16000000 0 0x1000>; 742*724ba675SRob Herring #clock-cells = <1>; 743*724ba675SRob Herring }; 744*724ba675SRob Herring 745*724ba675SRob Herring hifsys: syscon@1a000000 { 746*724ba675SRob Herring compatible = "mediatek,mt7623-hifsys", 747*724ba675SRob Herring "mediatek,mt2701-hifsys", 748*724ba675SRob Herring "syscon"; 749*724ba675SRob Herring reg = <0 0x1a000000 0 0x1000>; 750*724ba675SRob Herring #clock-cells = <1>; 751*724ba675SRob Herring #reset-cells = <1>; 752*724ba675SRob Herring }; 753*724ba675SRob Herring 754*724ba675SRob Herring pcie: pcie@1a140000 { 755*724ba675SRob Herring compatible = "mediatek,mt7623-pcie"; 756*724ba675SRob Herring device_type = "pci"; 757*724ba675SRob Herring reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ 758*724ba675SRob Herring <0 0x1a142000 0 0x1000>, /* Port0 registers */ 759*724ba675SRob Herring <0 0x1a143000 0 0x1000>, /* Port1 registers */ 760*724ba675SRob Herring <0 0x1a144000 0 0x1000>; /* Port2 registers */ 761*724ba675SRob Herring reg-names = "subsys", "port0", "port1", "port2"; 762*724ba675SRob Herring #address-cells = <3>; 763*724ba675SRob Herring #size-cells = <2>; 764*724ba675SRob Herring #interrupt-cells = <1>; 765*724ba675SRob Herring interrupt-map-mask = <0xf800 0 0 0>; 766*724ba675SRob Herring interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, 767*724ba675SRob Herring <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, 768*724ba675SRob Herring <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; 769*724ba675SRob Herring clocks = <&topckgen CLK_TOP_ETHIF_SEL>, 770*724ba675SRob Herring <&hifsys CLK_HIFSYS_PCIE0>, 771*724ba675SRob Herring <&hifsys CLK_HIFSYS_PCIE1>, 772*724ba675SRob Herring <&hifsys CLK_HIFSYS_PCIE2>; 773*724ba675SRob Herring clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; 774*724ba675SRob Herring resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, 775*724ba675SRob Herring <&hifsys MT2701_HIFSYS_PCIE1_RST>, 776*724ba675SRob Herring <&hifsys MT2701_HIFSYS_PCIE2_RST>; 777*724ba675SRob Herring reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; 778*724ba675SRob Herring phys = <&pcie0_port PHY_TYPE_PCIE>, 779*724ba675SRob Herring <&pcie1_port PHY_TYPE_PCIE>, 780*724ba675SRob Herring <&u3port1 PHY_TYPE_PCIE>; 781*724ba675SRob Herring phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; 782*724ba675SRob Herring power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; 783*724ba675SRob Herring bus-range = <0x00 0xff>; 784*724ba675SRob Herring status = "disabled"; 785*724ba675SRob Herring ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 786*724ba675SRob Herring 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; 787*724ba675SRob Herring 788*724ba675SRob Herring pcie@0,0 { 789*724ba675SRob Herring reg = <0x0000 0 0 0 0>; 790*724ba675SRob Herring #address-cells = <3>; 791*724ba675SRob Herring #size-cells = <2>; 792*724ba675SRob Herring #interrupt-cells = <1>; 793*724ba675SRob Herring interrupt-map-mask = <0 0 0 0>; 794*724ba675SRob Herring interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 795*724ba675SRob Herring ranges; 796*724ba675SRob Herring status = "disabled"; 797*724ba675SRob Herring }; 798*724ba675SRob Herring 799*724ba675SRob Herring pcie@1,0 { 800*724ba675SRob Herring reg = <0x0800 0 0 0 0>; 801*724ba675SRob Herring #address-cells = <3>; 802*724ba675SRob Herring #size-cells = <2>; 803*724ba675SRob Herring #interrupt-cells = <1>; 804*724ba675SRob Herring interrupt-map-mask = <0 0 0 0>; 805*724ba675SRob Herring interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 806*724ba675SRob Herring ranges; 807*724ba675SRob Herring status = "disabled"; 808*724ba675SRob Herring }; 809*724ba675SRob Herring 810*724ba675SRob Herring pcie@2,0 { 811*724ba675SRob Herring reg = <0x1000 0 0 0 0>; 812*724ba675SRob Herring #address-cells = <3>; 813*724ba675SRob Herring #size-cells = <2>; 814*724ba675SRob Herring #interrupt-cells = <1>; 815*724ba675SRob Herring interrupt-map-mask = <0 0 0 0>; 816*724ba675SRob Herring interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; 817*724ba675SRob Herring ranges; 818*724ba675SRob Herring status = "disabled"; 819*724ba675SRob Herring }; 820*724ba675SRob Herring }; 821*724ba675SRob Herring 822*724ba675SRob Herring pcie0_phy: t-phy@1a149000 { 823*724ba675SRob Herring compatible = "mediatek,mt7623-tphy", 824*724ba675SRob Herring "mediatek,generic-tphy-v1"; 825*724ba675SRob Herring reg = <0 0x1a149000 0 0x0700>; 826*724ba675SRob Herring #address-cells = <2>; 827*724ba675SRob Herring #size-cells = <2>; 828*724ba675SRob Herring ranges; 829*724ba675SRob Herring status = "disabled"; 830*724ba675SRob Herring 831*724ba675SRob Herring pcie0_port: pcie-phy@1a149900 { 832*724ba675SRob Herring reg = <0 0x1a149900 0 0x0700>; 833*724ba675SRob Herring clocks = <&clk26m>; 834*724ba675SRob Herring clock-names = "ref"; 835*724ba675SRob Herring #phy-cells = <1>; 836*724ba675SRob Herring status = "okay"; 837*724ba675SRob Herring }; 838*724ba675SRob Herring }; 839*724ba675SRob Herring 840*724ba675SRob Herring pcie1_phy: t-phy@1a14a000 { 841*724ba675SRob Herring compatible = "mediatek,mt7623-tphy", 842*724ba675SRob Herring "mediatek,generic-tphy-v1"; 843*724ba675SRob Herring reg = <0 0x1a14a000 0 0x0700>; 844*724ba675SRob Herring #address-cells = <2>; 845*724ba675SRob Herring #size-cells = <2>; 846*724ba675SRob Herring ranges; 847*724ba675SRob Herring status = "disabled"; 848*724ba675SRob Herring 849*724ba675SRob Herring pcie1_port: pcie-phy@1a14a900 { 850*724ba675SRob Herring reg = <0 0x1a14a900 0 0x0700>; 851*724ba675SRob Herring clocks = <&clk26m>; 852*724ba675SRob Herring clock-names = "ref"; 853*724ba675SRob Herring #phy-cells = <1>; 854*724ba675SRob Herring status = "okay"; 855*724ba675SRob Herring }; 856*724ba675SRob Herring }; 857*724ba675SRob Herring 858*724ba675SRob Herring usb1: usb@1a1c0000 { 859*724ba675SRob Herring compatible = "mediatek,mt7623-xhci", 860*724ba675SRob Herring "mediatek,mtk-xhci"; 861*724ba675SRob Herring reg = <0 0x1a1c0000 0 0x1000>, 862*724ba675SRob Herring <0 0x1a1c4700 0 0x0100>; 863*724ba675SRob Herring reg-names = "mac", "ippc"; 864*724ba675SRob Herring interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>; 865*724ba675SRob Herring clocks = <&hifsys CLK_HIFSYS_USB0PHY>, 866*724ba675SRob Herring <&topckgen CLK_TOP_ETHIF_SEL>; 867*724ba675SRob Herring clock-names = "sys_ck", "ref_ck"; 868*724ba675SRob Herring power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; 869*724ba675SRob Herring phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; 870*724ba675SRob Herring status = "disabled"; 871*724ba675SRob Herring }; 872*724ba675SRob Herring 873*724ba675SRob Herring u3phy1: t-phy@1a1c4000 { 874*724ba675SRob Herring compatible = "mediatek,mt7623-tphy", 875*724ba675SRob Herring "mediatek,generic-tphy-v1"; 876*724ba675SRob Herring reg = <0 0x1a1c4000 0 0x0700>; 877*724ba675SRob Herring #address-cells = <2>; 878*724ba675SRob Herring #size-cells = <2>; 879*724ba675SRob Herring ranges; 880*724ba675SRob Herring status = "disabled"; 881*724ba675SRob Herring 882*724ba675SRob Herring u2port0: usb-phy@1a1c4800 { 883*724ba675SRob Herring reg = <0 0x1a1c4800 0 0x0100>; 884*724ba675SRob Herring clocks = <&topckgen CLK_TOP_USB_PHY48M>; 885*724ba675SRob Herring clock-names = "ref"; 886*724ba675SRob Herring #phy-cells = <1>; 887*724ba675SRob Herring status = "okay"; 888*724ba675SRob Herring }; 889*724ba675SRob Herring 890*724ba675SRob Herring u3port0: usb-phy@1a1c4900 { 891*724ba675SRob Herring reg = <0 0x1a1c4900 0 0x0700>; 892*724ba675SRob Herring clocks = <&clk26m>; 893*724ba675SRob Herring clock-names = "ref"; 894*724ba675SRob Herring #phy-cells = <1>; 895*724ba675SRob Herring status = "okay"; 896*724ba675SRob Herring }; 897*724ba675SRob Herring }; 898*724ba675SRob Herring 899*724ba675SRob Herring usb2: usb@1a240000 { 900*724ba675SRob Herring compatible = "mediatek,mt7623-xhci", 901*724ba675SRob Herring "mediatek,mtk-xhci"; 902*724ba675SRob Herring reg = <0 0x1a240000 0 0x1000>, 903*724ba675SRob Herring <0 0x1a244700 0 0x0100>; 904*724ba675SRob Herring reg-names = "mac", "ippc"; 905*724ba675SRob Herring interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>; 906*724ba675SRob Herring clocks = <&hifsys CLK_HIFSYS_USB1PHY>, 907*724ba675SRob Herring <&topckgen CLK_TOP_ETHIF_SEL>; 908*724ba675SRob Herring clock-names = "sys_ck", "ref_ck"; 909*724ba675SRob Herring power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; 910*724ba675SRob Herring phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 911*724ba675SRob Herring status = "disabled"; 912*724ba675SRob Herring }; 913*724ba675SRob Herring 914*724ba675SRob Herring u3phy2: t-phy@1a244000 { 915*724ba675SRob Herring compatible = "mediatek,mt7623-tphy", 916*724ba675SRob Herring "mediatek,generic-tphy-v1"; 917*724ba675SRob Herring reg = <0 0x1a244000 0 0x0700>; 918*724ba675SRob Herring #address-cells = <2>; 919*724ba675SRob Herring #size-cells = <2>; 920*724ba675SRob Herring ranges; 921*724ba675SRob Herring status = "disabled"; 922*724ba675SRob Herring 923*724ba675SRob Herring u2port1: usb-phy@1a244800 { 924*724ba675SRob Herring reg = <0 0x1a244800 0 0x0100>; 925*724ba675SRob Herring clocks = <&topckgen CLK_TOP_USB_PHY48M>; 926*724ba675SRob Herring clock-names = "ref"; 927*724ba675SRob Herring #phy-cells = <1>; 928*724ba675SRob Herring status = "okay"; 929*724ba675SRob Herring }; 930*724ba675SRob Herring 931*724ba675SRob Herring u3port1: usb-phy@1a244900 { 932*724ba675SRob Herring reg = <0 0x1a244900 0 0x0700>; 933*724ba675SRob Herring clocks = <&clk26m>; 934*724ba675SRob Herring clock-names = "ref"; 935*724ba675SRob Herring #phy-cells = <1>; 936*724ba675SRob Herring status = "okay"; 937*724ba675SRob Herring }; 938*724ba675SRob Herring }; 939*724ba675SRob Herring 940*724ba675SRob Herring ethsys: syscon@1b000000 { 941*724ba675SRob Herring compatible = "mediatek,mt7623-ethsys", 942*724ba675SRob Herring "mediatek,mt2701-ethsys", 943*724ba675SRob Herring "syscon"; 944*724ba675SRob Herring reg = <0 0x1b000000 0 0x1000>; 945*724ba675SRob Herring #clock-cells = <1>; 946*724ba675SRob Herring #reset-cells = <1>; 947*724ba675SRob Herring }; 948*724ba675SRob Herring 949*724ba675SRob Herring hsdma: dma-controller@1b007000 { 950*724ba675SRob Herring compatible = "mediatek,mt7623-hsdma"; 951*724ba675SRob Herring reg = <0 0x1b007000 0 0x1000>; 952*724ba675SRob Herring interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>; 953*724ba675SRob Herring clocks = <ðsys CLK_ETHSYS_HSDMA>; 954*724ba675SRob Herring clock-names = "hsdma"; 955*724ba675SRob Herring power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; 956*724ba675SRob Herring #dma-cells = <1>; 957*724ba675SRob Herring }; 958*724ba675SRob Herring 959*724ba675SRob Herring eth: ethernet@1b100000 { 960*724ba675SRob Herring compatible = "mediatek,mt7623-eth", 961*724ba675SRob Herring "mediatek,mt2701-eth", 962*724ba675SRob Herring "syscon"; 963*724ba675SRob Herring reg = <0 0x1b100000 0 0x20000>; 964*724ba675SRob Herring interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>, 965*724ba675SRob Herring <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>, 966*724ba675SRob Herring <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; 967*724ba675SRob Herring clocks = <&topckgen CLK_TOP_ETHIF_SEL>, 968*724ba675SRob Herring <ðsys CLK_ETHSYS_ESW>, 969*724ba675SRob Herring <ðsys CLK_ETHSYS_GP1>, 970*724ba675SRob Herring <ðsys CLK_ETHSYS_GP2>, 971*724ba675SRob Herring <&apmixedsys CLK_APMIXED_TRGPLL>; 972*724ba675SRob Herring clock-names = "ethif", "esw", "gp1", "gp2", "trgpll"; 973*724ba675SRob Herring resets = <ðsys MT2701_ETHSYS_FE_RST>, 974*724ba675SRob Herring <ðsys MT2701_ETHSYS_GMAC_RST>, 975*724ba675SRob Herring <ðsys MT2701_ETHSYS_PPE_RST>; 976*724ba675SRob Herring reset-names = "fe", "gmac", "ppe"; 977*724ba675SRob Herring power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; 978*724ba675SRob Herring mediatek,ethsys = <ðsys>; 979*724ba675SRob Herring mediatek,pctl = <&syscfg_pctl_a>; 980*724ba675SRob Herring #address-cells = <1>; 981*724ba675SRob Herring #size-cells = <0>; 982*724ba675SRob Herring status = "disabled"; 983*724ba675SRob Herring 984*724ba675SRob Herring gmac0: mac@0 { 985*724ba675SRob Herring compatible = "mediatek,eth-mac"; 986*724ba675SRob Herring reg = <0>; 987*724ba675SRob Herring status = "disabled"; 988*724ba675SRob Herring }; 989*724ba675SRob Herring 990*724ba675SRob Herring gmac1: mac@1 { 991*724ba675SRob Herring compatible = "mediatek,eth-mac"; 992*724ba675SRob Herring reg = <1>; 993*724ba675SRob Herring status = "disabled"; 994*724ba675SRob Herring }; 995*724ba675SRob Herring }; 996*724ba675SRob Herring 997*724ba675SRob Herring crypto: crypto@1b240000 { 998*724ba675SRob Herring compatible = "mediatek,eip97-crypto"; 999*724ba675SRob Herring reg = <0 0x1b240000 0 0x20000>; 1000*724ba675SRob Herring interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>, 1001*724ba675SRob Herring <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>, 1002*724ba675SRob Herring <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>, 1003*724ba675SRob Herring <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>, 1004*724ba675SRob Herring <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>; 1005*724ba675SRob Herring clocks = <ðsys CLK_ETHSYS_CRYPTO>; 1006*724ba675SRob Herring clock-names = "cryp"; 1007*724ba675SRob Herring power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; 1008*724ba675SRob Herring status = "disabled"; 1009*724ba675SRob Herring }; 1010*724ba675SRob Herring 1011*724ba675SRob Herring bdpsys: syscon@1c000000 { 1012*724ba675SRob Herring compatible = "mediatek,mt7623-bdpsys", 1013*724ba675SRob Herring "mediatek,mt2701-bdpsys", 1014*724ba675SRob Herring "syscon"; 1015*724ba675SRob Herring reg = <0 0x1c000000 0 0x1000>; 1016*724ba675SRob Herring #clock-cells = <1>; 1017*724ba675SRob Herring }; 1018*724ba675SRob Herring}; 1019*724ba675SRob Herring 1020*724ba675SRob Herring&pio { 1021*724ba675SRob Herring cir_pins_a:cir-default { 1022*724ba675SRob Herring pins-cir { 1023*724ba675SRob Herring pinmux = <MT7623_PIN_46_IR_FUNC_IR>; 1024*724ba675SRob Herring bias-disable; 1025*724ba675SRob Herring }; 1026*724ba675SRob Herring }; 1027*724ba675SRob Herring 1028*724ba675SRob Herring i2c0_pins_a: i2c0-default { 1029*724ba675SRob Herring pins-i2c0 { 1030*724ba675SRob Herring pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>, 1031*724ba675SRob Herring <MT7623_PIN_76_SCL0_FUNC_SCL0>; 1032*724ba675SRob Herring bias-disable; 1033*724ba675SRob Herring }; 1034*724ba675SRob Herring }; 1035*724ba675SRob Herring 1036*724ba675SRob Herring i2c1_pins_a: i2c1-default { 1037*724ba675SRob Herring pin-i2c1 { 1038*724ba675SRob Herring pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>, 1039*724ba675SRob Herring <MT7623_PIN_58_SCL1_FUNC_SCL1>; 1040*724ba675SRob Herring bias-disable; 1041*724ba675SRob Herring }; 1042*724ba675SRob Herring }; 1043*724ba675SRob Herring 1044*724ba675SRob Herring i2c1_pins_b: i2c1-alt { 1045*724ba675SRob Herring pin-i2c1 { 1046*724ba675SRob Herring pinmux = <MT7623_PIN_242_URTS2_FUNC_SCL1>, 1047*724ba675SRob Herring <MT7623_PIN_243_UCTS2_FUNC_SDA1>; 1048*724ba675SRob Herring bias-disable; 1049*724ba675SRob Herring }; 1050*724ba675SRob Herring }; 1051*724ba675SRob Herring 1052*724ba675SRob Herring i2c2_pins_a: i2c2-default { 1053*724ba675SRob Herring pin-i2c2 { 1054*724ba675SRob Herring pinmux = <MT7623_PIN_77_SDA2_FUNC_SDA2>, 1055*724ba675SRob Herring <MT7623_PIN_78_SCL2_FUNC_SCL2>; 1056*724ba675SRob Herring bias-disable; 1057*724ba675SRob Herring }; 1058*724ba675SRob Herring }; 1059*724ba675SRob Herring 1060*724ba675SRob Herring i2c2_pins_b: i2c2-alt { 1061*724ba675SRob Herring pin-i2c2 { 1062*724ba675SRob Herring pinmux = <MT7623_PIN_122_GPIO122_FUNC_SDA2>, 1063*724ba675SRob Herring <MT7623_PIN_123_HTPLG_FUNC_SCL2>; 1064*724ba675SRob Herring bias-disable; 1065*724ba675SRob Herring }; 1066*724ba675SRob Herring }; 1067*724ba675SRob Herring 1068*724ba675SRob Herring i2s0_pins_a: i2s0-default { 1069*724ba675SRob Herring pin-i2s0 { 1070*724ba675SRob Herring pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>, 1071*724ba675SRob Herring <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>, 1072*724ba675SRob Herring <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>, 1073*724ba675SRob Herring <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>, 1074*724ba675SRob Herring <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>; 1075*724ba675SRob Herring drive-strength = <MTK_DRIVE_12mA>; 1076*724ba675SRob Herring bias-pull-down; 1077*724ba675SRob Herring }; 1078*724ba675SRob Herring }; 1079*724ba675SRob Herring 1080*724ba675SRob Herring i2s1_pins_a: i2s1-default { 1081*724ba675SRob Herring pin-i2s1 { 1082*724ba675SRob Herring pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>, 1083*724ba675SRob Herring <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>, 1084*724ba675SRob Herring <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>, 1085*724ba675SRob Herring <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>, 1086*724ba675SRob Herring <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>; 1087*724ba675SRob Herring drive-strength = <MTK_DRIVE_12mA>; 1088*724ba675SRob Herring bias-pull-down; 1089*724ba675SRob Herring }; 1090*724ba675SRob Herring }; 1091*724ba675SRob Herring 1092*724ba675SRob Herring key_pins_a: keys-alt { 1093*724ba675SRob Herring pins-keys { 1094*724ba675SRob Herring pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>, 1095*724ba675SRob Herring <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ; 1096*724ba675SRob Herring input-enable; 1097*724ba675SRob Herring }; 1098*724ba675SRob Herring }; 1099*724ba675SRob Herring 1100*724ba675SRob Herring led_pins_a: leds-alt { 1101*724ba675SRob Herring pins-leds { 1102*724ba675SRob Herring pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>, 1103*724ba675SRob Herring <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>, 1104*724ba675SRob Herring <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>; 1105*724ba675SRob Herring }; 1106*724ba675SRob Herring }; 1107*724ba675SRob Herring 1108*724ba675SRob Herring mmc0_pins_default: mmc0default { 1109*724ba675SRob Herring pins-cmd-dat { 1110*724ba675SRob Herring pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, 1111*724ba675SRob Herring <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, 1112*724ba675SRob Herring <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, 1113*724ba675SRob Herring <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, 1114*724ba675SRob Herring <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, 1115*724ba675SRob Herring <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, 1116*724ba675SRob Herring <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, 1117*724ba675SRob Herring <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, 1118*724ba675SRob Herring <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; 1119*724ba675SRob Herring input-enable; 1120*724ba675SRob Herring bias-pull-up; 1121*724ba675SRob Herring }; 1122*724ba675SRob Herring 1123*724ba675SRob Herring pins-clk { 1124*724ba675SRob Herring pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; 1125*724ba675SRob Herring bias-pull-down; 1126*724ba675SRob Herring }; 1127*724ba675SRob Herring 1128*724ba675SRob Herring pins-rst { 1129*724ba675SRob Herring pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; 1130*724ba675SRob Herring bias-pull-up; 1131*724ba675SRob Herring }; 1132*724ba675SRob Herring }; 1133*724ba675SRob Herring 1134*724ba675SRob Herring mmc0_pins_uhs: mmc0 { 1135*724ba675SRob Herring pins-cmd-dat { 1136*724ba675SRob Herring pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, 1137*724ba675SRob Herring <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, 1138*724ba675SRob Herring <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, 1139*724ba675SRob Herring <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, 1140*724ba675SRob Herring <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, 1141*724ba675SRob Herring <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, 1142*724ba675SRob Herring <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, 1143*724ba675SRob Herring <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, 1144*724ba675SRob Herring <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; 1145*724ba675SRob Herring input-enable; 1146*724ba675SRob Herring drive-strength = <MTK_DRIVE_2mA>; 1147*724ba675SRob Herring bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1148*724ba675SRob Herring }; 1149*724ba675SRob Herring 1150*724ba675SRob Herring pins-clk { 1151*724ba675SRob Herring pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; 1152*724ba675SRob Herring drive-strength = <MTK_DRIVE_2mA>; 1153*724ba675SRob Herring bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1154*724ba675SRob Herring }; 1155*724ba675SRob Herring 1156*724ba675SRob Herring pins-rst { 1157*724ba675SRob Herring pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; 1158*724ba675SRob Herring bias-pull-up; 1159*724ba675SRob Herring }; 1160*724ba675SRob Herring }; 1161*724ba675SRob Herring 1162*724ba675SRob Herring mmc1_pins_default: mmc1default { 1163*724ba675SRob Herring pins-cmd-dat { 1164*724ba675SRob Herring pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>, 1165*724ba675SRob Herring <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>, 1166*724ba675SRob Herring <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>, 1167*724ba675SRob Herring <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>, 1168*724ba675SRob Herring <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>; 1169*724ba675SRob Herring input-enable; 1170*724ba675SRob Herring drive-strength = <MTK_DRIVE_4mA>; 1171*724ba675SRob Herring bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 1172*724ba675SRob Herring }; 1173*724ba675SRob Herring 1174*724ba675SRob Herring pins-clk { 1175*724ba675SRob Herring pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>; 1176*724ba675SRob Herring bias-pull-down; 1177*724ba675SRob Herring drive-strength = <MTK_DRIVE_4mA>; 1178*724ba675SRob Herring }; 1179*724ba675SRob Herring 1180*724ba675SRob Herring pins-wp { 1181*724ba675SRob Herring pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>; 1182*724ba675SRob Herring input-enable; 1183*724ba675SRob Herring bias-pull-up; 1184*724ba675SRob Herring }; 1185*724ba675SRob Herring 1186*724ba675SRob Herring pins-insert { 1187*724ba675SRob Herring pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>; 1188*724ba675SRob Herring bias-pull-up; 1189*724ba675SRob Herring }; 1190*724ba675SRob Herring }; 1191*724ba675SRob Herring 1192*724ba675SRob Herring mmc1_pins_uhs: mmc1 { 1193*724ba675SRob Herring pins-cmd-dat { 1194*724ba675SRob Herring pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>, 1195*724ba675SRob Herring <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>, 1196*724ba675SRob Herring <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>, 1197*724ba675SRob Herring <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>, 1198*724ba675SRob Herring <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>; 1199*724ba675SRob Herring input-enable; 1200*724ba675SRob Herring drive-strength = <MTK_DRIVE_4mA>; 1201*724ba675SRob Herring bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 1202*724ba675SRob Herring }; 1203*724ba675SRob Herring 1204*724ba675SRob Herring pins-clk { 1205*724ba675SRob Herring pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>; 1206*724ba675SRob Herring drive-strength = <MTK_DRIVE_4mA>; 1207*724ba675SRob Herring bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1208*724ba675SRob Herring }; 1209*724ba675SRob Herring }; 1210*724ba675SRob Herring 1211*724ba675SRob Herring nand_pins_default: nanddefault { 1212*724ba675SRob Herring pins-ale { 1213*724ba675SRob Herring pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>; 1214*724ba675SRob Herring drive-strength = <MTK_DRIVE_8mA>; 1215*724ba675SRob Herring bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1216*724ba675SRob Herring }; 1217*724ba675SRob Herring 1218*724ba675SRob Herring pins-dat { 1219*724ba675SRob Herring pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>, 1220*724ba675SRob Herring <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>, 1221*724ba675SRob Herring <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>, 1222*724ba675SRob Herring <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>, 1223*724ba675SRob Herring <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>, 1224*724ba675SRob Herring <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>, 1225*724ba675SRob Herring <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>, 1226*724ba675SRob Herring <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>, 1227*724ba675SRob Herring <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>; 1228*724ba675SRob Herring input-enable; 1229*724ba675SRob Herring drive-strength = <MTK_DRIVE_8mA>; 1230*724ba675SRob Herring bias-pull-up; 1231*724ba675SRob Herring }; 1232*724ba675SRob Herring 1233*724ba675SRob Herring pins-we { 1234*724ba675SRob Herring pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>; 1235*724ba675SRob Herring drive-strength = <MTK_DRIVE_8mA>; 1236*724ba675SRob Herring bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 1237*724ba675SRob Herring }; 1238*724ba675SRob Herring }; 1239*724ba675SRob Herring 1240*724ba675SRob Herring pcie_default: pcie_pin_default { 1241*724ba675SRob Herring pins_cmd_dat { 1242*724ba675SRob Herring pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>, 1243*724ba675SRob Herring <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>; 1244*724ba675SRob Herring bias-disable; 1245*724ba675SRob Herring }; 1246*724ba675SRob Herring }; 1247*724ba675SRob Herring 1248*724ba675SRob Herring pwm_pins_a: pwm-default { 1249*724ba675SRob Herring pins-pwm { 1250*724ba675SRob Herring pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>, 1251*724ba675SRob Herring <MT7623_PIN_204_PWM1_FUNC_PWM1>, 1252*724ba675SRob Herring <MT7623_PIN_205_PWM2_FUNC_PWM2>, 1253*724ba675SRob Herring <MT7623_PIN_206_PWM3_FUNC_PWM3>, 1254*724ba675SRob Herring <MT7623_PIN_207_PWM4_FUNC_PWM4>; 1255*724ba675SRob Herring }; 1256*724ba675SRob Herring }; 1257*724ba675SRob Herring 1258*724ba675SRob Herring spi0_pins_a: spi0-default { 1259*724ba675SRob Herring pins-spi { 1260*724ba675SRob Herring pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>, 1261*724ba675SRob Herring <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>, 1262*724ba675SRob Herring <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>, 1263*724ba675SRob Herring <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>; 1264*724ba675SRob Herring bias-disable; 1265*724ba675SRob Herring }; 1266*724ba675SRob Herring }; 1267*724ba675SRob Herring 1268*724ba675SRob Herring spi1_pins_a: spi1-default { 1269*724ba675SRob Herring pins-spi { 1270*724ba675SRob Herring pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>, 1271*724ba675SRob Herring <MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>, 1272*724ba675SRob Herring <MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI>, 1273*724ba675SRob Herring <MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO>; 1274*724ba675SRob Herring }; 1275*724ba675SRob Herring }; 1276*724ba675SRob Herring 1277*724ba675SRob Herring spi2_pins_a: spi2-default { 1278*724ba675SRob Herring pins-spi { 1279*724ba675SRob Herring pinmux = <MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS>, 1280*724ba675SRob Herring <MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK>, 1281*724ba675SRob Herring <MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI>, 1282*724ba675SRob Herring <MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO>; 1283*724ba675SRob Herring }; 1284*724ba675SRob Herring }; 1285*724ba675SRob Herring 1286*724ba675SRob Herring uart0_pins_a: uart0-default { 1287*724ba675SRob Herring pins-dat { 1288*724ba675SRob Herring pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>, 1289*724ba675SRob Herring <MT7623_PIN_80_UTXD0_FUNC_UTXD0>; 1290*724ba675SRob Herring }; 1291*724ba675SRob Herring }; 1292*724ba675SRob Herring 1293*724ba675SRob Herring uart1_pins_a: uart1-default { 1294*724ba675SRob Herring pins-dat { 1295*724ba675SRob Herring pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>, 1296*724ba675SRob Herring <MT7623_PIN_82_UTXD1_FUNC_UTXD1>; 1297*724ba675SRob Herring }; 1298*724ba675SRob Herring }; 1299*724ba675SRob Herring 1300*724ba675SRob Herring uart2_pins_a: uart2-default { 1301*724ba675SRob Herring pins-dat { 1302*724ba675SRob Herring pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>, 1303*724ba675SRob Herring <MT7623_PIN_15_GPIO15_FUNC_UTXD2>; 1304*724ba675SRob Herring }; 1305*724ba675SRob Herring }; 1306*724ba675SRob Herring 1307*724ba675SRob Herring uart2_pins_b: uart2-alt { 1308*724ba675SRob Herring pins-dat { 1309*724ba675SRob Herring pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>, 1310*724ba675SRob Herring <MT7623_PIN_201_UTXD2_FUNC_UTXD2>; 1311*724ba675SRob Herring }; 1312*724ba675SRob Herring }; 1313*724ba675SRob Herring}; 1314