1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0+ 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (c) 2014 MundoReader S.L. 4*724ba675SRob Herring * Author: Matthias Brugger <matthias.bgg@gmail.com> 5*724ba675SRob Herring * 6*724ba675SRob Herring*/ 7*724ba675SRob Herring 8*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 9*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 10*724ba675SRob Herring 11*724ba675SRob Herring/ { 12*724ba675SRob Herring #address-cells = <1>; 13*724ba675SRob Herring #size-cells = <1>; 14*724ba675SRob Herring compatible = "mediatek,mt6589"; 15*724ba675SRob Herring interrupt-parent = <&sysirq>; 16*724ba675SRob Herring 17*724ba675SRob Herring cpus: cpus { 18*724ba675SRob Herring #address-cells = <1>; 19*724ba675SRob Herring #size-cells = <0>; 20*724ba675SRob Herring enable-method = "mediatek,mt6589-smp"; 21*724ba675SRob Herring 22*724ba675SRob Herring cpu@0 { 23*724ba675SRob Herring device_type = "cpu"; 24*724ba675SRob Herring compatible = "arm,cortex-a7"; 25*724ba675SRob Herring reg = <0x0>; 26*724ba675SRob Herring }; 27*724ba675SRob Herring cpu@1 { 28*724ba675SRob Herring device_type = "cpu"; 29*724ba675SRob Herring compatible = "arm,cortex-a7"; 30*724ba675SRob Herring reg = <0x1>; 31*724ba675SRob Herring }; 32*724ba675SRob Herring cpu@2 { 33*724ba675SRob Herring device_type = "cpu"; 34*724ba675SRob Herring compatible = "arm,cortex-a7"; 35*724ba675SRob Herring reg = <0x2>; 36*724ba675SRob Herring }; 37*724ba675SRob Herring cpu@3 { 38*724ba675SRob Herring device_type = "cpu"; 39*724ba675SRob Herring compatible = "arm,cortex-a7"; 40*724ba675SRob Herring reg = <0x3>; 41*724ba675SRob Herring }; 42*724ba675SRob Herring 43*724ba675SRob Herring }; 44*724ba675SRob Herring 45*724ba675SRob Herring clocks { 46*724ba675SRob Herring #address-cells = <1>; 47*724ba675SRob Herring #size-cells = <1>; 48*724ba675SRob Herring compatible = "simple-bus"; 49*724ba675SRob Herring ranges; 50*724ba675SRob Herring 51*724ba675SRob Herring system_clk: dummy13m { 52*724ba675SRob Herring compatible = "fixed-clock"; 53*724ba675SRob Herring clock-frequency = <13000000>; 54*724ba675SRob Herring #clock-cells = <0>; 55*724ba675SRob Herring }; 56*724ba675SRob Herring 57*724ba675SRob Herring rtc_clk: dummy32k { 58*724ba675SRob Herring compatible = "fixed-clock"; 59*724ba675SRob Herring clock-frequency = <32000>; 60*724ba675SRob Herring #clock-cells = <0>; 61*724ba675SRob Herring }; 62*724ba675SRob Herring 63*724ba675SRob Herring uart_clk: dummy26m { 64*724ba675SRob Herring compatible = "fixed-clock"; 65*724ba675SRob Herring clock-frequency = <26000000>; 66*724ba675SRob Herring #clock-cells = <0>; 67*724ba675SRob Herring }; 68*724ba675SRob Herring }; 69*724ba675SRob Herring 70*724ba675SRob Herring soc { 71*724ba675SRob Herring #address-cells = <1>; 72*724ba675SRob Herring #size-cells = <1>; 73*724ba675SRob Herring compatible = "simple-bus"; 74*724ba675SRob Herring ranges; 75*724ba675SRob Herring 76*724ba675SRob Herring timer: timer@10008000 { 77*724ba675SRob Herring compatible = "mediatek,mt6577-timer"; 78*724ba675SRob Herring reg = <0x10008000 0x80>; 79*724ba675SRob Herring interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>; 80*724ba675SRob Herring clocks = <&system_clk>, <&rtc_clk>; 81*724ba675SRob Herring clock-names = "system-clk", "rtc-clk"; 82*724ba675SRob Herring }; 83*724ba675SRob Herring 84*724ba675SRob Herring sysirq: interrupt-controller@10200100 { 85*724ba675SRob Herring compatible = "mediatek,mt6589-sysirq", 86*724ba675SRob Herring "mediatek,mt6577-sysirq"; 87*724ba675SRob Herring interrupt-controller; 88*724ba675SRob Herring #interrupt-cells = <3>; 89*724ba675SRob Herring interrupt-parent = <&gic>; 90*724ba675SRob Herring reg = <0x10200100 0x1c>; 91*724ba675SRob Herring }; 92*724ba675SRob Herring 93*724ba675SRob Herring gic: interrupt-controller@10211000 { 94*724ba675SRob Herring compatible = "arm,cortex-a7-gic"; 95*724ba675SRob Herring interrupt-controller; 96*724ba675SRob Herring #interrupt-cells = <3>; 97*724ba675SRob Herring interrupt-parent = <&gic>; 98*724ba675SRob Herring reg = <0x10211000 0x1000>, 99*724ba675SRob Herring <0x10212000 0x2000>, 100*724ba675SRob Herring <0x10214000 0x2000>, 101*724ba675SRob Herring <0x10216000 0x2000>; 102*724ba675SRob Herring }; 103*724ba675SRob Herring 104*724ba675SRob Herring uart0: serial@11006000 { 105*724ba675SRob Herring compatible = "mediatek,mt6577-uart"; 106*724ba675SRob Herring reg = <0x11006000 0x400>; 107*724ba675SRob Herring interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; 108*724ba675SRob Herring clocks = <&uart_clk>; 109*724ba675SRob Herring status = "disabled"; 110*724ba675SRob Herring }; 111*724ba675SRob Herring 112*724ba675SRob Herring uart1: serial@11007000 { 113*724ba675SRob Herring compatible = "mediatek,mt6577-uart"; 114*724ba675SRob Herring reg = <0x11007000 0x400>; 115*724ba675SRob Herring interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 116*724ba675SRob Herring clocks = <&uart_clk>; 117*724ba675SRob Herring status = "disabled"; 118*724ba675SRob Herring }; 119*724ba675SRob Herring 120*724ba675SRob Herring uart2: serial@11008000 { 121*724ba675SRob Herring compatible = "mediatek,mt6577-uart"; 122*724ba675SRob Herring reg = <0x11008000 0x400>; 123*724ba675SRob Herring interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; 124*724ba675SRob Herring clocks = <&uart_clk>; 125*724ba675SRob Herring status = "disabled"; 126*724ba675SRob Herring }; 127*724ba675SRob Herring 128*724ba675SRob Herring uart3: serial@11009000 { 129*724ba675SRob Herring compatible = "mediatek,mt6577-uart"; 130*724ba675SRob Herring reg = <0x11009000 0x400>; 131*724ba675SRob Herring interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; 132*724ba675SRob Herring clocks = <&uart_clk>; 133*724ba675SRob Herring status = "disabled"; 134*724ba675SRob Herring }; 135*724ba675SRob Herring 136*724ba675SRob Herring wdt: watchdog@10000000 { 137*724ba675SRob Herring compatible = "mediatek,mt6589-wdt"; 138*724ba675SRob Herring reg = <0x10000000 0x44>; 139*724ba675SRob Herring }; 140*724ba675SRob Herring }; 141*724ba675SRob Herring}; 142