1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0+ 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (c) 2021 Maxim Kutnij <gtk3@inbox.ru> 4*724ba675SRob Herring */ 5*724ba675SRob Herring 6*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 7*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 8*724ba675SRob Herring 9*724ba675SRob Herring/ { 10*724ba675SRob Herring #address-cells = <1>; 11*724ba675SRob Herring #size-cells = <1>; 12*724ba675SRob Herring compatible = "mediatek,mt6582"; 13*724ba675SRob Herring interrupt-parent = <&sysirq>; 14*724ba675SRob Herring 15*724ba675SRob Herring cpus { 16*724ba675SRob Herring #address-cells = <1>; 17*724ba675SRob Herring #size-cells = <0>; 18*724ba675SRob Herring 19*724ba675SRob Herring cpu@0 { 20*724ba675SRob Herring device_type = "cpu"; 21*724ba675SRob Herring compatible = "arm,cortex-a7"; 22*724ba675SRob Herring reg = <0x0>; 23*724ba675SRob Herring }; 24*724ba675SRob Herring cpu@1 { 25*724ba675SRob Herring device_type = "cpu"; 26*724ba675SRob Herring compatible = "arm,cortex-a7"; 27*724ba675SRob Herring reg = <0x1>; 28*724ba675SRob Herring }; 29*724ba675SRob Herring cpu@2 { 30*724ba675SRob Herring device_type = "cpu"; 31*724ba675SRob Herring compatible = "arm,cortex-a7"; 32*724ba675SRob Herring reg = <0x2>; 33*724ba675SRob Herring }; 34*724ba675SRob Herring cpu@3 { 35*724ba675SRob Herring device_type = "cpu"; 36*724ba675SRob Herring compatible = "arm,cortex-a7"; 37*724ba675SRob Herring reg = <0x3>; 38*724ba675SRob Herring }; 39*724ba675SRob Herring }; 40*724ba675SRob Herring 41*724ba675SRob Herring system_clk: dummy13m { 42*724ba675SRob Herring compatible = "fixed-clock"; 43*724ba675SRob Herring clock-frequency = <13000000>; 44*724ba675SRob Herring #clock-cells = <0>; 45*724ba675SRob Herring }; 46*724ba675SRob Herring 47*724ba675SRob Herring rtc_clk: dummy32k { 48*724ba675SRob Herring compatible = "fixed-clock"; 49*724ba675SRob Herring clock-frequency = <32000>; 50*724ba675SRob Herring #clock-cells = <0>; 51*724ba675SRob Herring }; 52*724ba675SRob Herring 53*724ba675SRob Herring uart_clk: dummy26m { 54*724ba675SRob Herring compatible = "fixed-clock"; 55*724ba675SRob Herring clock-frequency = <26000000>; 56*724ba675SRob Herring #clock-cells = <0>; 57*724ba675SRob Herring }; 58*724ba675SRob Herring 59*724ba675SRob Herring timer: timer@11008000 { 60*724ba675SRob Herring compatible = "mediatek,mt6577-timer"; 61*724ba675SRob Herring reg = <0x10008000 0x80>; 62*724ba675SRob Herring interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>; 63*724ba675SRob Herring clocks = <&system_clk>, <&rtc_clk>; 64*724ba675SRob Herring clock-names = "system-clk", "rtc-clk"; 65*724ba675SRob Herring }; 66*724ba675SRob Herring 67*724ba675SRob Herring sysirq: interrupt-controller@10200100 { 68*724ba675SRob Herring compatible = "mediatek,mt6582-sysirq", 69*724ba675SRob Herring "mediatek,mt6577-sysirq"; 70*724ba675SRob Herring interrupt-controller; 71*724ba675SRob Herring #interrupt-cells = <3>; 72*724ba675SRob Herring interrupt-parent = <&gic>; 73*724ba675SRob Herring reg = <0x10200100 0x1c>; 74*724ba675SRob Herring }; 75*724ba675SRob Herring 76*724ba675SRob Herring gic: interrupt-controller@10211000 { 77*724ba675SRob Herring compatible = "arm,cortex-a7-gic"; 78*724ba675SRob Herring interrupt-controller; 79*724ba675SRob Herring #interrupt-cells = <3>; 80*724ba675SRob Herring interrupt-parent = <&gic>; 81*724ba675SRob Herring reg = <0x10211000 0x1000>, 82*724ba675SRob Herring <0x10212000 0x2000>, 83*724ba675SRob Herring <0x10214000 0x2000>, 84*724ba675SRob Herring <0x10216000 0x2000>; 85*724ba675SRob Herring }; 86*724ba675SRob Herring 87*724ba675SRob Herring uart0: serial@11002000 { 88*724ba675SRob Herring compatible = "mediatek,mt6582-uart", 89*724ba675SRob Herring "mediatek,mt6577-uart"; 90*724ba675SRob Herring reg = <0x11002000 0x400>; 91*724ba675SRob Herring interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; 92*724ba675SRob Herring clocks = <&uart_clk>; 93*724ba675SRob Herring status = "disabled"; 94*724ba675SRob Herring }; 95*724ba675SRob Herring 96*724ba675SRob Herring uart1: serial@11003000 { 97*724ba675SRob Herring compatible = "mediatek,mt6582-uart", 98*724ba675SRob Herring "mediatek,mt6577-uart"; 99*724ba675SRob Herring reg = <0x11003000 0x400>; 100*724ba675SRob Herring interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 101*724ba675SRob Herring clocks = <&uart_clk>; 102*724ba675SRob Herring status = "disabled"; 103*724ba675SRob Herring }; 104*724ba675SRob Herring 105*724ba675SRob Herring uart2: serial@11004000 { 106*724ba675SRob Herring compatible = "mediatek,mt6582-uart", 107*724ba675SRob Herring "mediatek,mt6577-uart"; 108*724ba675SRob Herring reg = <0x11004000 0x400>; 109*724ba675SRob Herring interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; 110*724ba675SRob Herring clocks = <&uart_clk>; 111*724ba675SRob Herring status = "disabled"; 112*724ba675SRob Herring }; 113*724ba675SRob Herring 114*724ba675SRob Herring uart3: serial@11005000 { 115*724ba675SRob Herring compatible = "mediatek,mt6582-uart", 116*724ba675SRob Herring "mediatek,mt6577-uart"; 117*724ba675SRob Herring reg = <0x11005000 0x400>; 118*724ba675SRob Herring interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; 119*724ba675SRob Herring clocks = <&uart_clk>; 120*724ba675SRob Herring status = "disabled"; 121*724ba675SRob Herring }; 122*724ba675SRob Herring 123*724ba675SRob Herring watchdog: watchdog@10007000 { 124*724ba675SRob Herring compatible = "mediatek,mt6582-wdt", 125*724ba675SRob Herring "mediatek,mt6589-wdt"; 126*724ba675SRob Herring reg = <0x10007000 0x100>; 127*724ba675SRob Herring }; 128*724ba675SRob Herring}; 129