1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (c) 2015 MediaTek Inc. 4*724ba675SRob Herring * Author: Mars.C <mars.cheng@mediatek.com> 5*724ba675SRob Herring * 6*724ba675SRob Herring */ 7*724ba675SRob Herring 8*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 9*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 10*724ba675SRob Herring 11*724ba675SRob Herring/ { 12*724ba675SRob Herring compatible = "mediatek,mt6580"; 13*724ba675SRob Herring #address-cells = <1>; 14*724ba675SRob Herring #size-cells = <1>; 15*724ba675SRob Herring interrupt-parent = <&sysirq>; 16*724ba675SRob Herring 17*724ba675SRob Herring cpus { 18*724ba675SRob Herring #address-cells = <1>; 19*724ba675SRob Herring #size-cells = <0>; 20*724ba675SRob Herring 21*724ba675SRob Herring cpu@0 { 22*724ba675SRob Herring device_type = "cpu"; 23*724ba675SRob Herring compatible = "arm,cortex-a7"; 24*724ba675SRob Herring reg = <0x0>; 25*724ba675SRob Herring }; 26*724ba675SRob Herring cpu@1 { 27*724ba675SRob Herring device_type = "cpu"; 28*724ba675SRob Herring compatible = "arm,cortex-a7"; 29*724ba675SRob Herring reg = <0x1>; 30*724ba675SRob Herring }; 31*724ba675SRob Herring cpu@2 { 32*724ba675SRob Herring device_type = "cpu"; 33*724ba675SRob Herring compatible = "arm,cortex-a7"; 34*724ba675SRob Herring reg = <0x2>; 35*724ba675SRob Herring }; 36*724ba675SRob Herring cpu@3 { 37*724ba675SRob Herring device_type = "cpu"; 38*724ba675SRob Herring compatible = "arm,cortex-a7"; 39*724ba675SRob Herring reg = <0x3>; 40*724ba675SRob Herring }; 41*724ba675SRob Herring 42*724ba675SRob Herring }; 43*724ba675SRob Herring 44*724ba675SRob Herring system_clk: dummy13m { 45*724ba675SRob Herring compatible = "fixed-clock"; 46*724ba675SRob Herring clock-frequency = <13000000>; 47*724ba675SRob Herring #clock-cells = <0>; 48*724ba675SRob Herring }; 49*724ba675SRob Herring 50*724ba675SRob Herring rtc_clk: dummy32k { 51*724ba675SRob Herring compatible = "fixed-clock"; 52*724ba675SRob Herring clock-frequency = <32000>; 53*724ba675SRob Herring #clock-cells = <0>; 54*724ba675SRob Herring }; 55*724ba675SRob Herring 56*724ba675SRob Herring uart_clk: dummy26m { 57*724ba675SRob Herring compatible = "fixed-clock"; 58*724ba675SRob Herring clock-frequency = <26000000>; 59*724ba675SRob Herring #clock-cells = <0>; 60*724ba675SRob Herring }; 61*724ba675SRob Herring 62*724ba675SRob Herring timer: timer@10008000 { 63*724ba675SRob Herring compatible = "mediatek,mt6580-timer", 64*724ba675SRob Herring "mediatek,mt6577-timer"; 65*724ba675SRob Herring reg = <0x10008000 0x80>; 66*724ba675SRob Herring interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 67*724ba675SRob Herring clocks = <&system_clk>, <&rtc_clk>; 68*724ba675SRob Herring clock-names = "system-clk", "rtc-clk"; 69*724ba675SRob Herring }; 70*724ba675SRob Herring 71*724ba675SRob Herring sysirq: interrupt-controller@10200100 { 72*724ba675SRob Herring compatible = "mediatek,mt6580-sysirq", 73*724ba675SRob Herring "mediatek,mt6577-sysirq"; 74*724ba675SRob Herring interrupt-controller; 75*724ba675SRob Herring #interrupt-cells = <3>; 76*724ba675SRob Herring interrupt-parent = <&gic>; 77*724ba675SRob Herring reg = <0x10200100 0x1c>; 78*724ba675SRob Herring }; 79*724ba675SRob Herring 80*724ba675SRob Herring gic: interrupt-controller@10211000 { 81*724ba675SRob Herring compatible = "arm,cortex-a7-gic"; 82*724ba675SRob Herring interrupt-controller; 83*724ba675SRob Herring #interrupt-cells = <3>; 84*724ba675SRob Herring interrupt-parent = <&gic>; 85*724ba675SRob Herring reg = <0x10211000 0x1000>, 86*724ba675SRob Herring <0x10212000 0x2000>, 87*724ba675SRob Herring <0x10214000 0x2000>, 88*724ba675SRob Herring <0x10216000 0x2000>; 89*724ba675SRob Herring }; 90*724ba675SRob Herring 91*724ba675SRob Herring uart0: serial@11005000 { 92*724ba675SRob Herring compatible = "mediatek,mt6580-uart", 93*724ba675SRob Herring "mediatek,mt6577-uart"; 94*724ba675SRob Herring reg = <0x11005000 0x400>; 95*724ba675SRob Herring interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>; 96*724ba675SRob Herring clocks = <&uart_clk>; 97*724ba675SRob Herring status = "disabled"; 98*724ba675SRob Herring }; 99*724ba675SRob Herring 100*724ba675SRob Herring uart1: serial@11006000 { 101*724ba675SRob Herring compatible = "mediatek,mt6580-uart", 102*724ba675SRob Herring "mediatek,mt6577-uart"; 103*724ba675SRob Herring reg = <0x11006000 0x400>; 104*724ba675SRob Herring interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>; 105*724ba675SRob Herring clocks = <&uart_clk>; 106*724ba675SRob Herring status = "disabled"; 107*724ba675SRob Herring }; 108*724ba675SRob Herring}; 109