1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0
2*724ba675SRob Herring/ {
3*724ba675SRob Herring	mbus@f1000000 {
4*724ba675SRob Herring		pciec: pcie@82000000 {
5*724ba675SRob Herring			compatible = "marvell,kirkwood-pcie";
6*724ba675SRob Herring			status = "disabled";
7*724ba675SRob Herring			device_type = "pci";
8*724ba675SRob Herring
9*724ba675SRob Herring			#address-cells = <3>;
10*724ba675SRob Herring			#size-cells = <2>;
11*724ba675SRob Herring
12*724ba675SRob Herring			bus-range = <0x00 0xff>;
13*724ba675SRob Herring
14*724ba675SRob Herring			ranges =
15*724ba675SRob Herring			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
16*724ba675SRob Herring				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
17*724ba675SRob Herring				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */>;
18*724ba675SRob Herring
19*724ba675SRob Herring			pcie0: pcie@1,0 {
20*724ba675SRob Herring				device_type = "pci";
21*724ba675SRob Herring				assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
22*724ba675SRob Herring				reg = <0x0800 0 0 0 0>;
23*724ba675SRob Herring				#address-cells = <3>;
24*724ba675SRob Herring				#size-cells = <2>;
25*724ba675SRob Herring				#interrupt-cells = <1>;
26*724ba675SRob Herring				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
27*724ba675SRob Herring					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
28*724ba675SRob Herring				bus-range = <0x00 0xff>;
29*724ba675SRob Herring				interrupt-names = "intx", "error";
30*724ba675SRob Herring				interrupts = <9>, <44>;
31*724ba675SRob Herring				interrupt-map-mask = <0 0 0 7>;
32*724ba675SRob Herring				interrupt-map = <0 0 0 1 &pcie_intc 0>,
33*724ba675SRob Herring						<0 0 0 2 &pcie_intc 1>,
34*724ba675SRob Herring						<0 0 0 3 &pcie_intc 2>,
35*724ba675SRob Herring						<0 0 0 4 &pcie_intc 3>;
36*724ba675SRob Herring				marvell,pcie-port = <0>;
37*724ba675SRob Herring				marvell,pcie-lane = <0>;
38*724ba675SRob Herring				clocks = <&gate_clk 2>;
39*724ba675SRob Herring				status = "disabled";
40*724ba675SRob Herring
41*724ba675SRob Herring				pcie_intc: interrupt-controller {
42*724ba675SRob Herring					interrupt-controller;
43*724ba675SRob Herring					#interrupt-cells = <1>;
44*724ba675SRob Herring				};
45*724ba675SRob Herring			};
46*724ba675SRob Herring		};
47*724ba675SRob Herring	};
48*724ba675SRob Herring
49*724ba675SRob Herring	ocp@f1000000 {
50*724ba675SRob Herring		pinctrl: pin-controller@10000 {
51*724ba675SRob Herring			compatible = "marvell,98dx4122-pinctrl";
52*724ba675SRob Herring
53*724ba675SRob Herring		};
54*724ba675SRob Herring	};
55*724ba675SRob Herring};
56*724ba675SRob Herring
57*724ba675SRob Herring&sata_phy0 {
58*724ba675SRob Herring	status = "disabled";
59*724ba675SRob Herring};
60*724ba675SRob Herring
61*724ba675SRob Herring&sata_phy1 {
62*724ba675SRob Herring	status = "disabled";
63*724ba675SRob Herring};
64