1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree Include file for Marvell Armada XP family SoC 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2012 Marvell 6*724ba675SRob Herring * 7*724ba675SRob Herring * Lior Amsalem <alior@marvell.com> 8*724ba675SRob Herring * Gregory CLEMENT <gregory.clement@free-electrons.com> 9*724ba675SRob Herring * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 10*724ba675SRob Herring * Ben Dooks <ben.dooks@codethink.co.uk> 11*724ba675SRob Herring * 12*724ba675SRob Herring * Contains definitions specific to the Armada XP SoC that are not 13*724ba675SRob Herring * common to all Armada SoCs. 14*724ba675SRob Herring */ 15*724ba675SRob Herring 16*724ba675SRob Herring#include "armada-370-xp.dtsi" 17*724ba675SRob Herring 18*724ba675SRob Herring/ { 19*724ba675SRob Herring #address-cells = <2>; 20*724ba675SRob Herring #size-cells = <2>; 21*724ba675SRob Herring 22*724ba675SRob Herring model = "Marvell Armada XP family SoC"; 23*724ba675SRob Herring compatible = "marvell,armadaxp", "marvell,armada-370-xp"; 24*724ba675SRob Herring 25*724ba675SRob Herring aliases { 26*724ba675SRob Herring serial2 = &uart2; 27*724ba675SRob Herring serial3 = &uart3; 28*724ba675SRob Herring }; 29*724ba675SRob Herring 30*724ba675SRob Herring soc { 31*724ba675SRob Herring compatible = "marvell,armadaxp-mbus", "simple-bus"; 32*724ba675SRob Herring 33*724ba675SRob Herring bootrom { 34*724ba675SRob Herring compatible = "marvell,bootrom"; 35*724ba675SRob Herring reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; 36*724ba675SRob Herring }; 37*724ba675SRob Herring 38*724ba675SRob Herring internal-regs { 39*724ba675SRob Herring sdramc: sdramc@1400 { 40*724ba675SRob Herring compatible = "marvell,armada-xp-sdram-controller"; 41*724ba675SRob Herring reg = <0x1400 0x500>; 42*724ba675SRob Herring }; 43*724ba675SRob Herring 44*724ba675SRob Herring L2: l2-cache@8000 { 45*724ba675SRob Herring compatible = "marvell,aurora-system-cache"; 46*724ba675SRob Herring reg = <0x08000 0x1000>; 47*724ba675SRob Herring cache-id-part = <0x100>; 48*724ba675SRob Herring cache-level = <2>; 49*724ba675SRob Herring cache-unified; 50*724ba675SRob Herring wt-override; 51*724ba675SRob Herring }; 52*724ba675SRob Herring 53*724ba675SRob Herring uart2: serial@12200 { 54*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 55*724ba675SRob Herring pinctrl-0 = <&uart2_pins>; 56*724ba675SRob Herring pinctrl-names = "default"; 57*724ba675SRob Herring reg = <0x12200 0x100>; 58*724ba675SRob Herring reg-shift = <2>; 59*724ba675SRob Herring interrupts = <43>; 60*724ba675SRob Herring reg-io-width = <1>; 61*724ba675SRob Herring clocks = <&coreclk 0>; 62*724ba675SRob Herring status = "disabled"; 63*724ba675SRob Herring }; 64*724ba675SRob Herring 65*724ba675SRob Herring uart3: serial@12300 { 66*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 67*724ba675SRob Herring pinctrl-0 = <&uart3_pins>; 68*724ba675SRob Herring pinctrl-names = "default"; 69*724ba675SRob Herring reg = <0x12300 0x100>; 70*724ba675SRob Herring reg-shift = <2>; 71*724ba675SRob Herring interrupts = <44>; 72*724ba675SRob Herring reg-io-width = <1>; 73*724ba675SRob Herring clocks = <&coreclk 0>; 74*724ba675SRob Herring status = "disabled"; 75*724ba675SRob Herring }; 76*724ba675SRob Herring 77*724ba675SRob Herring systemc: system-controller@18200 { 78*724ba675SRob Herring compatible = "marvell,armada-370-xp-system-controller"; 79*724ba675SRob Herring reg = <0x18200 0x500>; 80*724ba675SRob Herring }; 81*724ba675SRob Herring 82*724ba675SRob Herring gateclk: clock-gating-control@18220 { 83*724ba675SRob Herring compatible = "marvell,armada-xp-gating-clock"; 84*724ba675SRob Herring reg = <0x18220 0x4>; 85*724ba675SRob Herring clocks = <&coreclk 0>; 86*724ba675SRob Herring #clock-cells = <1>; 87*724ba675SRob Herring }; 88*724ba675SRob Herring 89*724ba675SRob Herring coreclk: mvebu-sar@18230 { 90*724ba675SRob Herring compatible = "marvell,armada-xp-core-clock"; 91*724ba675SRob Herring reg = <0x18230 0x08>; 92*724ba675SRob Herring #clock-cells = <1>; 93*724ba675SRob Herring }; 94*724ba675SRob Herring 95*724ba675SRob Herring thermal: thermal@182b0 { 96*724ba675SRob Herring compatible = "marvell,armadaxp-thermal"; 97*724ba675SRob Herring reg = <0x182b0 0x4 98*724ba675SRob Herring 0x184d0 0x4>; 99*724ba675SRob Herring status = "okay"; 100*724ba675SRob Herring }; 101*724ba675SRob Herring 102*724ba675SRob Herring cpuclk: clock-complex@18700 { 103*724ba675SRob Herring #clock-cells = <1>; 104*724ba675SRob Herring compatible = "marvell,armada-xp-cpu-clock"; 105*724ba675SRob Herring reg = <0x18700 0x24>, <0x1c054 0x10>; 106*724ba675SRob Herring clocks = <&coreclk 1>; 107*724ba675SRob Herring }; 108*724ba675SRob Herring 109*724ba675SRob Herring cpu-config@21000 { 110*724ba675SRob Herring compatible = "marvell,armada-xp-cpu-config"; 111*724ba675SRob Herring reg = <0x21000 0x8>; 112*724ba675SRob Herring }; 113*724ba675SRob Herring 114*724ba675SRob Herring eth2: ethernet@30000 { 115*724ba675SRob Herring compatible = "marvell,armada-xp-neta"; 116*724ba675SRob Herring reg = <0x30000 0x4000>; 117*724ba675SRob Herring interrupts = <12>; 118*724ba675SRob Herring clocks = <&gateclk 2>; 119*724ba675SRob Herring status = "disabled"; 120*724ba675SRob Herring }; 121*724ba675SRob Herring 122*724ba675SRob Herring usb2: usb@52000 { 123*724ba675SRob Herring compatible = "marvell,orion-ehci"; 124*724ba675SRob Herring reg = <0x52000 0x500>; 125*724ba675SRob Herring interrupts = <47>; 126*724ba675SRob Herring clocks = <&gateclk 20>; 127*724ba675SRob Herring status = "disabled"; 128*724ba675SRob Herring }; 129*724ba675SRob Herring 130*724ba675SRob Herring xor1: xor@60900 { 131*724ba675SRob Herring compatible = "marvell,orion-xor"; 132*724ba675SRob Herring reg = <0x60900 0x100 133*724ba675SRob Herring 0x60b00 0x100>; 134*724ba675SRob Herring clocks = <&gateclk 22>; 135*724ba675SRob Herring status = "okay"; 136*724ba675SRob Herring 137*724ba675SRob Herring xor10 { 138*724ba675SRob Herring interrupts = <51>; 139*724ba675SRob Herring dmacap,memcpy; 140*724ba675SRob Herring dmacap,xor; 141*724ba675SRob Herring }; 142*724ba675SRob Herring xor11 { 143*724ba675SRob Herring interrupts = <52>; 144*724ba675SRob Herring dmacap,memcpy; 145*724ba675SRob Herring dmacap,xor; 146*724ba675SRob Herring dmacap,memset; 147*724ba675SRob Herring }; 148*724ba675SRob Herring }; 149*724ba675SRob Herring 150*724ba675SRob Herring ethernet@70000 { 151*724ba675SRob Herring compatible = "marvell,armada-xp-neta"; 152*724ba675SRob Herring }; 153*724ba675SRob Herring 154*724ba675SRob Herring ethernet@74000 { 155*724ba675SRob Herring compatible = "marvell,armada-xp-neta"; 156*724ba675SRob Herring }; 157*724ba675SRob Herring 158*724ba675SRob Herring cesa: crypto@90000 { 159*724ba675SRob Herring compatible = "marvell,armada-xp-crypto"; 160*724ba675SRob Herring reg = <0x90000 0x10000>; 161*724ba675SRob Herring reg-names = "regs"; 162*724ba675SRob Herring interrupts = <48>, <49>; 163*724ba675SRob Herring clocks = <&gateclk 23>, <&gateclk 23>; 164*724ba675SRob Herring clock-names = "cesa0", "cesa1"; 165*724ba675SRob Herring marvell,crypto-srams = <&crypto_sram0>, 166*724ba675SRob Herring <&crypto_sram1>; 167*724ba675SRob Herring marvell,crypto-sram-size = <0x800>; 168*724ba675SRob Herring }; 169*724ba675SRob Herring 170*724ba675SRob Herring bm: bm@c0000 { 171*724ba675SRob Herring compatible = "marvell,armada-380-neta-bm"; 172*724ba675SRob Herring reg = <0xc0000 0xac>; 173*724ba675SRob Herring clocks = <&gateclk 13>; 174*724ba675SRob Herring internal-mem = <&bm_bppi>; 175*724ba675SRob Herring status = "disabled"; 176*724ba675SRob Herring }; 177*724ba675SRob Herring 178*724ba675SRob Herring xor0: xor@f0900 { 179*724ba675SRob Herring compatible = "marvell,orion-xor"; 180*724ba675SRob Herring reg = <0xF0900 0x100 181*724ba675SRob Herring 0xF0B00 0x100>; 182*724ba675SRob Herring clocks = <&gateclk 28>; 183*724ba675SRob Herring status = "okay"; 184*724ba675SRob Herring 185*724ba675SRob Herring xor00 { 186*724ba675SRob Herring interrupts = <94>; 187*724ba675SRob Herring dmacap,memcpy; 188*724ba675SRob Herring dmacap,xor; 189*724ba675SRob Herring }; 190*724ba675SRob Herring xor01 { 191*724ba675SRob Herring interrupts = <95>; 192*724ba675SRob Herring dmacap,memcpy; 193*724ba675SRob Herring dmacap,xor; 194*724ba675SRob Herring dmacap,memset; 195*724ba675SRob Herring }; 196*724ba675SRob Herring }; 197*724ba675SRob Herring }; 198*724ba675SRob Herring 199*724ba675SRob Herring crypto_sram0: sa-sram0 { 200*724ba675SRob Herring compatible = "mmio-sram"; 201*724ba675SRob Herring reg = <MBUS_ID(0x09, 0x09) 0 0x800>; 202*724ba675SRob Herring clocks = <&gateclk 23>; 203*724ba675SRob Herring #address-cells = <1>; 204*724ba675SRob Herring #size-cells = <1>; 205*724ba675SRob Herring ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>; 206*724ba675SRob Herring }; 207*724ba675SRob Herring 208*724ba675SRob Herring crypto_sram1: sa-sram1 { 209*724ba675SRob Herring compatible = "mmio-sram"; 210*724ba675SRob Herring reg = <MBUS_ID(0x09, 0x05) 0 0x800>; 211*724ba675SRob Herring clocks = <&gateclk 23>; 212*724ba675SRob Herring #address-cells = <1>; 213*724ba675SRob Herring #size-cells = <1>; 214*724ba675SRob Herring ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; 215*724ba675SRob Herring }; 216*724ba675SRob Herring 217*724ba675SRob Herring bm_bppi: bm-bppi { 218*724ba675SRob Herring compatible = "mmio-sram"; 219*724ba675SRob Herring reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>; 220*724ba675SRob Herring ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; 221*724ba675SRob Herring #address-cells = <1>; 222*724ba675SRob Herring #size-cells = <1>; 223*724ba675SRob Herring clocks = <&gateclk 13>; 224*724ba675SRob Herring no-memory-wc; 225*724ba675SRob Herring status = "disabled"; 226*724ba675SRob Herring }; 227*724ba675SRob Herring }; 228*724ba675SRob Herring 229*724ba675SRob Herring clocks { 230*724ba675SRob Herring /* 25 MHz reference crystal */ 231*724ba675SRob Herring refclk: oscillator { 232*724ba675SRob Herring compatible = "fixed-clock"; 233*724ba675SRob Herring #clock-cells = <0>; 234*724ba675SRob Herring clock-frequency = <25000000>; 235*724ba675SRob Herring }; 236*724ba675SRob Herring }; 237*724ba675SRob Herring}; 238*724ba675SRob Herring 239*724ba675SRob Herring&i2c0 { 240*724ba675SRob Herring compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; 241*724ba675SRob Herring reg = <0x11000 0x100>; 242*724ba675SRob Herring}; 243*724ba675SRob Herring 244*724ba675SRob Herring&i2c1 { 245*724ba675SRob Herring compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; 246*724ba675SRob Herring reg = <0x11100 0x100>; 247*724ba675SRob Herring}; 248*724ba675SRob Herring 249*724ba675SRob Herring&mpic { 250*724ba675SRob Herring reg = <0x20a00 0x2d0>, <0x21070 0x58>; 251*724ba675SRob Herring}; 252*724ba675SRob Herring 253*724ba675SRob Herring&timer { 254*724ba675SRob Herring compatible = "marvell,armada-xp-timer"; 255*724ba675SRob Herring clocks = <&coreclk 2>, <&refclk>; 256*724ba675SRob Herring clock-names = "nbclk", "fixed"; 257*724ba675SRob Herring}; 258*724ba675SRob Herring 259*724ba675SRob Herring&watchdog { 260*724ba675SRob Herring compatible = "marvell,armada-xp-wdt"; 261*724ba675SRob Herring clocks = <&coreclk 2>, <&refclk>; 262*724ba675SRob Herring clock-names = "nbclk", "fixed"; 263*724ba675SRob Herring interrupts = <93>, <38>; 264*724ba675SRob Herring}; 265*724ba675SRob Herring 266*724ba675SRob Herring&cpurst { 267*724ba675SRob Herring reg = <0x20800 0x20>; 268*724ba675SRob Herring}; 269*724ba675SRob Herring 270*724ba675SRob Herring&usb0 { 271*724ba675SRob Herring clocks = <&gateclk 18>; 272*724ba675SRob Herring}; 273*724ba675SRob Herring 274*724ba675SRob Herring&usb1 { 275*724ba675SRob Herring clocks = <&gateclk 19>; 276*724ba675SRob Herring}; 277*724ba675SRob Herring 278*724ba675SRob Herring&pinctrl { 279*724ba675SRob Herring ge0_gmii_pins: ge0-gmii-pins { 280*724ba675SRob Herring marvell,pins = 281*724ba675SRob Herring "mpp0", "mpp1", "mpp2", "mpp3", 282*724ba675SRob Herring "mpp4", "mpp5", "mpp6", "mpp7", 283*724ba675SRob Herring "mpp8", "mpp9", "mpp10", "mpp11", 284*724ba675SRob Herring "mpp12", "mpp13", "mpp14", "mpp15", 285*724ba675SRob Herring "mpp16", "mpp17", "mpp18", "mpp19", 286*724ba675SRob Herring "mpp20", "mpp21", "mpp22", "mpp23"; 287*724ba675SRob Herring marvell,function = "ge0"; 288*724ba675SRob Herring }; 289*724ba675SRob Herring 290*724ba675SRob Herring ge0_rgmii_pins: ge0-rgmii-pins { 291*724ba675SRob Herring marvell,pins = 292*724ba675SRob Herring "mpp0", "mpp1", "mpp2", "mpp3", 293*724ba675SRob Herring "mpp4", "mpp5", "mpp6", "mpp7", 294*724ba675SRob Herring "mpp8", "mpp9", "mpp10", "mpp11"; 295*724ba675SRob Herring marvell,function = "ge0"; 296*724ba675SRob Herring }; 297*724ba675SRob Herring 298*724ba675SRob Herring ge1_rgmii_pins: ge1-rgmii-pins { 299*724ba675SRob Herring marvell,pins = 300*724ba675SRob Herring "mpp12", "mpp13", "mpp14", "mpp15", 301*724ba675SRob Herring "mpp16", "mpp17", "mpp18", "mpp19", 302*724ba675SRob Herring "mpp20", "mpp21", "mpp22", "mpp23"; 303*724ba675SRob Herring marvell,function = "ge1"; 304*724ba675SRob Herring }; 305*724ba675SRob Herring 306*724ba675SRob Herring sdio_pins: sdio-pins { 307*724ba675SRob Herring marvell,pins = "mpp30", "mpp31", "mpp32", 308*724ba675SRob Herring "mpp33", "mpp34", "mpp35"; 309*724ba675SRob Herring marvell,function = "sd0"; 310*724ba675SRob Herring }; 311*724ba675SRob Herring 312*724ba675SRob Herring spi0_pins: spi0-pins { 313*724ba675SRob Herring marvell,pins = "mpp36", "mpp37", 314*724ba675SRob Herring "mpp38", "mpp39"; 315*724ba675SRob Herring marvell,function = "spi0"; 316*724ba675SRob Herring }; 317*724ba675SRob Herring 318*724ba675SRob Herring spi1_pins: spi1-pins { 319*724ba675SRob Herring marvell,pins = "mpp13", "mpp14", 320*724ba675SRob Herring "mpp16", "mpp17"; 321*724ba675SRob Herring marvell,function = "spi1"; 322*724ba675SRob Herring }; 323*724ba675SRob Herring 324*724ba675SRob Herring uart2_pins: uart2-pins { 325*724ba675SRob Herring marvell,pins = "mpp42", "mpp43"; 326*724ba675SRob Herring marvell,function = "uart2"; 327*724ba675SRob Herring }; 328*724ba675SRob Herring 329*724ba675SRob Herring uart3_pins: uart3-pins { 330*724ba675SRob Herring marvell,pins = "mpp44", "mpp45"; 331*724ba675SRob Herring marvell,function = "uart3"; 332*724ba675SRob Herring }; 333*724ba675SRob Herring}; 334*724ba675SRob Herring 335*724ba675SRob Herring&spi0 { 336*724ba675SRob Herring compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; 337*724ba675SRob Herring pinctrl-0 = <&spi0_pins>; 338*724ba675SRob Herring pinctrl-names = "default"; 339*724ba675SRob Herring}; 340*724ba675SRob Herring 341*724ba675SRob Herring&spi1 { 342*724ba675SRob Herring compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; 343*724ba675SRob Herring pinctrl-0 = <&spi1_pins>; 344*724ba675SRob Herring pinctrl-names = "default"; 345*724ba675SRob Herring}; 346