1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*724ba675SRob Herring/*
3*724ba675SRob Herring * Device Tree file for CRS326-24G-2S board
4*724ba675SRob Herring *
5*724ba675SRob Herring * Copyright (C) 2016 Allied Telesis Labs
6*724ba675SRob Herring * Copyright (C) 2020 Sartura Ltd.
7*724ba675SRob Herring *
8*724ba675SRob Herring * Based on armada-xp-db.dts
9*724ba675SRob Herring *
10*724ba675SRob Herring * Note: this Device Tree assumes that the bootloader has remapped the
11*724ba675SRob Herring * internal registers to 0xf1000000 (instead of the default
12*724ba675SRob Herring * 0xd0000000). The 0xf1000000 is the default used by the recent,
13*724ba675SRob Herring * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
14*724ba675SRob Herring * boards were delivered with an older version of the bootloader that
15*724ba675SRob Herring * left internal registers mapped at 0xd0000000. If you are in this
16*724ba675SRob Herring * situation, you should either update your bootloader (preferred
17*724ba675SRob Herring * solution) or the below Device Tree should be adjusted.
18*724ba675SRob Herring */
19*724ba675SRob Herring
20*724ba675SRob Herring/dts-v1/;
21*724ba675SRob Herring#include "armada-xp-98dx3236.dtsi"
22*724ba675SRob Herring
23*724ba675SRob Herring/ {
24*724ba675SRob Herring	model = "CRS326-24G-2S+";
25*724ba675SRob Herring	compatible = "mikrotik,crs326-24g-2s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
26*724ba675SRob Herring
27*724ba675SRob Herring	chosen {
28*724ba675SRob Herring		bootargs = "console=ttyS0,115200 earlyprintk";
29*724ba675SRob Herring	};
30*724ba675SRob Herring
31*724ba675SRob Herring	memory {
32*724ba675SRob Herring		device_type = "memory";
33*724ba675SRob Herring		reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
34*724ba675SRob Herring	};
35*724ba675SRob Herring};
36*724ba675SRob Herring
37*724ba675SRob Herring&L2 {
38*724ba675SRob Herring	arm,parity-enable;
39*724ba675SRob Herring	marvell,ecc-enable;
40*724ba675SRob Herring};
41*724ba675SRob Herring
42*724ba675SRob Herring&devbus_bootcs {
43*724ba675SRob Herring	status = "okay";
44*724ba675SRob Herring
45*724ba675SRob Herring	/* Device Bus parameters are required */
46*724ba675SRob Herring
47*724ba675SRob Herring	/* Read parameters */
48*724ba675SRob Herring	devbus,bus-width    = <16>;
49*724ba675SRob Herring	devbus,turn-off-ps  = <60000>;
50*724ba675SRob Herring	devbus,badr-skew-ps = <0>;
51*724ba675SRob Herring	devbus,acc-first-ps = <124000>;
52*724ba675SRob Herring	devbus,acc-next-ps  = <248000>;
53*724ba675SRob Herring	devbus,rd-setup-ps  = <0>;
54*724ba675SRob Herring	devbus,rd-hold-ps   = <0>;
55*724ba675SRob Herring
56*724ba675SRob Herring	/* Write parameters */
57*724ba675SRob Herring	devbus,sync-enable = <0>;
58*724ba675SRob Herring	devbus,wr-high-ps  = <60000>;
59*724ba675SRob Herring	devbus,wr-low-ps   = <60000>;
60*724ba675SRob Herring	devbus,ale-wr-ps   = <60000>;
61*724ba675SRob Herring};
62*724ba675SRob Herring
63*724ba675SRob Herring&uart0 {
64*724ba675SRob Herring	status = "okay";
65*724ba675SRob Herring};
66*724ba675SRob Herring
67*724ba675SRob Herring&uart1 {
68*724ba675SRob Herring	status = "okay";
69*724ba675SRob Herring};
70*724ba675SRob Herring
71*724ba675SRob Herring&i2c0 {
72*724ba675SRob Herring	clock-frequency = <100000>;
73*724ba675SRob Herring	status = "okay";
74*724ba675SRob Herring};
75*724ba675SRob Herring
76*724ba675SRob Herring&usb0 {
77*724ba675SRob Herring	status = "okay";
78*724ba675SRob Herring};
79*724ba675SRob Herring
80*724ba675SRob Herring&spi0 {
81*724ba675SRob Herring	status = "okay";
82*724ba675SRob Herring
83*724ba675SRob Herring	flash@0 {
84*724ba675SRob Herring		#address-cells = <1>;
85*724ba675SRob Herring		#size-cells = <1>;
86*724ba675SRob Herring		compatible = "jedec,spi-nor";
87*724ba675SRob Herring		reg = <0>; /* Chip select 0 */
88*724ba675SRob Herring		spi-max-frequency = <108000000>;
89*724ba675SRob Herring		m25p,fast-read;
90*724ba675SRob Herring
91*724ba675SRob Herring		partition@u-boot {
92*724ba675SRob Herring			reg = <0x00000000 0x001f0000>;
93*724ba675SRob Herring			label = "u-boot";
94*724ba675SRob Herring		};
95*724ba675SRob Herring		partition@u-boot-env {
96*724ba675SRob Herring			reg = <0x001f0000 0x00010000>;
97*724ba675SRob Herring			label = "u-boot-env";
98*724ba675SRob Herring		};
99*724ba675SRob Herring		partition@ubi1 {
100*724ba675SRob Herring			reg = <0x00200000 0x00e00000>;
101*724ba675SRob Herring			label = "ubi1";
102*724ba675SRob Herring		};
103*724ba675SRob Herring	};
104*724ba675SRob Herring};
105