1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree Include file for Marvell 98dx3336 family SoC 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2016 Allied Telesis Labs 6*724ba675SRob Herring * 7*724ba675SRob Herring * Contains definitions specific to the 98dx3236 SoC that are not 8*724ba675SRob Herring * common to all Armada XP SoCs. 9*724ba675SRob Herring */ 10*724ba675SRob Herring 11*724ba675SRob Herring#include "armada-xp-98dx3236.dtsi" 12*724ba675SRob Herring 13*724ba675SRob Herring/ { 14*724ba675SRob Herring model = "Marvell 98DX3336 SoC"; 15*724ba675SRob Herring compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; 16*724ba675SRob Herring 17*724ba675SRob Herring cpus { 18*724ba675SRob Herring cpu@1 { 19*724ba675SRob Herring device_type = "cpu"; 20*724ba675SRob Herring compatible = "marvell,sheeva-v7"; 21*724ba675SRob Herring reg = <1>; 22*724ba675SRob Herring clocks = <&cpuclk 1>; 23*724ba675SRob Herring clock-latency = <1000000>; 24*724ba675SRob Herring }; 25*724ba675SRob Herring }; 26*724ba675SRob Herring 27*724ba675SRob Herring soc { 28*724ba675SRob Herring internal-regs { 29*724ba675SRob Herring resume@20980 { 30*724ba675SRob Herring compatible = "marvell,98dx3336-resume-ctrl"; 31*724ba675SRob Herring reg = <0x20980 0x10>; 32*724ba675SRob Herring }; 33*724ba675SRob Herring }; 34*724ba675SRob Herring }; 35*724ba675SRob Herring}; 36*724ba675SRob Herring 37*724ba675SRob Herring&pp0 { 38*724ba675SRob Herring compatible = "marvell,prestera-98dx3336", "marvell,prestera"; 39*724ba675SRob Herring}; 40