1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Marvell Armada 38x family of SoCs. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Lior Amsalem <alior@marvell.com> 8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 10 */ 11 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14 15#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 model = "Marvell Armada 38x family SoC"; 22 compatible = "marvell,armada380"; 23 24 aliases { 25 gpio0 = &gpio0; 26 gpio1 = &gpio1; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 }; 30 31 pmu { 32 compatible = "arm,cortex-a9-pmu"; 33 interrupts-extended = <&mpic 3>; 34 }; 35 36 soc { 37 compatible = "marvell,armada380-mbus", "simple-bus"; 38 #address-cells = <2>; 39 #size-cells = <1>; 40 controller = <&mbusc>; 41 interrupt-parent = <&gic>; 42 pcie-mem-aperture = <0xe0000000 0x8000000>; 43 pcie-io-aperture = <0xe8000000 0x100000>; 44 45 bootrom { 46 compatible = "marvell,bootrom"; 47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; 48 }; 49 50 devbus_bootcs: devbus-bootcs { 51 compatible = "marvell,mvebu-devbus"; 52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; 53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; 54 #address-cells = <1>; 55 #size-cells = <1>; 56 clocks = <&coreclk 0>; 57 status = "disabled"; 58 }; 59 60 devbus_cs0: devbus-cs0 { 61 compatible = "marvell,mvebu-devbus"; 62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; 63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 clocks = <&coreclk 0>; 67 status = "disabled"; 68 }; 69 70 devbus_cs1: devbus-cs1 { 71 compatible = "marvell,mvebu-devbus"; 72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; 73 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 clocks = <&coreclk 0>; 77 status = "disabled"; 78 }; 79 80 devbus_cs2: devbus-cs2 { 81 compatible = "marvell,mvebu-devbus"; 82 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; 83 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; 84 #address-cells = <1>; 85 #size-cells = <1>; 86 clocks = <&coreclk 0>; 87 status = "disabled"; 88 }; 89 90 devbus_cs3: devbus-cs3 { 91 compatible = "marvell,mvebu-devbus"; 92 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; 93 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; 94 #address-cells = <1>; 95 #size-cells = <1>; 96 clocks = <&coreclk 0>; 97 status = "disabled"; 98 }; 99 100 internal-regs { 101 compatible = "simple-bus"; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; 105 106 sdramc: sdramc@1400 { 107 compatible = "marvell,armada-xp-sdram-controller"; 108 reg = <0x1400 0x500>; 109 }; 110 111 L2: cache-controller@8000 { 112 compatible = "arm,pl310-cache"; 113 reg = <0x8000 0x1000>; 114 cache-unified; 115 cache-level = <2>; 116 arm,double-linefill-incr = <0>; 117 arm,double-linefill-wrap = <0>; 118 arm,double-linefill = <0>; 119 prefetch-data = <1>; 120 }; 121 122 scu@c000 { 123 compatible = "arm,cortex-a9-scu"; 124 reg = <0xc000 0x58>; 125 }; 126 127 timer@c200 { 128 compatible = "arm,cortex-a9-global-timer"; 129 reg = <0xc200 0x20>; 130 interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 131 clocks = <&coreclk 2>; 132 }; 133 134 timer@c600 { 135 compatible = "arm,cortex-a9-twd-timer"; 136 reg = <0xc600 0x20>; 137 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 138 clocks = <&coreclk 2>; 139 }; 140 141 gic: interrupt-controller@d000 { 142 compatible = "arm,cortex-a9-gic"; 143 #interrupt-cells = <3>; 144 #size-cells = <0>; 145 interrupt-controller; 146 reg = <0xd000 0x1000>, 147 <0xc100 0x100>; 148 }; 149 150 i2c0: i2c@11000 { 151 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; 152 reg = <0x11000 0x20>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&coreclk 0>; 157 status = "disabled"; 158 }; 159 160 i2c1: i2c@11100 { 161 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; 162 reg = <0x11100 0x20>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&coreclk 0>; 167 status = "disabled"; 168 }; 169 170 uart0: serial@12000 { 171 compatible = "marvell,armada-38x-uart", "ns16550a"; 172 reg = <0x12000 0x100>; 173 reg-shift = <2>; 174 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 175 reg-io-width = <1>; 176 clocks = <&coreclk 0>; 177 status = "disabled"; 178 }; 179 180 uart1: serial@12100 { 181 compatible = "marvell,armada-38x-uart", "ns16550a"; 182 reg = <0x12100 0x100>; 183 reg-shift = <2>; 184 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 185 reg-io-width = <1>; 186 clocks = <&coreclk 0>; 187 status = "disabled"; 188 }; 189 190 pinctrl: pinctrl@18000 { 191 reg = <0x18000 0x20>; 192 193 ge0_rgmii_pins: ge-rgmii-pins-0 { 194 marvell,pins = "mpp6", "mpp7", "mpp8", 195 "mpp9", "mpp10", "mpp11", 196 "mpp12", "mpp13", "mpp14", 197 "mpp15", "mpp16", "mpp17"; 198 marvell,function = "ge0"; 199 }; 200 201 ge1_rgmii_pins: ge-rgmii-pins-1 { 202 marvell,pins = "mpp21", "mpp27", "mpp28", 203 "mpp29", "mpp30", "mpp31", 204 "mpp32", "mpp37", "mpp38", 205 "mpp39", "mpp40", "mpp41"; 206 marvell,function = "ge1"; 207 }; 208 209 i2c0_pins: i2c-pins-0 { 210 marvell,pins = "mpp2", "mpp3"; 211 marvell,function = "i2c0"; 212 }; 213 214 mdio_pins: mdio-pins { 215 marvell,pins = "mpp4", "mpp5"; 216 marvell,function = "ge"; 217 }; 218 219 ref_clk0_pins: ref-clk-pins-0 { 220 marvell,pins = "mpp45"; 221 marvell,function = "ref"; 222 }; 223 224 ref_clk1_pins: ref-clk-pins-1 { 225 marvell,pins = "mpp46"; 226 marvell,function = "ref"; 227 }; 228 229 spi0_pins: spi-pins-0 { 230 marvell,pins = "mpp22", "mpp23", "mpp24", 231 "mpp25"; 232 marvell,function = "spi0"; 233 }; 234 235 spi1_pins: spi-pins-1 { 236 marvell,pins = "mpp56", "mpp57", "mpp58", 237 "mpp59"; 238 marvell,function = "spi1"; 239 }; 240 241 nand_pins: nand-pins { 242 marvell,pins = "mpp22", "mpp34", "mpp23", 243 "mpp33", "mpp38", "mpp28", 244 "mpp40", "mpp42", "mpp35", 245 "mpp36", "mpp25", "mpp30", 246 "mpp32"; 247 marvell,function = "dev"; 248 }; 249 250 nand_rb: nand-rb { 251 marvell,pins = "mpp41"; 252 marvell,function = "nand"; 253 }; 254 255 uart0_pins: uart-pins-0 { 256 marvell,pins = "mpp0", "mpp1"; 257 marvell,function = "ua0"; 258 }; 259 260 uart1_pins: uart-pins-1 { 261 marvell,pins = "mpp19", "mpp20"; 262 marvell,function = "ua1"; 263 }; 264 265 sdhci_pins: sdhci-pins { 266 marvell,pins = "mpp48", "mpp49", "mpp50", 267 "mpp52", "mpp53", "mpp54", 268 "mpp55", "mpp57", "mpp58", 269 "mpp59"; 270 marvell,function = "sd0"; 271 }; 272 273 sata0_pins: sata-pins-0 { 274 marvell,pins = "mpp20"; 275 marvell,function = "sata0"; 276 }; 277 278 sata1_pins: sata-pins-1 { 279 marvell,pins = "mpp19"; 280 marvell,function = "sata1"; 281 }; 282 283 sata2_pins: sata-pins-2 { 284 marvell,pins = "mpp47"; 285 marvell,function = "sata2"; 286 }; 287 288 sata3_pins: sata-pins-3 { 289 marvell,pins = "mpp44"; 290 marvell,function = "sata3"; 291 }; 292 293 i2s_pins: i2s-pins { 294 marvell,pins = "mpp48", "mpp49", 295 "mpp50", "mpp51", 296 "mpp52", "mpp53"; 297 marvell,function = "audio"; 298 }; 299 300 spdif_pins: spdif-pins { 301 marvell,pins = "mpp51"; 302 marvell,function = "audio"; 303 }; 304 }; 305 306 gpio0: gpio@18100 { 307 compatible = "marvell,armada-370-gpio", 308 "marvell,orion-gpio"; 309 reg = <0x18100 0x40>, <0x181c0 0x08>; 310 reg-names = "gpio", "pwm"; 311 ngpios = <32>; 312 gpio-controller; 313 gpio-ranges = <&pinctrl 0 0 32>; 314 #gpio-cells = <2>; 315 #pwm-cells = <2>; 316 interrupt-controller; 317 #interrupt-cells = <2>; 318 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&coreclk 0>; 323 }; 324 325 gpio1: gpio@18140 { 326 compatible = "marvell,armada-370-gpio", 327 "marvell,orion-gpio"; 328 reg = <0x18140 0x40>, <0x181c8 0x08>; 329 reg-names = "gpio", "pwm"; 330 ngpios = <28>; 331 gpio-controller; 332 gpio-ranges = <&pinctrl 0 32 28>; 333 #gpio-cells = <2>; 334 #pwm-cells = <2>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&coreclk 0>; 342 }; 343 344 systemc: system-controller@18200 { 345 compatible = "marvell,armada-380-system-controller", 346 "marvell,armada-370-xp-system-controller"; 347 reg = <0x18200 0x100>; 348 }; 349 350 gateclk: clock-gating-control@18220 { 351 compatible = "marvell,armada-380-gating-clock"; 352 reg = <0x18220 0x4>; 353 clocks = <&coreclk 0>; 354 #clock-cells = <1>; 355 }; 356 357 comphy: phy@18300 { 358 compatible = "marvell,armada-380-comphy"; 359 reg-names = "comphy", "conf"; 360 reg = <0x18300 0x100>, <0x18460 4>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 364 comphy0: phy@0 { 365 reg = <0>; 366 #phy-cells = <1>; 367 }; 368 369 comphy1: phy@1 { 370 reg = <1>; 371 #phy-cells = <1>; 372 }; 373 374 comphy2: phy@2 { 375 reg = <2>; 376 #phy-cells = <1>; 377 }; 378 379 comphy3: phy@3 { 380 reg = <3>; 381 #phy-cells = <1>; 382 }; 383 384 comphy4: phy@4 { 385 reg = <4>; 386 #phy-cells = <1>; 387 }; 388 389 comphy5: phy@5 { 390 reg = <5>; 391 #phy-cells = <1>; 392 }; 393 }; 394 395 coreclk: mvebu-sar@18600 { 396 compatible = "marvell,armada-380-core-clock"; 397 reg = <0x18600 0x04>; 398 #clock-cells = <1>; 399 }; 400 401 mbusc: mbus-controller@20000 { 402 compatible = "marvell,mbus-controller"; 403 reg = <0x20000 0x100>, <0x20180 0x20>, 404 <0x20250 0x8>; 405 }; 406 407 mpic: interrupt-controller@20a00 { 408 compatible = "marvell,mpic"; 409 reg = <0x20a00 0x2d0>, <0x21070 0x58>; 410 #interrupt-cells = <1>; 411 #size-cells = <1>; 412 interrupt-controller; 413 msi-controller; 414 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 415 }; 416 417 timer: timer@20300 { 418 compatible = "marvell,armada-380-timer", 419 "marvell,armada-xp-timer"; 420 reg = <0x20300 0x30>, <0x21040 0x30>; 421 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 422 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 423 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 424 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 425 <&mpic 5>, 426 <&mpic 6>; 427 clocks = <&coreclk 2>, <&refclk>; 428 clock-names = "nbclk", "fixed"; 429 }; 430 431 watchdog: watchdog@20300 { 432 compatible = "marvell,armada-380-wdt"; 433 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; 434 clocks = <&coreclk 2>, <&refclk>; 435 clock-names = "nbclk", "fixed"; 436 interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 437 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 438 }; 439 440 cpurst: cpurst@20800 { 441 compatible = "marvell,armada-370-cpu-reset"; 442 reg = <0x20800 0x10>; 443 }; 444 445 mpcore-soc-ctrl@20d20 { 446 compatible = "marvell,armada-380-mpcore-soc-ctrl"; 447 reg = <0x20d20 0x6c>; 448 }; 449 450 coherencyfab: coherency-fabric@21010 { 451 compatible = "marvell,armada-380-coherency-fabric"; 452 reg = <0x21010 0x1c>; 453 }; 454 455 pmsu: pmsu@22000 { 456 compatible = "marvell,armada-380-pmsu"; 457 reg = <0x22000 0x1000>; 458 }; 459 460 /* 461 * As a special exception to the "order by 462 * register address" rule, the eth0 node is 463 * placed here to ensure that it gets 464 * registered as the first interface, since 465 * the network subsystem doesn't allow naming 466 * interfaces using DT aliases. Without this, 467 * the ordering of interfaces is different 468 * from the one used in U-Boot and the 469 * labeling of interfaces on the boards, which 470 * is very confusing for users. 471 */ 472 eth0: ethernet@70000 { 473 compatible = "marvell,armada-370-neta"; 474 reg = <0x70000 0x4000>; 475 interrupts-extended = <&mpic 8>; 476 clocks = <&gateclk 4>; 477 tx-csum-limit = <9800>; 478 status = "disabled"; 479 }; 480 481 eth1: ethernet@30000 { 482 compatible = "marvell,armada-370-neta"; 483 reg = <0x30000 0x4000>; 484 interrupts-extended = <&mpic 10>; 485 clocks = <&gateclk 3>; 486 status = "disabled"; 487 }; 488 489 eth2: ethernet@34000 { 490 compatible = "marvell,armada-370-neta"; 491 reg = <0x34000 0x4000>; 492 interrupts-extended = <&mpic 12>; 493 clocks = <&gateclk 2>; 494 status = "disabled"; 495 }; 496 497 usb0: usb@58000 { 498 compatible = "marvell,orion-ehci"; 499 reg = <0x58000 0x500>; 500 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&gateclk 18>; 502 status = "disabled"; 503 }; 504 505 xor0: xor@60800 { 506 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 507 reg = <0x60800 0x100 508 0x60a00 0x100>; 509 clocks = <&gateclk 22>; 510 status = "okay"; 511 512 xor00 { 513 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 514 dmacap,memcpy; 515 dmacap,xor; 516 }; 517 xor01 { 518 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 519 dmacap,memcpy; 520 dmacap,xor; 521 dmacap,memset; 522 }; 523 }; 524 525 xor1: xor@60900 { 526 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 527 reg = <0x60900 0x100 528 0x60b00 0x100>; 529 clocks = <&gateclk 28>; 530 status = "okay"; 531 532 xor10 { 533 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 534 dmacap,memcpy; 535 dmacap,xor; 536 }; 537 xor11 { 538 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 539 dmacap,memcpy; 540 dmacap,xor; 541 dmacap,memset; 542 }; 543 }; 544 545 mdio: mdio@72004 { 546 #address-cells = <1>; 547 #size-cells = <0>; 548 compatible = "marvell,orion-mdio"; 549 reg = <0x72004 0x4>; 550 clocks = <&gateclk 4>; 551 }; 552 553 cesa: crypto@90000 { 554 compatible = "marvell,armada-38x-crypto"; 555 reg = <0x90000 0x10000>; 556 reg-names = "regs"; 557 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&gateclk 23>, <&gateclk 21>, 560 <&gateclk 14>, <&gateclk 16>; 561 clock-names = "cesa0", "cesa1", 562 "cesaz0", "cesaz1"; 563 marvell,crypto-srams = <&crypto_sram0>, 564 <&crypto_sram1>; 565 marvell,crypto-sram-size = <0x800>; 566 }; 567 568 rtc: rtc@a3800 { 569 compatible = "marvell,armada-380-rtc"; 570 reg = <0xa3800 0x20>, <0x184a0 0x0c>; 571 reg-names = "rtc", "rtc-soc"; 572 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 573 }; 574 575 ahci0: sata@a8000 { 576 compatible = "marvell,armada-380-ahci"; 577 reg = <0xa8000 0x2000>; 578 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&gateclk 15>; 580 status = "disabled"; 581 }; 582 583 bm: bm@c8000 { 584 compatible = "marvell,armada-380-neta-bm"; 585 reg = <0xc8000 0xac>; 586 clocks = <&gateclk 13>; 587 internal-mem = <&bm_bppi>; 588 status = "disabled"; 589 }; 590 591 ahci1: sata@e0000 { 592 compatible = "marvell,armada-380-ahci"; 593 reg = <0xe0000 0x2000>; 594 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&gateclk 30>; 596 status = "disabled"; 597 }; 598 599 coredivclk: clock@e4250 { 600 compatible = "marvell,armada-380-corediv-clock"; 601 reg = <0xe4250 0xc>; 602 #clock-cells = <1>; 603 clocks = <&mainpll>; 604 clock-output-names = "nand"; 605 }; 606 607 thermal: thermal@e8078 { 608 compatible = "marvell,armada380-thermal"; 609 reg = <0xe4078 0x4>, <0xe4070 0x8>; 610 status = "okay"; 611 }; 612 613 nand_controller: nand-controller@d0000 { 614 compatible = "marvell,armada370-nand-controller"; 615 reg = <0xd0000 0x54>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&coredivclk 0>; 620 status = "disabled"; 621 }; 622 623 sdhci: sdhci@d8000 { 624 compatible = "marvell,armada-380-sdhci"; 625 reg-names = "sdhci", "mbus", "conf-sdio3"; 626 reg = <0xd8000 0x1000>, 627 <0xdc000 0x100>, 628 <0x18454 0x4>; 629 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&gateclk 17>; 631 mrvl,clk-delay-cycles = <0x1F>; 632 status = "disabled"; 633 }; 634 635 audio_controller: audio-controller@e8000 { 636 #sound-dai-cells = <1>; 637 compatible = "marvell,armada-380-audio"; 638 reg = <0xe8000 0x4000>, <0x18410 0xc>, 639 <0x18204 0x4>; 640 reg-names = "i2s_regs", "pll_regs", "soc_ctrl"; 641 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&gateclk 0>; 643 clock-names = "internal"; 644 status = "disabled"; 645 }; 646 647 usb3_0: usb3@f0000 { 648 compatible = "marvell,armada-380-xhci"; 649 reg = <0xf0000 0x4000>,<0xf4000 0x4000>; 650 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&gateclk 9>; 652 status = "disabled"; 653 }; 654 655 usb3_1: usb3@f8000 { 656 compatible = "marvell,armada-380-xhci"; 657 reg = <0xf8000 0x4000>,<0xfc000 0x4000>; 658 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&gateclk 10>; 660 status = "disabled"; 661 }; 662 }; 663 664 crypto_sram0: sa-sram0 { 665 compatible = "mmio-sram"; 666 reg = <MBUS_ID(0x09, 0x19) 0 0x800>; 667 clocks = <&gateclk 23>; 668 #address-cells = <1>; 669 #size-cells = <1>; 670 ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>; 671 }; 672 673 crypto_sram1: sa-sram1 { 674 compatible = "mmio-sram"; 675 reg = <MBUS_ID(0x09, 0x15) 0 0x800>; 676 clocks = <&gateclk 21>; 677 #address-cells = <1>; 678 #size-cells = <1>; 679 ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>; 680 }; 681 682 bm_bppi: bm-bppi { 683 compatible = "mmio-sram"; 684 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>; 685 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; 686 #address-cells = <1>; 687 #size-cells = <1>; 688 clocks = <&gateclk 13>; 689 no-memory-wc; 690 status = "disabled"; 691 }; 692 693 spi0: spi@10600 { 694 compatible = "marvell,armada-380-spi", 695 "marvell,orion-spi"; 696 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 cell-index = <0>; 700 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&coreclk 0>; 702 status = "disabled"; 703 }; 704 705 spi1: spi@10680 { 706 compatible = "marvell,armada-380-spi", 707 "marvell,orion-spi"; 708 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 cell-index = <1>; 712 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&coreclk 0>; 714 status = "disabled"; 715 }; 716 }; 717 718 clocks { 719 /* 1 GHz fixed main PLL */ 720 mainpll: mainpll { 721 compatible = "fixed-clock"; 722 #clock-cells = <0>; 723 clock-frequency = <1000000000>; 724 }; 725 726 /* 25 MHz reference crystal */ 727 refclk: oscillator { 728 compatible = "fixed-clock"; 729 #clock-cells = <0>; 730 clock-frequency = <25000000>; 731 }; 732 }; 733}; 734