1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2*724ba675SRob Herring/*
3*724ba675SRob Herring * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828)
4*724ba675SRob Herring *
5*724ba675SRob Herring *  Copyright (C) 2015 Russell King
6*724ba675SRob Herring */
7*724ba675SRob Herring
8*724ba675SRob Herring/dts-v1/;
9*724ba675SRob Herring#include "armada-388-clearfog.dtsi"
10*724ba675SRob Herring
11*724ba675SRob Herring/ {
12*724ba675SRob Herring	model = "SolidRun Clearfog A1";
13*724ba675SRob Herring	compatible = "solidrun,clearfog-a1", "marvell,armada388",
14*724ba675SRob Herring		"marvell,armada385", "marvell,armada380";
15*724ba675SRob Herring
16*724ba675SRob Herring	soc {
17*724ba675SRob Herring		internal-regs {
18*724ba675SRob Herring			usb3@f0000 {
19*724ba675SRob Herring				/* CON2, nearest CPU, USB2 only. */
20*724ba675SRob Herring				status = "okay";
21*724ba675SRob Herring			};
22*724ba675SRob Herring		};
23*724ba675SRob Herring
24*724ba675SRob Herring		pcie {
25*724ba675SRob Herring			pcie@3,0 {
26*724ba675SRob Herring				/* Port 2, Lane 0. CON2, nearest CPU. */
27*724ba675SRob Herring				reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
28*724ba675SRob Herring				status = "okay";
29*724ba675SRob Herring			};
30*724ba675SRob Herring		};
31*724ba675SRob Herring	};
32*724ba675SRob Herring
33*724ba675SRob Herring	gpio-keys {
34*724ba675SRob Herring		compatible = "gpio-keys";
35*724ba675SRob Herring		pinctrl-0 = <&rear_button_pins>;
36*724ba675SRob Herring		pinctrl-names = "default";
37*724ba675SRob Herring
38*724ba675SRob Herring		button-0 {
39*724ba675SRob Herring			/* The rear SW3 button */
40*724ba675SRob Herring			label = "Rear Button";
41*724ba675SRob Herring			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
42*724ba675SRob Herring			linux,can-disable;
43*724ba675SRob Herring			linux,code = <BTN_0>;
44*724ba675SRob Herring		};
45*724ba675SRob Herring	};
46*724ba675SRob Herring};
47*724ba675SRob Herring
48*724ba675SRob Herring&eth1 {
49*724ba675SRob Herring	/* ethernet@30000 */
50*724ba675SRob Herring	phy-mode = "1000base-x";
51*724ba675SRob Herring
52*724ba675SRob Herring	fixed-link {
53*724ba675SRob Herring		speed = <1000>;
54*724ba675SRob Herring		full-duplex;
55*724ba675SRob Herring	};
56*724ba675SRob Herring};
57*724ba675SRob Herring
58*724ba675SRob Herring&expander0 {
59*724ba675SRob Herring	/*
60*724ba675SRob Herring	 * PCA9655 GPIO expander:
61*724ba675SRob Herring	 *  0-CON3 CLKREQ#
62*724ba675SRob Herring	 *  1-CON3 PERST#
63*724ba675SRob Herring	 *  2-CON2 PERST#
64*724ba675SRob Herring	 *  3-CON3 W_DISABLE
65*724ba675SRob Herring	 *  4-CON2 CLKREQ#
66*724ba675SRob Herring	 *  5-USB3 overcurrent
67*724ba675SRob Herring	 *  6-USB3 power
68*724ba675SRob Herring	 *  7-CON2 W_DISABLE
69*724ba675SRob Herring	 *  8-JP4 P1
70*724ba675SRob Herring	 *  9-JP4 P4
71*724ba675SRob Herring	 * 10-JP4 P5
72*724ba675SRob Herring	 * 11-m.2 DEVSLP
73*724ba675SRob Herring	 * 12-SFP_LOS
74*724ba675SRob Herring	 * 13-SFP_TX_FAULT
75*724ba675SRob Herring	 * 14-SFP_TX_DISABLE
76*724ba675SRob Herring	 * 15-SFP_MOD_DEF0
77*724ba675SRob Herring	 */
78*724ba675SRob Herring	pcie2-0-clkreq-hog {
79*724ba675SRob Herring		gpio-hog;
80*724ba675SRob Herring		gpios = <4 GPIO_ACTIVE_LOW>;
81*724ba675SRob Herring		input;
82*724ba675SRob Herring		line-name = "pcie2.0-clkreq";
83*724ba675SRob Herring	};
84*724ba675SRob Herring	pcie2-0-w-disable-hog {
85*724ba675SRob Herring		gpio-hog;
86*724ba675SRob Herring		gpios = <7 GPIO_ACTIVE_LOW>;
87*724ba675SRob Herring		output-low;
88*724ba675SRob Herring		line-name = "pcie2.0-w-disable";
89*724ba675SRob Herring	};
90*724ba675SRob Herring};
91*724ba675SRob Herring
92*724ba675SRob Herring&mdio {
93*724ba675SRob Herring	status = "okay";
94*724ba675SRob Herring
95*724ba675SRob Herring	switch@4 {
96*724ba675SRob Herring		compatible = "marvell,mv88e6085";
97*724ba675SRob Herring		#address-cells = <1>;
98*724ba675SRob Herring		#size-cells = <0>;
99*724ba675SRob Herring		reg = <4>;
100*724ba675SRob Herring		pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
101*724ba675SRob Herring		pinctrl-names = "default";
102*724ba675SRob Herring
103*724ba675SRob Herring		ports {
104*724ba675SRob Herring			#address-cells = <1>;
105*724ba675SRob Herring			#size-cells = <0>;
106*724ba675SRob Herring
107*724ba675SRob Herring			port@0 {
108*724ba675SRob Herring				reg = <0>;
109*724ba675SRob Herring				label = "lan5";
110*724ba675SRob Herring			};
111*724ba675SRob Herring
112*724ba675SRob Herring			port@1 {
113*724ba675SRob Herring				reg = <1>;
114*724ba675SRob Herring				label = "lan4";
115*724ba675SRob Herring			};
116*724ba675SRob Herring
117*724ba675SRob Herring			port@2 {
118*724ba675SRob Herring				reg = <2>;
119*724ba675SRob Herring				label = "lan3";
120*724ba675SRob Herring			};
121*724ba675SRob Herring
122*724ba675SRob Herring			port@3 {
123*724ba675SRob Herring				reg = <3>;
124*724ba675SRob Herring				label = "lan2";
125*724ba675SRob Herring			};
126*724ba675SRob Herring
127*724ba675SRob Herring			port@4 {
128*724ba675SRob Herring				reg = <4>;
129*724ba675SRob Herring				label = "lan1";
130*724ba675SRob Herring			};
131*724ba675SRob Herring
132*724ba675SRob Herring			port@5 {
133*724ba675SRob Herring				reg = <5>;
134*724ba675SRob Herring				ethernet = <&eth1>;
135*724ba675SRob Herring				phy-mode = "1000base-x";
136*724ba675SRob Herring
137*724ba675SRob Herring				fixed-link {
138*724ba675SRob Herring					speed = <1000>;
139*724ba675SRob Herring					full-duplex;
140*724ba675SRob Herring				};
141*724ba675SRob Herring			};
142*724ba675SRob Herring
143*724ba675SRob Herring			port@6 {
144*724ba675SRob Herring				/* 88E1512 external phy */
145*724ba675SRob Herring				reg = <6>;
146*724ba675SRob Herring				label = "lan6";
147*724ba675SRob Herring				phy-mode = "rgmii-id";
148*724ba675SRob Herring
149*724ba675SRob Herring				fixed-link {
150*724ba675SRob Herring					speed = <1000>;
151*724ba675SRob Herring					full-duplex;
152*724ba675SRob Herring				};
153*724ba675SRob Herring			};
154*724ba675SRob Herring		};
155*724ba675SRob Herring	};
156*724ba675SRob Herring};
157*724ba675SRob Herring
158*724ba675SRob Herring&pinctrl {
159*724ba675SRob Herring	clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
160*724ba675SRob Herring		marvell,pins = "mpp46";
161*724ba675SRob Herring		marvell,function = "ref";
162*724ba675SRob Herring	};
163*724ba675SRob Herring	clearfog_dsa0_pins: clearfog-dsa0-pins {
164*724ba675SRob Herring		marvell,pins = "mpp23", "mpp41";
165*724ba675SRob Herring		marvell,function = "gpio";
166*724ba675SRob Herring	};
167*724ba675SRob Herring	clearfog_spi1_cs_pins: spi1-cs-pins {
168*724ba675SRob Herring		marvell,pins = "mpp55";
169*724ba675SRob Herring		marvell,function = "spi1";
170*724ba675SRob Herring	};
171*724ba675SRob Herring	rear_button_pins: rear-button-pins {
172*724ba675SRob Herring		marvell,pins = "mpp34";
173*724ba675SRob Herring		marvell,function = "gpio";
174*724ba675SRob Herring	};
175*724ba675SRob Herring};
176*724ba675SRob Herring
177*724ba675SRob Herring&spi1 {
178*724ba675SRob Herring	/*
179*724ba675SRob Herring	 * Add SPI CS pins for clearfog:
180*724ba675SRob Herring	 * CS0: W25Q32
181*724ba675SRob Herring	 * CS1:
182*724ba675SRob Herring	 * CS2: mikrobus
183*724ba675SRob Herring	 */
184*724ba675SRob Herring	pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
185*724ba675SRob Herring};
186