1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*724ba675SRob Herring/*
3*724ba675SRob Herring * Device Tree file for Marvell Armada 375 evaluation board
4*724ba675SRob Herring * (DB-88F6720)
5*724ba675SRob Herring *
6*724ba675SRob Herring *  Copyright (C) 2014 Marvell
7*724ba675SRob Herring *
8*724ba675SRob Herring * Gregory CLEMENT <gregory.clement@free-electrons.com>
9*724ba675SRob Herring * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10*724ba675SRob Herring */
11*724ba675SRob Herring
12*724ba675SRob Herring/dts-v1/;
13*724ba675SRob Herring#include <dt-bindings/gpio/gpio.h>
14*724ba675SRob Herring#include "armada-375.dtsi"
15*724ba675SRob Herring
16*724ba675SRob Herring/ {
17*724ba675SRob Herring	model = "Marvell Armada 375 Development Board";
18*724ba675SRob Herring	compatible = "marvell,a375-db", "marvell,armada375";
19*724ba675SRob Herring
20*724ba675SRob Herring	chosen {
21*724ba675SRob Herring		stdout-path = "serial0:115200n8";
22*724ba675SRob Herring	};
23*724ba675SRob Herring
24*724ba675SRob Herring	memory@0 {
25*724ba675SRob Herring		device_type = "memory";
26*724ba675SRob Herring		reg = <0x00000000 0x40000000>; /* 1 GB */
27*724ba675SRob Herring	};
28*724ba675SRob Herring
29*724ba675SRob Herring	soc {
30*724ba675SRob Herring		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
31*724ba675SRob Herring			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
32*724ba675SRob Herring			  MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
33*724ba675SRob Herring			  MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
34*724ba675SRob Herring
35*724ba675SRob Herring	};
36*724ba675SRob Herring};
37*724ba675SRob Herring&pciec {
38*724ba675SRob Herring	status = "okay";
39*724ba675SRob Herring};
40*724ba675SRob Herring
41*724ba675SRob Herring/*
42*724ba675SRob Herring * The two PCIe units are accessible through
43*724ba675SRob Herring * standard PCIe slots on the board.
44*724ba675SRob Herring */
45*724ba675SRob Herring&pcie0 {
46*724ba675SRob Herring	/* Port 0, Lane 0 */
47*724ba675SRob Herring	status = "okay";
48*724ba675SRob Herring};
49*724ba675SRob Herring
50*724ba675SRob Herring&pcie1 {
51*724ba675SRob Herring	/* Port 1, Lane 0 */
52*724ba675SRob Herring	status = "okay";
53*724ba675SRob Herring};
54*724ba675SRob Herring
55*724ba675SRob Herring
56*724ba675SRob Herring&spi0 {
57*724ba675SRob Herring	pinctrl-0 = <&spi0_pins>;
58*724ba675SRob Herring	pinctrl-names = "default";
59*724ba675SRob Herring
60*724ba675SRob Herring	/*
61*724ba675SRob Herring	 * SPI conflicts with NAND, so we disable it here, and
62*724ba675SRob Herring	 * select NAND as the enabled device by default.
63*724ba675SRob Herring	 */
64*724ba675SRob Herring
65*724ba675SRob Herring	status = "disabled";
66*724ba675SRob Herring
67*724ba675SRob Herring	flash@0 {
68*724ba675SRob Herring		#address-cells = <1>;
69*724ba675SRob Herring		#size-cells = <1>;
70*724ba675SRob Herring		compatible = "n25q128a13", "jedec,spi-nor";
71*724ba675SRob Herring		reg = <0>; /* Chip select 0 */
72*724ba675SRob Herring		spi-max-frequency = <108000000>;
73*724ba675SRob Herring	};
74*724ba675SRob Herring};
75*724ba675SRob Herring
76*724ba675SRob Herring&i2c0 {
77*724ba675SRob Herring	status = "okay";
78*724ba675SRob Herring	clock-frequency = <100000>;
79*724ba675SRob Herring	pinctrl-0 = <&i2c0_pins>;
80*724ba675SRob Herring	pinctrl-names = "default";
81*724ba675SRob Herring};
82*724ba675SRob Herring
83*724ba675SRob Herring&i2c1 {
84*724ba675SRob Herring	status = "okay";
85*724ba675SRob Herring	clock-frequency = <100000>;
86*724ba675SRob Herring	pinctrl-0 = <&i2c1_pins>;
87*724ba675SRob Herring	pinctrl-names = "default";
88*724ba675SRob Herring};
89*724ba675SRob Herring
90*724ba675SRob Herring&uart0 {
91*724ba675SRob Herring	status = "okay";
92*724ba675SRob Herring};
93*724ba675SRob Herring
94*724ba675SRob Herring&pinctrl {
95*724ba675SRob Herring	sdio_st_pins: sdio-st-pins {
96*724ba675SRob Herring		marvell,pins = "mpp44", "mpp45";
97*724ba675SRob Herring		marvell,function = "gpio";
98*724ba675SRob Herring	};
99*724ba675SRob Herring};
100*724ba675SRob Herring
101*724ba675SRob Herring&sata {
102*724ba675SRob Herring	status = "okay";
103*724ba675SRob Herring	nr-ports = <2>;
104*724ba675SRob Herring};
105*724ba675SRob Herring
106*724ba675SRob Herring&nand_controller {
107*724ba675SRob Herring	status = "okay";
108*724ba675SRob Herring	pinctrl-0 = <&nand_pins>;
109*724ba675SRob Herring	pinctrl-names = "default";
110*724ba675SRob Herring
111*724ba675SRob Herring	nand@0 {
112*724ba675SRob Herring		reg = <0>;
113*724ba675SRob Herring		label = "pxa3xx_nand-0";
114*724ba675SRob Herring		nand-rb = <0>;
115*724ba675SRob Herring		marvell,nand-keep-config;
116*724ba675SRob Herring		nand-on-flash-bbt;
117*724ba675SRob Herring		nand-ecc-strength = <4>;
118*724ba675SRob Herring		nand-ecc-step-size = <512>;
119*724ba675SRob Herring
120*724ba675SRob Herring		partitions {
121*724ba675SRob Herring			compatible = "fixed-partitions";
122*724ba675SRob Herring			#address-cells = <1>;
123*724ba675SRob Herring			#size-cells = <1>;
124*724ba675SRob Herring
125*724ba675SRob Herring			partition@0 {
126*724ba675SRob Herring				label = "U-Boot";
127*724ba675SRob Herring				reg = <0 0x800000>;
128*724ba675SRob Herring			};
129*724ba675SRob Herring			partition@800000 {
130*724ba675SRob Herring				label = "Linux";
131*724ba675SRob Herring				reg = <0x800000 0x800000>;
132*724ba675SRob Herring			};
133*724ba675SRob Herring			partition@1000000 {
134*724ba675SRob Herring				label = "Filesystem";
135*724ba675SRob Herring				reg = <0x1000000 0x3f000000>;
136*724ba675SRob Herring			};
137*724ba675SRob Herring		};
138*724ba675SRob Herring	};
139*724ba675SRob Herring};
140*724ba675SRob Herring
141*724ba675SRob Herring&usb1 {
142*724ba675SRob Herring	status = "okay";
143*724ba675SRob Herring};
144*724ba675SRob Herring
145*724ba675SRob Herring&usb2 {
146*724ba675SRob Herring	status = "okay";
147*724ba675SRob Herring};
148*724ba675SRob Herring
149*724ba675SRob Herring&sdio {
150*724ba675SRob Herring	pinctrl-0 = <&sdio_pins &sdio_st_pins>;
151*724ba675SRob Herring	pinctrl-names = "default";
152*724ba675SRob Herring	status = "okay";
153*724ba675SRob Herring	cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
154*724ba675SRob Herring	wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
155*724ba675SRob Herring};
156*724ba675SRob Herring
157*724ba675SRob Herring&mdio {
158*724ba675SRob Herring	phy0: ethernet-phy@0 {
159*724ba675SRob Herring		reg = <0>;
160*724ba675SRob Herring	};
161*724ba675SRob Herring
162*724ba675SRob Herring	phy3: ethernet-phy@3 {
163*724ba675SRob Herring		reg = <3>;
164*724ba675SRob Herring	};
165*724ba675SRob Herring};
166*724ba675SRob Herring
167*724ba675SRob Herring&ethernet {
168*724ba675SRob Herring	status = "okay";
169*724ba675SRob Herring};
170*724ba675SRob Herring
171*724ba675SRob Herring
172*724ba675SRob Herring&eth0 {
173*724ba675SRob Herring	status = "okay";
174*724ba675SRob Herring	phy = <&phy0>;
175*724ba675SRob Herring	phy-mode = "rgmii-id";
176*724ba675SRob Herring};
177*724ba675SRob Herring
178*724ba675SRob Herring&eth1 {
179*724ba675SRob Herring	status = "okay";
180*724ba675SRob Herring	phy = <&phy3>;
181*724ba675SRob Herring	phy-mode = "gmii";
182*724ba675SRob Herring};
183