1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* The pxa3xx skeleton simply augments the 2xx version */ 3*724ba675SRob Herring#include "pxa2xx.dtsi" 4*724ba675SRob Herring 5*724ba675SRob Herring#define MFP_PIN_PXA300(gpio) \ 6*724ba675SRob Herring ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ 7*724ba675SRob Herring (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ 8*724ba675SRob Herring (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \ 9*724ba675SRob Herring (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ 10*724ba675SRob Herring 0) 11*724ba675SRob Herring#define MFP_PIN_PXA300_2(gpio) \ 12*724ba675SRob Herring ((gpio <= 1) ? (0x674 + 4 * gpio) : \ 13*724ba675SRob Herring (gpio <= 6) ? (0x2dc + 4 * gpio) : \ 14*724ba675SRob Herring 0) 15*724ba675SRob Herring 16*724ba675SRob Herring#define MFP_PIN_PXA310(gpio) \ 17*724ba675SRob Herring ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ 18*724ba675SRob Herring (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ 19*724ba675SRob Herring (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \ 20*724ba675SRob Herring (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \ 21*724ba675SRob Herring (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ 22*724ba675SRob Herring (gpio <= 262) ? 0 : \ 23*724ba675SRob Herring (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \ 24*724ba675SRob Herring 0) 25*724ba675SRob Herring#define MFP_PIN_PXA310_2(gpio) \ 26*724ba675SRob Herring ((gpio <= 1) ? (0x674 + 4 * gpio) : \ 27*724ba675SRob Herring (gpio <= 6) ? (0x2dc + 4 * gpio) : \ 28*724ba675SRob Herring (gpio <= 10) ? (0x52c + 4 * gpio) : \ 29*724ba675SRob Herring 0) 30*724ba675SRob Herring 31*724ba675SRob Herring#define MFP_PIN_PXA320(gpio) \ 32*724ba675SRob Herring ((gpio <= 4) ? (0x0124 + 4 * gpio) : \ 33*724ba675SRob Herring (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \ 34*724ba675SRob Herring (gpio <= 10) ? (0x0458 + 4 * (gpio - 10)) : \ 35*724ba675SRob Herring (gpio <= 26) ? (0x02a0 + 4 * (gpio - 11)) : \ 36*724ba675SRob Herring (gpio <= 48) ? (0x0400 + 4 * (gpio - 27)) : \ 37*724ba675SRob Herring (gpio <= 62) ? (0x045c + 4 * (gpio - 49)) : \ 38*724ba675SRob Herring (gpio <= 73) ? (0x04b4 + 4 * (gpio - 63)) : \ 39*724ba675SRob Herring (gpio <= 98) ? (0x04f0 + 4 * (gpio - 74)) : \ 40*724ba675SRob Herring (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ 41*724ba675SRob Herring 0) 42*724ba675SRob Herring#define MFP_PIN_PXA320_2(gpio) \ 43*724ba675SRob Herring ((gpio <= 3) ? (0x674 + 4 * gpio) : \ 44*724ba675SRob Herring (gpio <= 5) ? (0x284 + 4 * gpio) : \ 45*724ba675SRob Herring 0) 46*724ba675SRob Herring 47*724ba675SRob Herring/* 48*724ba675SRob Herring * MFP Alternate functions for pins having a gpio. 49*724ba675SRob Herring * Example of use: pinctrl-single,pins = < MFP_PIN_PXA310(21) MFP_AF1 > 50*724ba675SRob Herring */ 51*724ba675SRob Herring#define MFP_AF0 (0 << 0) 52*724ba675SRob Herring#define MFP_AF1 (1 << 0) 53*724ba675SRob Herring#define MFP_AF2 (2 << 0) 54*724ba675SRob Herring#define MFP_AF3 (3 << 0) 55*724ba675SRob Herring#define MFP_AF4 (4 << 0) 56*724ba675SRob Herring#define MFP_AF5 (5 << 0) 57*724ba675SRob Herring#define MFP_AF6 (6 << 0) 58*724ba675SRob Herring 59*724ba675SRob Herring/* 60*724ba675SRob Herring * MFP drive strength functions for pins. 61*724ba675SRob Herring * Example of use: pinctrl-single,drive-strength = MFP_DS03X; 62*724ba675SRob Herring */ 63*724ba675SRob Herring#define MFP_DSMSK (0x7 << 10) 64*724ba675SRob Herring#define MFP_DS01X < (0x0 << 10) MFP_DSMSK > 65*724ba675SRob Herring#define MFP_DS02X < (0x1 << 10) MFP_DSMSK > 66*724ba675SRob Herring#define MFP_DS03X < (0x2 << 10) MFP_DSMSK > 67*724ba675SRob Herring#define MFP_DS04X < (0x3 << 10) MFP_DSMSK > 68*724ba675SRob Herring#define MFP_DS06X < (0x4 << 10) MFP_DSMSK > 69*724ba675SRob Herring#define MFP_DS08X < (0x5 << 10) MFP_DSMSK > 70*724ba675SRob Herring#define MFP_DS10X < (0x6 << 10) MFP_DSMSK > 71*724ba675SRob Herring#define MFP_DS13X < (0x7 << 10) MFP_DSMSK > 72*724ba675SRob Herring 73*724ba675SRob Herring/* 74*724ba675SRob Herring * MFP bias pull mode for pins. 75*724ba675SRob Herring * Example of use: pinctrl-single,bias-pullup = MPF_PULL_UP; 76*724ba675SRob Herring */ 77*724ba675SRob Herring#define MPF_PULL_MSK (0x7 << 13) 78*724ba675SRob Herring#define MPF_PULL_DOWN < (0x5 << 13) (0x5 << 13) 0 MPF_PULL_MSK > 79*724ba675SRob Herring#define MPF_PULL_UP < (0x6 << 13) (0x6 << 13) 0 MPF_PULL_MSK > 80*724ba675SRob Herring 81*724ba675SRob Herring/* 82*724ba675SRob Herring * MFP low power mode for pins. 83*724ba675SRob Herring * Example of use: 84*724ba675SRob Herring * pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW|MFP_LPM_EDGE_FALL); 85*724ba675SRob Herring * 86*724ba675SRob Herring * Table that determines the low power modes outputs, with actual settings 87*724ba675SRob Herring * used in parentheses for don't-care values. Except for the float output, 88*724ba675SRob Herring * the configured driven and pulled levels match, so if there is a need for 89*724ba675SRob Herring * non-LPM pulled output, the same configuration could probably be used. 90*724ba675SRob Herring * 91*724ba675SRob Herring * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel 92*724ba675SRob Herring * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) 93*724ba675SRob Herring * 94*724ba675SRob Herring * Input 0 X(0) X(0) X(0) 0 95*724ba675SRob Herring * Drive 0 0 0 0 X(1) 0 96*724ba675SRob Herring * Drive 1 0 1 X(1) 0 0 97*724ba675SRob Herring * Pull hi (1) 1 X(1) 1 0 0 98*724ba675SRob Herring * Pull lo (0) 1 X(0) 0 1 0 99*724ba675SRob Herring * Z (float) 1 X(0) 0 0 0 100*724ba675SRob Herring */ 101*724ba675SRob Herring#define MFP_LPM(x) < (x) MFP_LPM_MSK > 102*724ba675SRob Herring 103*724ba675SRob Herring#define MFP_LPM_MSK 0xe1f0 104*724ba675SRob Herring#define MFP_LPM_INPUT 0x0000 105*724ba675SRob Herring#define MFP_LPM_DRIVE_LOW 0x2000 106*724ba675SRob Herring#define MFP_LPM_DRIVE_HIGH 0x4100 107*724ba675SRob Herring#define MFP_LPM_PULL_LOW 0x2080 108*724ba675SRob Herring#define MFP_LPM_PULL_HIGH 0x4180 109*724ba675SRob Herring#define MFP_LPM_FLOAT 0x0080 110*724ba675SRob Herring 111*724ba675SRob Herring#define MFP_LPM_EDGE_NONE 0x0000 112*724ba675SRob Herring#define MFP_LPM_EDGE_RISE 0x0010 113*724ba675SRob Herring#define MFP_LPM_EDGE_FALL 0x0020 114*724ba675SRob Herring#define MFP_LPM_EDGE_BOTH 0x0030 115*724ba675SRob Herring 116*724ba675SRob Herring/ { 117*724ba675SRob Herring model = "Marvell PXA3xx familiy SoC"; 118*724ba675SRob Herring compatible = "marvell,pxa3xx"; 119*724ba675SRob Herring 120*724ba675SRob Herring pxabus { 121*724ba675SRob Herring pdma: dma-controller@40000000 { 122*724ba675SRob Herring compatible = "marvell,pdma-1.0"; 123*724ba675SRob Herring reg = <0x40000000 0x10000>; 124*724ba675SRob Herring interrupts = <25>; 125*724ba675SRob Herring #dma-cells = <2>; 126*724ba675SRob Herring /* For backwards compatibility: */ 127*724ba675SRob Herring #dma-channels = <32>; 128*724ba675SRob Herring dma-channels = <32>; 129*724ba675SRob Herring #dma-requests = <100>; 130*724ba675SRob Herring dma-requests = <100>; 131*724ba675SRob Herring status = "okay"; 132*724ba675SRob Herring }; 133*724ba675SRob Herring 134*724ba675SRob Herring pwri2c: i2c@40f500c0 { 135*724ba675SRob Herring compatible = "mrvl,pwri2c"; 136*724ba675SRob Herring reg = <0x40f500c0 0x30>; 137*724ba675SRob Herring interrupts = <6>; 138*724ba675SRob Herring clocks = <&clks CLK_PWRI2C>; 139*724ba675SRob Herring #address-cells = <0x1>; 140*724ba675SRob Herring #size-cells = <0>; 141*724ba675SRob Herring status = "disabled"; 142*724ba675SRob Herring }; 143*724ba675SRob Herring 144*724ba675SRob Herring nand_controller: nand-controller@43100000 { 145*724ba675SRob Herring compatible = "marvell,pxa3xx-nand-controller"; 146*724ba675SRob Herring reg = <0x43100000 90>; 147*724ba675SRob Herring interrupts = <45>; 148*724ba675SRob Herring clocks = <&clks CLK_NAND>; 149*724ba675SRob Herring clock-names = "core"; 150*724ba675SRob Herring dmas = <&pdma 97 3>; 151*724ba675SRob Herring dma-names = "data"; 152*724ba675SRob Herring #address-cells = <1>; 153*724ba675SRob Herring #size-cells = <0>; 154*724ba675SRob Herring status = "disabled"; 155*724ba675SRob Herring }; 156*724ba675SRob Herring 157*724ba675SRob Herring pxairq: interrupt-controller@40d00000 { 158*724ba675SRob Herring marvell,intc-priority; 159*724ba675SRob Herring marvell,intc-nr-irqs = <56>; 160*724ba675SRob Herring }; 161*724ba675SRob Herring 162*724ba675SRob Herring pinctrl: pinctrl@40e10000 { 163*724ba675SRob Herring compatible = "pinconf-single"; 164*724ba675SRob Herring reg = <0x40e10000 0xffff>; 165*724ba675SRob Herring #pinctrl-cells = <1>; 166*724ba675SRob Herring pinctrl-single,register-width = <32>; 167*724ba675SRob Herring pinctrl-single,function-mask = <0x7>; 168*724ba675SRob Herring }; 169*724ba675SRob Herring 170*724ba675SRob Herring gpio: gpio@40e00000 { 171*724ba675SRob Herring compatible = "intel,pxa3xx-gpio"; 172*724ba675SRob Herring reg = <0x40e00000 0x10000>; 173*724ba675SRob Herring clocks = <&clks CLK_GPIO>; 174*724ba675SRob Herring gpio-ranges = <&pinctrl 0 0 128>; 175*724ba675SRob Herring interrupt-names = "gpio0", "gpio1", "gpio_mux"; 176*724ba675SRob Herring interrupts = <8>, <9>, <10>; 177*724ba675SRob Herring gpio-controller; 178*724ba675SRob Herring #gpio-cells = <0x2>; 179*724ba675SRob Herring interrupt-controller; 180*724ba675SRob Herring #interrupt-cells = <0x2>; 181*724ba675SRob Herring }; 182*724ba675SRob Herring 183*724ba675SRob Herring mmc0: mmc@41100000 { 184*724ba675SRob Herring compatible = "marvell,pxa-mmc"; 185*724ba675SRob Herring reg = <0x41100000 0x1000>; 186*724ba675SRob Herring interrupts = <23>; 187*724ba675SRob Herring clocks = <&clks CLK_MMC1>; 188*724ba675SRob Herring dmas = <&pdma 21 3 189*724ba675SRob Herring &pdma 22 3>; 190*724ba675SRob Herring dma-names = "rx", "tx"; 191*724ba675SRob Herring status = "disabled"; 192*724ba675SRob Herring }; 193*724ba675SRob Herring 194*724ba675SRob Herring mmc1: mmc@42000000 { 195*724ba675SRob Herring compatible = "marvell,pxa-mmc"; 196*724ba675SRob Herring reg = <0x42000000 0x1000>; 197*724ba675SRob Herring interrupts = <41>; 198*724ba675SRob Herring clocks = <&clks CLK_MMC2>; 199*724ba675SRob Herring dmas = <&pdma 93 3 200*724ba675SRob Herring &pdma 94 3>; 201*724ba675SRob Herring dma-names = "rx", "tx"; 202*724ba675SRob Herring status = "disabled"; 203*724ba675SRob Herring }; 204*724ba675SRob Herring 205*724ba675SRob Herring mmc2: mmc@42500000 { 206*724ba675SRob Herring compatible = "marvell,pxa-mmc"; 207*724ba675SRob Herring reg = <0x42500000 0x1000>; 208*724ba675SRob Herring interrupts = <55>; 209*724ba675SRob Herring clocks = <&clks CLK_MMC3>; 210*724ba675SRob Herring dmas = <&pdma 46 3 211*724ba675SRob Herring &pdma 47 3>; 212*724ba675SRob Herring dma-names = "rx", "tx"; 213*724ba675SRob Herring status = "disabled"; 214*724ba675SRob Herring }; 215*724ba675SRob Herring 216*724ba675SRob Herring usb0: usb@4c000000 { 217*724ba675SRob Herring compatible = "marvell,pxa-ohci"; 218*724ba675SRob Herring reg = <0x4c000000 0x10000>; 219*724ba675SRob Herring interrupts = <3>; 220*724ba675SRob Herring clocks = <&clks CLK_USBH>; 221*724ba675SRob Herring status = "disabled"; 222*724ba675SRob Herring }; 223*724ba675SRob Herring 224*724ba675SRob Herring pwm0: pwm@40b00000 { 225*724ba675SRob Herring compatible = "marvell,pxa270-pwm"; 226*724ba675SRob Herring reg = <0x40b00000 0x10>; 227*724ba675SRob Herring #pwm-cells = <1>; 228*724ba675SRob Herring clocks = <&clks CLK_PWM0>; 229*724ba675SRob Herring status = "disabled"; 230*724ba675SRob Herring }; 231*724ba675SRob Herring 232*724ba675SRob Herring pwm1: pwm@40b00010 { 233*724ba675SRob Herring compatible = "marvell,pxa270-pwm"; 234*724ba675SRob Herring reg = <0x40b00010 0x10>; 235*724ba675SRob Herring #pwm-cells = <1>; 236*724ba675SRob Herring clocks = <&clks CLK_PWM1>; 237*724ba675SRob Herring status = "disabled"; 238*724ba675SRob Herring }; 239*724ba675SRob Herring 240*724ba675SRob Herring pwm2: pwm@40c00000 { 241*724ba675SRob Herring compatible = "marvell,pxa270-pwm"; 242*724ba675SRob Herring reg = <0x40c00000 0x10>; 243*724ba675SRob Herring #pwm-cells = <1>; 244*724ba675SRob Herring clocks = <&clks CLK_PWM0>; 245*724ba675SRob Herring status = "disabled"; 246*724ba675SRob Herring }; 247*724ba675SRob Herring 248*724ba675SRob Herring pwm3: pwm@40c00010 { 249*724ba675SRob Herring compatible = "marvell,pxa270-pwm"; 250*724ba675SRob Herring reg = <0x40c00010 0x10>; 251*724ba675SRob Herring #pwm-cells = <1>; 252*724ba675SRob Herring clocks = <&clks CLK_PWM1>; 253*724ba675SRob Herring status = "disabled"; 254*724ba675SRob Herring }; 255*724ba675SRob Herring 256*724ba675SRob Herring ssp1: ssp@41000000 { 257*724ba675SRob Herring compatible = "mrvl,pxa3xx-ssp"; 258*724ba675SRob Herring reg = <0x41000000 0x40>; 259*724ba675SRob Herring interrupts = <24>; 260*724ba675SRob Herring clocks = <&clks CLK_SSP1>; 261*724ba675SRob Herring status = "disabled"; 262*724ba675SRob Herring }; 263*724ba675SRob Herring 264*724ba675SRob Herring ssp2: ssp@41700000 { 265*724ba675SRob Herring compatible = "mrvl,pxa3xx-ssp"; 266*724ba675SRob Herring reg = <0x41700000 0x40>; 267*724ba675SRob Herring interrupts = <16>; 268*724ba675SRob Herring clocks = <&clks CLK_SSP2>; 269*724ba675SRob Herring status = "disabled"; 270*724ba675SRob Herring }; 271*724ba675SRob Herring 272*724ba675SRob Herring ssp3: ssp@41900000 { 273*724ba675SRob Herring compatible = "mrvl,pxa3xx-ssp"; 274*724ba675SRob Herring reg = <0x41900000 0x40>; 275*724ba675SRob Herring interrupts = <0>; 276*724ba675SRob Herring clocks = <&clks CLK_SSP3>; 277*724ba675SRob Herring status = "disabled"; 278*724ba675SRob Herring }; 279*724ba675SRob Herring 280*724ba675SRob Herring ssp4: ssp@41a00000 { 281*724ba675SRob Herring compatible = "mrvl,pxa3xx-ssp"; 282*724ba675SRob Herring reg = <0x41a00000 0x40>; 283*724ba675SRob Herring interrupts = <13>; 284*724ba675SRob Herring clocks = <&clks CLK_SSP4>; 285*724ba675SRob Herring status = "disabled"; 286*724ba675SRob Herring }; 287*724ba675SRob Herring 288*724ba675SRob Herring timer@40a00000 { 289*724ba675SRob Herring compatible = "marvell,pxa-timer"; 290*724ba675SRob Herring reg = <0x40a00000 0x20>; 291*724ba675SRob Herring interrupts = <26>; 292*724ba675SRob Herring clocks = <&clks CLK_OSTIMER>; 293*724ba675SRob Herring status = "okay"; 294*724ba675SRob Herring }; 295*724ba675SRob Herring 296*724ba675SRob Herring gcu: display-controller@54000000 { 297*724ba675SRob Herring compatible = "marvell,pxa300-gcu"; 298*724ba675SRob Herring reg = <0x54000000 0x1000>; 299*724ba675SRob Herring interrupts = <39>; 300*724ba675SRob Herring clocks = <&clks CLK_PXA300_GCU>; 301*724ba675SRob Herring status = "disabled"; 302*724ba675SRob Herring }; 303*724ba675SRob Herring }; 304*724ba675SRob Herring 305*724ba675SRob Herring clocks { 306*724ba675SRob Herring /* 307*724ba675SRob Herring * The muxing of external clocks/internal dividers for osc* clock 308*724ba675SRob Herring * sources has been hidden under the carpet by now. 309*724ba675SRob Herring */ 310*724ba675SRob Herring #address-cells = <1>; 311*724ba675SRob Herring #size-cells = <1>; 312*724ba675SRob Herring ranges; 313*724ba675SRob Herring 314*724ba675SRob Herring clks: clocks { 315*724ba675SRob Herring compatible = "marvell,pxa300-clocks"; 316*724ba675SRob Herring #clock-cells = <1>; 317*724ba675SRob Herring status = "okay"; 318*724ba675SRob Herring }; 319*724ba675SRob Herring }; 320*724ba675SRob Herring}; 321