1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-or-later 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (C) 2016 Robert Jarzmik <robert.jarzmik@free.fr> 4*724ba675SRob Herring */ 5*724ba675SRob Herring#include "pxa2xx.dtsi" 6*724ba675SRob Herring#include "dt-bindings/clock/pxa-clock.h" 7*724ba675SRob Herring 8*724ba675SRob Herring/ { 9*724ba675SRob Herring model = "Marvell PXA25x family SoC"; 10*724ba675SRob Herring compatible = "marvell,pxa250"; 11*724ba675SRob Herring 12*724ba675SRob Herring clocks { 13*724ba675SRob Herring /* 14*724ba675SRob Herring * The muxing of external clocks/internal dividers for osc* clock 15*724ba675SRob Herring * sources has been hidden under the carpet by now. 16*724ba675SRob Herring */ 17*724ba675SRob Herring #address-cells = <1>; 18*724ba675SRob Herring #size-cells = <1>; 19*724ba675SRob Herring ranges; 20*724ba675SRob Herring 21*724ba675SRob Herring clks: pxa2xx_clks@41300004 { 22*724ba675SRob Herring compatible = "marvell,pxa250-core-clocks"; 23*724ba675SRob Herring #clock-cells = <1>; 24*724ba675SRob Herring status = "okay"; 25*724ba675SRob Herring }; 26*724ba675SRob Herring 27*724ba675SRob Herring /* timer oscillator */ 28*724ba675SRob Herring clktimer: oscillator { 29*724ba675SRob Herring compatible = "fixed-clock"; 30*724ba675SRob Herring #clock-cells = <0>; 31*724ba675SRob Herring clock-frequency = <3686400>; 32*724ba675SRob Herring clock-output-names = "ostimer"; 33*724ba675SRob Herring }; 34*724ba675SRob Herring }; 35*724ba675SRob Herring 36*724ba675SRob Herring pxabus { 37*724ba675SRob Herring pdma: dma-controller@40000000 { 38*724ba675SRob Herring compatible = "marvell,pdma-1.0"; 39*724ba675SRob Herring reg = <0x40000000 0x10000>; 40*724ba675SRob Herring interrupts = <25>; 41*724ba675SRob Herring #dma-cells = <2>; 42*724ba675SRob Herring /* For backwards compatibility: */ 43*724ba675SRob Herring #dma-channels = <16>; 44*724ba675SRob Herring dma-channels = <16>; 45*724ba675SRob Herring #dma-requests = <40>; 46*724ba675SRob Herring dma-requests = <40>; 47*724ba675SRob Herring status = "okay"; 48*724ba675SRob Herring }; 49*724ba675SRob Herring 50*724ba675SRob Herring pxairq: interrupt-controller@40d00000 { 51*724ba675SRob Herring marvell,intc-priority; 52*724ba675SRob Herring marvell,intc-nr-irqs = <32>; 53*724ba675SRob Herring }; 54*724ba675SRob Herring 55*724ba675SRob Herring pinctrl: pinctrl@40e00000 { 56*724ba675SRob Herring reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4 57*724ba675SRob Herring 0x40f00020 0x10>; 58*724ba675SRob Herring compatible = "marvell,pxa25x-pinctrl"; 59*724ba675SRob Herring }; 60*724ba675SRob Herring 61*724ba675SRob Herring gpio: gpio@40e00000 { 62*724ba675SRob Herring compatible = "intel,pxa25x-gpio"; 63*724ba675SRob Herring gpio-ranges = <&pinctrl 0 0 84>; 64*724ba675SRob Herring clocks = <&clks CLK_NONE>; 65*724ba675SRob Herring }; 66*724ba675SRob Herring 67*724ba675SRob Herring pwm0: pwm@40b00000 { 68*724ba675SRob Herring compatible = "marvell,pxa250-pwm"; 69*724ba675SRob Herring reg = <0x40b00000 0x10>; 70*724ba675SRob Herring #pwm-cells = <1>; 71*724ba675SRob Herring clocks = <&clks CLK_PWM0>; 72*724ba675SRob Herring }; 73*724ba675SRob Herring 74*724ba675SRob Herring pwm1: pwm@40b00010 { 75*724ba675SRob Herring compatible = "marvell,pxa250-pwm"; 76*724ba675SRob Herring reg = <0x40b00010 0x10>; 77*724ba675SRob Herring #pwm-cells = <1>; 78*724ba675SRob Herring clocks = <&clks CLK_PWM1>; 79*724ba675SRob Herring }; 80*724ba675SRob Herring 81*724ba675SRob Herring rtc@40900000 { 82*724ba675SRob Herring clocks = <&clks CLK_OSC32k768>; 83*724ba675SRob Herring }; 84*724ba675SRob Herring }; 85*724ba675SRob Herring 86*724ba675SRob Herring timer@40a00000 { 87*724ba675SRob Herring compatible = "marvell,pxa-timer"; 88*724ba675SRob Herring reg = <0x40a00000 0x20>; 89*724ba675SRob Herring interrupts = <26>; 90*724ba675SRob Herring clocks = <&clktimer>; 91*724ba675SRob Herring status = "okay"; 92*724ba675SRob Herring }; 93*724ba675SRob Herring 94*724ba675SRob Herring pxa250_opp_table: opp_table0 { 95*724ba675SRob Herring compatible = "operating-points-v2"; 96*724ba675SRob Herring 97*724ba675SRob Herring opp-99532800 { 98*724ba675SRob Herring opp-hz = /bits/ 64 <99532800>; 99*724ba675SRob Herring opp-microvolt = <1000000 950000 1650000>; 100*724ba675SRob Herring clock-latency-ns = <20>; 101*724ba675SRob Herring }; 102*724ba675SRob Herring opp-199065600 { 103*724ba675SRob Herring opp-hz = /bits/ 64 <199065600>; 104*724ba675SRob Herring opp-microvolt = <1000000 950000 1650000>; 105*724ba675SRob Herring clock-latency-ns = <20>; 106*724ba675SRob Herring }; 107*724ba675SRob Herring opp-298598400 { 108*724ba675SRob Herring opp-hz = /bits/ 64 <298598400>; 109*724ba675SRob Herring opp-microvolt = <1100000 1045000 1650000>; 110*724ba675SRob Herring clock-latency-ns = <20>; 111*724ba675SRob Herring }; 112*724ba675SRob Herring opp-398131200 { 113*724ba675SRob Herring opp-hz = /bits/ 64 <398131200>; 114*724ba675SRob Herring opp-microvolt = <1300000 1235000 1650000>; 115*724ba675SRob Herring clock-latency-ns = <20>; 116*724ba675SRob Herring }; 117*724ba675SRob Herring }; 118*724ba675SRob Herring}; 119