1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-or-later
2*724ba675SRob Herring/*
3*724ba675SRob Herring * arch/arm/boot/dts/axm55xx.dtsi
4*724ba675SRob Herring *
5*724ba675SRob Herring * Copyright (C) 2013 LSI
6*724ba675SRob Herring */
7*724ba675SRob Herring
8*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h>
9*724ba675SRob Herring#include <dt-bindings/clock/lsi,axm5516-clks.h>
10*724ba675SRob Herring
11*724ba675SRob Herring/ {
12*724ba675SRob Herring	#address-cells = <2>;
13*724ba675SRob Herring	#size-cells = <2>;
14*724ba675SRob Herring	interrupt-parent = <&gic>;
15*724ba675SRob Herring
16*724ba675SRob Herring	aliases {
17*724ba675SRob Herring		serial0	  = &serial0;
18*724ba675SRob Herring		serial1   = &serial1;
19*724ba675SRob Herring		serial2	  = &serial2;
20*724ba675SRob Herring		serial3	  = &serial3;
21*724ba675SRob Herring		timer	  = &timer0;
22*724ba675SRob Herring	};
23*724ba675SRob Herring
24*724ba675SRob Herring	clocks {
25*724ba675SRob Herring		compatible = "simple-bus";
26*724ba675SRob Herring		#address-cells = <2>;
27*724ba675SRob Herring		#size-cells = <2>;
28*724ba675SRob Herring		ranges;
29*724ba675SRob Herring
30*724ba675SRob Herring		clk_ref0: clk_ref0 {
31*724ba675SRob Herring			compatible = "fixed-clock";
32*724ba675SRob Herring			#clock-cells = <0>;
33*724ba675SRob Herring			clock-frequency = <125000000>;
34*724ba675SRob Herring		};
35*724ba675SRob Herring
36*724ba675SRob Herring		clk_ref1: clk_ref1 {
37*724ba675SRob Herring			compatible = "fixed-clock";
38*724ba675SRob Herring			#clock-cells = <0>;
39*724ba675SRob Herring			clock-frequency = <125000000>;
40*724ba675SRob Herring		};
41*724ba675SRob Herring
42*724ba675SRob Herring		clk_ref2: clk_ref2 {
43*724ba675SRob Herring			compatible = "fixed-clock";
44*724ba675SRob Herring			#clock-cells = <0>;
45*724ba675SRob Herring			clock-frequency = <125000000>;
46*724ba675SRob Herring		};
47*724ba675SRob Herring
48*724ba675SRob Herring		clks: clock-controller@2010020000 {
49*724ba675SRob Herring			compatible = "lsi,axm5516-clks";
50*724ba675SRob Herring			#clock-cells = <1>;
51*724ba675SRob Herring			reg = <0x20 0x10020000 0 0x20000>;
52*724ba675SRob Herring		};
53*724ba675SRob Herring	};
54*724ba675SRob Herring
55*724ba675SRob Herring	gic: interrupt-controller@2001001000 {
56*724ba675SRob Herring		compatible = "arm,cortex-a15-gic";
57*724ba675SRob Herring		#interrupt-cells = <3>;
58*724ba675SRob Herring		#address-cells = <0>;
59*724ba675SRob Herring		interrupt-controller;
60*724ba675SRob Herring		reg = <0x20 0x01001000 0 0x1000>,
61*724ba675SRob Herring		      <0x20 0x01002000 0 0x2000>,
62*724ba675SRob Herring		      <0x20 0x01004000 0 0x2000>,
63*724ba675SRob Herring		      <0x20 0x01006000 0 0x2000>;
64*724ba675SRob Herring		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
65*724ba675SRob Herring				IRQ_TYPE_LEVEL_HIGH)>;
66*724ba675SRob Herring	};
67*724ba675SRob Herring
68*724ba675SRob Herring	timer {
69*724ba675SRob Herring		compatible = "arm,armv7-timer";
70*724ba675SRob Herring		interrupts =
71*724ba675SRob Herring			<GIC_PPI 13
72*724ba675SRob Herring				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
73*724ba675SRob Herring			<GIC_PPI 14
74*724ba675SRob Herring				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
75*724ba675SRob Herring			<GIC_PPI 11
76*724ba675SRob Herring				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
77*724ba675SRob Herring			<GIC_PPI 10
78*724ba675SRob Herring				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
79*724ba675SRob Herring	};
80*724ba675SRob Herring
81*724ba675SRob Herring
82*724ba675SRob Herring	pmu {
83*724ba675SRob Herring		compatible = "arm,cortex-a15-pmu";
84*724ba675SRob Herring		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
85*724ba675SRob Herring	};
86*724ba675SRob Herring
87*724ba675SRob Herring	soc {
88*724ba675SRob Herring		compatible = "simple-bus";
89*724ba675SRob Herring		device_type = "soc";
90*724ba675SRob Herring		#address-cells = <2>;
91*724ba675SRob Herring		#size-cells = <2>;
92*724ba675SRob Herring		interrupt-parent = <&gic>;
93*724ba675SRob Herring		ranges;
94*724ba675SRob Herring
95*724ba675SRob Herring		syscon: syscon@2010030000 {
96*724ba675SRob Herring			compatible = "lsi,axxia-syscon", "syscon";
97*724ba675SRob Herring			reg = <0x20 0x10030000 0 0x2000>;
98*724ba675SRob Herring		};
99*724ba675SRob Herring
100*724ba675SRob Herring		reset: reset@2010031000 {
101*724ba675SRob Herring			compatible = "lsi,axm55xx-reset";
102*724ba675SRob Herring			syscon = <&syscon>;
103*724ba675SRob Herring		};
104*724ba675SRob Herring
105*724ba675SRob Herring		amba {
106*724ba675SRob Herring			compatible = "simple-bus";
107*724ba675SRob Herring			#address-cells = <2>;
108*724ba675SRob Herring			#size-cells = <2>;
109*724ba675SRob Herring			ranges;
110*724ba675SRob Herring
111*724ba675SRob Herring			serial0: serial@2010080000 {
112*724ba675SRob Herring				compatible = "arm,pl011", "arm,primecell";
113*724ba675SRob Herring				reg = <0x20 0x10080000 0 0x1000>;
114*724ba675SRob Herring				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
115*724ba675SRob Herring				clocks = <&clks AXXIA_CLK_PER>;
116*724ba675SRob Herring				clock-names = "apb_pclk";
117*724ba675SRob Herring				status = "disabled";
118*724ba675SRob Herring			};
119*724ba675SRob Herring
120*724ba675SRob Herring			serial1: serial@2010081000 {
121*724ba675SRob Herring				compatible = "arm,pl011", "arm,primecell";
122*724ba675SRob Herring				reg = <0x20 0x10081000 0 0x1000>;
123*724ba675SRob Herring				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
124*724ba675SRob Herring				clocks = <&clks AXXIA_CLK_PER>;
125*724ba675SRob Herring				clock-names = "apb_pclk";
126*724ba675SRob Herring				status = "disabled";
127*724ba675SRob Herring			};
128*724ba675SRob Herring
129*724ba675SRob Herring			serial2: serial@2010082000 {
130*724ba675SRob Herring				compatible = "arm,pl011", "arm,primecell";
131*724ba675SRob Herring				reg = <0x20 0x10082000 0 0x1000>;
132*724ba675SRob Herring				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
133*724ba675SRob Herring				clocks = <&clks AXXIA_CLK_PER>;
134*724ba675SRob Herring				clock-names = "apb_pclk";
135*724ba675SRob Herring				status = "disabled";
136*724ba675SRob Herring			};
137*724ba675SRob Herring
138*724ba675SRob Herring			serial3: serial@2010083000 {
139*724ba675SRob Herring				compatible = "arm,pl011", "arm,primecell";
140*724ba675SRob Herring				reg = <0x20 0x10083000 0 0x1000>;
141*724ba675SRob Herring				interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
142*724ba675SRob Herring				clocks = <&clks AXXIA_CLK_PER>;
143*724ba675SRob Herring				clock-names = "apb_pclk";
144*724ba675SRob Herring				status = "disabled";
145*724ba675SRob Herring			};
146*724ba675SRob Herring
147*724ba675SRob Herring			timer0: timer@2010091000 {
148*724ba675SRob Herring				compatible = "arm,sp804", "arm,primecell";
149*724ba675SRob Herring				reg = <0x20 0x10091000 0 0x1000>;
150*724ba675SRob Herring				interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
151*724ba675SRob Herring					     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
152*724ba675SRob Herring					     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
153*724ba675SRob Herring					     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
154*724ba675SRob Herring					     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
155*724ba675SRob Herring					     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
156*724ba675SRob Herring					     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
157*724ba675SRob Herring					     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
158*724ba675SRob Herring					     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
159*724ba675SRob Herring				clocks = <&clks AXXIA_CLK_PER>;
160*724ba675SRob Herring				clock-names = "apb_pclk";
161*724ba675SRob Herring				status = "okay";
162*724ba675SRob Herring			};
163*724ba675SRob Herring
164*724ba675SRob Herring			gpio0: gpio@2010092000 {
165*724ba675SRob Herring				#gpio-cells = <2>;
166*724ba675SRob Herring				compatible = "arm,pl061", "arm,primecell";
167*724ba675SRob Herring				gpio-controller;
168*724ba675SRob Herring				reg = <0x20 0x10092000 0x00 0x1000>;
169*724ba675SRob Herring				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
170*724ba675SRob Herring					     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
171*724ba675SRob Herring					     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
172*724ba675SRob Herring					     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
173*724ba675SRob Herring					     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
174*724ba675SRob Herring					     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
175*724ba675SRob Herring					     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
176*724ba675SRob Herring					     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
177*724ba675SRob Herring				clocks = <&clks AXXIA_CLK_PER>;
178*724ba675SRob Herring				clock-names = "apb_pclk";
179*724ba675SRob Herring				status = "disabled";
180*724ba675SRob Herring			};
181*724ba675SRob Herring
182*724ba675SRob Herring			gpio1: gpio@2010093000 {
183*724ba675SRob Herring				#gpio-cells = <2>;
184*724ba675SRob Herring				compatible = "arm,pl061", "arm,primecell";
185*724ba675SRob Herring				gpio-controller;
186*724ba675SRob Herring				reg = <0x20 0x10093000 0x00 0x1000>;
187*724ba675SRob Herring				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
188*724ba675SRob Herring				clocks = <&clks AXXIA_CLK_PER>;
189*724ba675SRob Herring				clock-names = "apb_pclk";
190*724ba675SRob Herring				status = "disabled";
191*724ba675SRob Herring			};
192*724ba675SRob Herring		};
193*724ba675SRob Herring	};
194*724ba675SRob Herring};
195*724ba675SRob Herring
196*724ba675SRob Herring/*
197*724ba675SRob Herring  Local Variables:
198*724ba675SRob Herring  mode: C
199*724ba675SRob Herring  End:
200*724ba675SRob Herring*/
201