1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (c) 2013-2014 Linaro Ltd. 4*724ba675SRob Herring * Copyright (c) 2013-2014 HiSilicon Limited. 5*724ba675SRob Herring */ 6*724ba675SRob Herring 7*724ba675SRob Herring#include <dt-bindings/clock/hix5hd2-clock.h> 8*724ba675SRob Herring 9*724ba675SRob Herring/ { 10*724ba675SRob Herring #address-cells = <1>; 11*724ba675SRob Herring #size-cells = <1>; 12*724ba675SRob Herring 13*724ba675SRob Herring aliases { 14*724ba675SRob Herring serial0 = &uart0; 15*724ba675SRob Herring }; 16*724ba675SRob Herring 17*724ba675SRob Herring gic: interrupt-controller@f8a01000 { 18*724ba675SRob Herring compatible = "arm,cortex-a9-gic"; 19*724ba675SRob Herring #interrupt-cells = <3>; 20*724ba675SRob Herring #address-cells = <0>; 21*724ba675SRob Herring interrupt-controller; 22*724ba675SRob Herring /* gic dist base, gic cpu base */ 23*724ba675SRob Herring reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>; 24*724ba675SRob Herring }; 25*724ba675SRob Herring 26*724ba675SRob Herring soc { 27*724ba675SRob Herring #address-cells = <1>; 28*724ba675SRob Herring #size-cells = <1>; 29*724ba675SRob Herring compatible = "simple-bus"; 30*724ba675SRob Herring interrupt-parent = <&gic>; 31*724ba675SRob Herring ranges = <0 0xf8000000 0x8000000>; 32*724ba675SRob Herring 33*724ba675SRob Herring amba-bus { 34*724ba675SRob Herring #address-cells = <1>; 35*724ba675SRob Herring #size-cells = <1>; 36*724ba675SRob Herring compatible = "simple-bus"; 37*724ba675SRob Herring ranges; 38*724ba675SRob Herring 39*724ba675SRob Herring timer0: timer@2000 { 40*724ba675SRob Herring compatible = "arm,sp804", "arm,primecell"; 41*724ba675SRob Herring reg = <0x00002000 0x1000>; 42*724ba675SRob Herring /* timer00 & timer01 */ 43*724ba675SRob Herring interrupts = <0 24 4>; 44*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_24M>; 45*724ba675SRob Herring status = "disabled"; 46*724ba675SRob Herring }; 47*724ba675SRob Herring 48*724ba675SRob Herring timer1: timer@a29000 { 49*724ba675SRob Herring /* 50*724ba675SRob Herring * Only used in NORMAL state, not available ins 51*724ba675SRob Herring * SLOW or DOZE state. 52*724ba675SRob Herring * The rate is fixed in 24MHz. 53*724ba675SRob Herring */ 54*724ba675SRob Herring compatible = "arm,sp804", "arm,primecell"; 55*724ba675SRob Herring reg = <0x00a29000 0x1000>; 56*724ba675SRob Herring /* timer10 & timer11 */ 57*724ba675SRob Herring interrupts = <0 25 4>; 58*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_24M>; 59*724ba675SRob Herring status = "disabled"; 60*724ba675SRob Herring }; 61*724ba675SRob Herring 62*724ba675SRob Herring timer2: timer@a2a000 { 63*724ba675SRob Herring compatible = "arm,sp804", "arm,primecell"; 64*724ba675SRob Herring reg = <0x00a2a000 0x1000>; 65*724ba675SRob Herring /* timer20 & timer21 */ 66*724ba675SRob Herring interrupts = <0 26 4>; 67*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_24M>; 68*724ba675SRob Herring status = "disabled"; 69*724ba675SRob Herring }; 70*724ba675SRob Herring 71*724ba675SRob Herring timer3: timer@a2b000 { 72*724ba675SRob Herring compatible = "arm,sp804", "arm,primecell"; 73*724ba675SRob Herring reg = <0x00a2b000 0x1000>; 74*724ba675SRob Herring /* timer30 & timer31 */ 75*724ba675SRob Herring interrupts = <0 27 4>; 76*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_24M>; 77*724ba675SRob Herring status = "disabled"; 78*724ba675SRob Herring }; 79*724ba675SRob Herring 80*724ba675SRob Herring timer4: timer@a81000 { 81*724ba675SRob Herring compatible = "arm,sp804", "arm,primecell"; 82*724ba675SRob Herring reg = <0x00a81000 0x1000>; 83*724ba675SRob Herring /* timer30 & timer31 */ 84*724ba675SRob Herring interrupts = <0 28 4>; 85*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_24M>; 86*724ba675SRob Herring status = "disabled"; 87*724ba675SRob Herring }; 88*724ba675SRob Herring 89*724ba675SRob Herring uart0: serial@b00000 { 90*724ba675SRob Herring compatible = "arm,pl011", "arm,primecell"; 91*724ba675SRob Herring reg = <0x00b00000 0x1000>; 92*724ba675SRob Herring interrupts = <0 49 4>; 93*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; 94*724ba675SRob Herring clock-names = "uartclk", "apb_pclk"; 95*724ba675SRob Herring status = "disabled"; 96*724ba675SRob Herring }; 97*724ba675SRob Herring 98*724ba675SRob Herring uart1: serial@6000 { 99*724ba675SRob Herring compatible = "arm,pl011", "arm,primecell"; 100*724ba675SRob Herring reg = <0x00006000 0x1000>; 101*724ba675SRob Herring interrupts = <0 50 4>; 102*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; 103*724ba675SRob Herring clock-names = "uartclk", "apb_pclk"; 104*724ba675SRob Herring status = "disabled"; 105*724ba675SRob Herring }; 106*724ba675SRob Herring 107*724ba675SRob Herring uart2: serial@b02000 { 108*724ba675SRob Herring compatible = "arm,pl011", "arm,primecell"; 109*724ba675SRob Herring reg = <0x00b02000 0x1000>; 110*724ba675SRob Herring interrupts = <0 51 4>; 111*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; 112*724ba675SRob Herring clock-names = "uartclk", "apb_pclk"; 113*724ba675SRob Herring status = "disabled"; 114*724ba675SRob Herring }; 115*724ba675SRob Herring 116*724ba675SRob Herring uart3: serial@b03000 { 117*724ba675SRob Herring compatible = "arm,pl011", "arm,primecell"; 118*724ba675SRob Herring reg = <0x00b03000 0x1000>; 119*724ba675SRob Herring interrupts = <0 52 4>; 120*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; 121*724ba675SRob Herring clock-names = "uartclk", "apb_pclk"; 122*724ba675SRob Herring status = "disabled"; 123*724ba675SRob Herring }; 124*724ba675SRob Herring 125*724ba675SRob Herring uart4: serial@b04000 { 126*724ba675SRob Herring compatible = "arm,pl011", "arm,primecell"; 127*724ba675SRob Herring reg = <0xb04000 0x1000>; 128*724ba675SRob Herring interrupts = <0 53 4>; 129*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; 130*724ba675SRob Herring clock-names = "uartclk", "apb_pclk"; 131*724ba675SRob Herring status = "disabled"; 132*724ba675SRob Herring }; 133*724ba675SRob Herring 134*724ba675SRob Herring gpio0: gpio@b20000 { 135*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 136*724ba675SRob Herring reg = <0xb20000 0x1000>; 137*724ba675SRob Herring interrupts = <0 108 0x4>; 138*724ba675SRob Herring gpio-controller; 139*724ba675SRob Herring #gpio-cells = <2>; 140*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_100M>; 141*724ba675SRob Herring clock-names = "apb_pclk"; 142*724ba675SRob Herring interrupt-controller; 143*724ba675SRob Herring #interrupt-cells = <2>; 144*724ba675SRob Herring status = "disabled"; 145*724ba675SRob Herring }; 146*724ba675SRob Herring 147*724ba675SRob Herring gpio1: gpio@b21000 { 148*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 149*724ba675SRob Herring reg = <0xb21000 0x1000>; 150*724ba675SRob Herring interrupts = <0 109 0x4>; 151*724ba675SRob Herring gpio-controller; 152*724ba675SRob Herring #gpio-cells = <2>; 153*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_100M>; 154*724ba675SRob Herring clock-names = "apb_pclk"; 155*724ba675SRob Herring interrupt-controller; 156*724ba675SRob Herring #interrupt-cells = <2>; 157*724ba675SRob Herring status = "disabled"; 158*724ba675SRob Herring }; 159*724ba675SRob Herring 160*724ba675SRob Herring gpio2: gpio@b22000 { 161*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 162*724ba675SRob Herring reg = <0xb22000 0x1000>; 163*724ba675SRob Herring interrupts = <0 110 0x4>; 164*724ba675SRob Herring gpio-controller; 165*724ba675SRob Herring #gpio-cells = <2>; 166*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_100M>; 167*724ba675SRob Herring clock-names = "apb_pclk"; 168*724ba675SRob Herring interrupt-controller; 169*724ba675SRob Herring #interrupt-cells = <2>; 170*724ba675SRob Herring status = "disabled"; 171*724ba675SRob Herring }; 172*724ba675SRob Herring 173*724ba675SRob Herring gpio3: gpio@b23000 { 174*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 175*724ba675SRob Herring reg = <0xb23000 0x1000>; 176*724ba675SRob Herring interrupts = <0 111 0x4>; 177*724ba675SRob Herring gpio-controller; 178*724ba675SRob Herring #gpio-cells = <2>; 179*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_100M>; 180*724ba675SRob Herring clock-names = "apb_pclk"; 181*724ba675SRob Herring interrupt-controller; 182*724ba675SRob Herring #interrupt-cells = <2>; 183*724ba675SRob Herring status = "disabled"; 184*724ba675SRob Herring }; 185*724ba675SRob Herring 186*724ba675SRob Herring gpio4: gpio@b24000 { 187*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 188*724ba675SRob Herring reg = <0xb24000 0x1000>; 189*724ba675SRob Herring interrupts = <0 112 0x4>; 190*724ba675SRob Herring gpio-controller; 191*724ba675SRob Herring #gpio-cells = <2>; 192*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_100M>; 193*724ba675SRob Herring clock-names = "apb_pclk"; 194*724ba675SRob Herring interrupt-controller; 195*724ba675SRob Herring #interrupt-cells = <2>; 196*724ba675SRob Herring status = "disabled"; 197*724ba675SRob Herring }; 198*724ba675SRob Herring 199*724ba675SRob Herring gpio5: gpio@4000 { 200*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 201*724ba675SRob Herring reg = <0x004000 0x1000>; 202*724ba675SRob Herring interrupts = <0 113 0x4>; 203*724ba675SRob Herring gpio-controller; 204*724ba675SRob Herring #gpio-cells = <2>; 205*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_100M>; 206*724ba675SRob Herring clock-names = "apb_pclk"; 207*724ba675SRob Herring interrupt-controller; 208*724ba675SRob Herring #interrupt-cells = <2>; 209*724ba675SRob Herring status = "disabled"; 210*724ba675SRob Herring }; 211*724ba675SRob Herring 212*724ba675SRob Herring gpio6: gpio@b26000 { 213*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 214*724ba675SRob Herring reg = <0xb26000 0x1000>; 215*724ba675SRob Herring interrupts = <0 114 0x4>; 216*724ba675SRob Herring gpio-controller; 217*724ba675SRob Herring #gpio-cells = <2>; 218*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_100M>; 219*724ba675SRob Herring clock-names = "apb_pclk"; 220*724ba675SRob Herring interrupt-controller; 221*724ba675SRob Herring #interrupt-cells = <2>; 222*724ba675SRob Herring status = "disabled"; 223*724ba675SRob Herring }; 224*724ba675SRob Herring 225*724ba675SRob Herring gpio7: gpio@b27000 { 226*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 227*724ba675SRob Herring reg = <0xb27000 0x1000>; 228*724ba675SRob Herring interrupts = <0 115 0x4>; 229*724ba675SRob Herring gpio-controller; 230*724ba675SRob Herring #gpio-cells = <2>; 231*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_100M>; 232*724ba675SRob Herring clock-names = "apb_pclk"; 233*724ba675SRob Herring interrupt-controller; 234*724ba675SRob Herring #interrupt-cells = <2>; 235*724ba675SRob Herring status = "disabled"; 236*724ba675SRob Herring }; 237*724ba675SRob Herring 238*724ba675SRob Herring gpio8: gpio@b28000 { 239*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 240*724ba675SRob Herring reg = <0xb28000 0x1000>; 241*724ba675SRob Herring interrupts = <0 116 0x4>; 242*724ba675SRob Herring gpio-controller; 243*724ba675SRob Herring #gpio-cells = <2>; 244*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_100M>; 245*724ba675SRob Herring clock-names = "apb_pclk"; 246*724ba675SRob Herring interrupt-controller; 247*724ba675SRob Herring #interrupt-cells = <2>; 248*724ba675SRob Herring status = "disabled"; 249*724ba675SRob Herring }; 250*724ba675SRob Herring 251*724ba675SRob Herring gpio9: gpio@b29000 { 252*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 253*724ba675SRob Herring reg = <0xb29000 0x1000>; 254*724ba675SRob Herring interrupts = <0 117 0x4>; 255*724ba675SRob Herring gpio-controller; 256*724ba675SRob Herring #gpio-cells = <2>; 257*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_100M>; 258*724ba675SRob Herring clock-names = "apb_pclk"; 259*724ba675SRob Herring interrupt-controller; 260*724ba675SRob Herring #interrupt-cells = <2>; 261*724ba675SRob Herring status = "disabled"; 262*724ba675SRob Herring }; 263*724ba675SRob Herring 264*724ba675SRob Herring gpio10: gpio@b2a000 { 265*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 266*724ba675SRob Herring reg = <0xb2a000 0x1000>; 267*724ba675SRob Herring interrupts = <0 118 0x4>; 268*724ba675SRob Herring gpio-controller; 269*724ba675SRob Herring #gpio-cells = <2>; 270*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_100M>; 271*724ba675SRob Herring clock-names = "apb_pclk"; 272*724ba675SRob Herring interrupt-controller; 273*724ba675SRob Herring #interrupt-cells = <2>; 274*724ba675SRob Herring status = "disabled"; 275*724ba675SRob Herring }; 276*724ba675SRob Herring 277*724ba675SRob Herring gpio11: gpio@b2b000 { 278*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 279*724ba675SRob Herring reg = <0xb2b000 0x1000>; 280*724ba675SRob Herring interrupts = <0 119 0x4>; 281*724ba675SRob Herring gpio-controller; 282*724ba675SRob Herring #gpio-cells = <2>; 283*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_100M>; 284*724ba675SRob Herring clock-names = "apb_pclk"; 285*724ba675SRob Herring interrupt-controller; 286*724ba675SRob Herring #interrupt-cells = <2>; 287*724ba675SRob Herring status = "disabled"; 288*724ba675SRob Herring }; 289*724ba675SRob Herring 290*724ba675SRob Herring gpio12: gpio@b2c000 { 291*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 292*724ba675SRob Herring reg = <0xb2c000 0x1000>; 293*724ba675SRob Herring interrupts = <0 120 0x4>; 294*724ba675SRob Herring gpio-controller; 295*724ba675SRob Herring #gpio-cells = <2>; 296*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_100M>; 297*724ba675SRob Herring clock-names = "apb_pclk"; 298*724ba675SRob Herring interrupt-controller; 299*724ba675SRob Herring #interrupt-cells = <2>; 300*724ba675SRob Herring status = "disabled"; 301*724ba675SRob Herring }; 302*724ba675SRob Herring 303*724ba675SRob Herring gpio13: gpio@b2d000 { 304*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 305*724ba675SRob Herring reg = <0xb2d000 0x1000>; 306*724ba675SRob Herring interrupts = <0 121 0x4>; 307*724ba675SRob Herring gpio-controller; 308*724ba675SRob Herring #gpio-cells = <2>; 309*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_100M>; 310*724ba675SRob Herring clock-names = "apb_pclk"; 311*724ba675SRob Herring interrupt-controller; 312*724ba675SRob Herring #interrupt-cells = <2>; 313*724ba675SRob Herring status = "disabled"; 314*724ba675SRob Herring }; 315*724ba675SRob Herring 316*724ba675SRob Herring gpio14: gpio@b2e000 { 317*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 318*724ba675SRob Herring reg = <0xb2e000 0x1000>; 319*724ba675SRob Herring interrupts = <0 122 0x4>; 320*724ba675SRob Herring gpio-controller; 321*724ba675SRob Herring #gpio-cells = <2>; 322*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_100M>; 323*724ba675SRob Herring clock-names = "apb_pclk"; 324*724ba675SRob Herring interrupt-controller; 325*724ba675SRob Herring #interrupt-cells = <2>; 326*724ba675SRob Herring status = "disabled"; 327*724ba675SRob Herring }; 328*724ba675SRob Herring 329*724ba675SRob Herring gpio15: gpio@b2f000 { 330*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 331*724ba675SRob Herring reg = <0xb2f000 0x1000>; 332*724ba675SRob Herring interrupts = <0 123 0x4>; 333*724ba675SRob Herring gpio-controller; 334*724ba675SRob Herring #gpio-cells = <2>; 335*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_100M>; 336*724ba675SRob Herring clock-names = "apb_pclk"; 337*724ba675SRob Herring interrupt-controller; 338*724ba675SRob Herring #interrupt-cells = <2>; 339*724ba675SRob Herring status = "disabled"; 340*724ba675SRob Herring }; 341*724ba675SRob Herring 342*724ba675SRob Herring gpio16: gpio@b30000 { 343*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 344*724ba675SRob Herring reg = <0xb30000 0x1000>; 345*724ba675SRob Herring interrupts = <0 124 0x4>; 346*724ba675SRob Herring gpio-controller; 347*724ba675SRob Herring #gpio-cells = <2>; 348*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_100M>; 349*724ba675SRob Herring clock-names = "apb_pclk"; 350*724ba675SRob Herring interrupt-controller; 351*724ba675SRob Herring #interrupt-cells = <2>; 352*724ba675SRob Herring status = "disabled"; 353*724ba675SRob Herring }; 354*724ba675SRob Herring 355*724ba675SRob Herring gpio17: gpio@b31000 { 356*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 357*724ba675SRob Herring reg = <0xb31000 0x1000>; 358*724ba675SRob Herring interrupts = <0 125 0x4>; 359*724ba675SRob Herring gpio-controller; 360*724ba675SRob Herring #gpio-cells = <2>; 361*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_100M>; 362*724ba675SRob Herring clock-names = "apb_pclk"; 363*724ba675SRob Herring interrupt-controller; 364*724ba675SRob Herring #interrupt-cells = <2>; 365*724ba675SRob Herring status = "disabled"; 366*724ba675SRob Herring }; 367*724ba675SRob Herring 368*724ba675SRob Herring wdt0: watchdog@a2c000 { 369*724ba675SRob Herring compatible = "arm,sp805", "arm,primecell"; 370*724ba675SRob Herring arm,primecell-periphid = <0x00141805>; 371*724ba675SRob Herring reg = <0xa2c000 0x1000>; 372*724ba675SRob Herring interrupts = <0 29 4>; 373*724ba675SRob Herring clocks = <&clock HIX5HD2_WDG0_RST>, 374*724ba675SRob Herring <&clock HIX5HD2_WDG0_RST>; 375*724ba675SRob Herring clock-names = "wdog_clk", "apb_pclk"; 376*724ba675SRob Herring }; 377*724ba675SRob Herring }; 378*724ba675SRob Herring 379*724ba675SRob Herring local_timer@a00600 { 380*724ba675SRob Herring compatible = "arm,cortex-a9-twd-timer"; 381*724ba675SRob Herring reg = <0x00a00600 0x20>; 382*724ba675SRob Herring interrupts = <1 13 0xf01>; 383*724ba675SRob Herring }; 384*724ba675SRob Herring 385*724ba675SRob Herring l2: cache-controller { 386*724ba675SRob Herring compatible = "arm,pl310-cache"; 387*724ba675SRob Herring reg = <0x00a10000 0x100000>; 388*724ba675SRob Herring interrupts = <0 15 4>; 389*724ba675SRob Herring cache-unified; 390*724ba675SRob Herring cache-level = <2>; 391*724ba675SRob Herring }; 392*724ba675SRob Herring 393*724ba675SRob Herring sysctrl: system-controller@0 { 394*724ba675SRob Herring compatible = "hisilicon,sysctrl", "syscon"; 395*724ba675SRob Herring reg = <0x00000000 0x1000>; 396*724ba675SRob Herring }; 397*724ba675SRob Herring 398*724ba675SRob Herring reboot { 399*724ba675SRob Herring compatible = "syscon-reboot"; 400*724ba675SRob Herring regmap = <&sysctrl>; 401*724ba675SRob Herring offset = <0x4>; 402*724ba675SRob Herring mask = <0xdeadbeef>; 403*724ba675SRob Herring }; 404*724ba675SRob Herring 405*724ba675SRob Herring cpuctrl@a22000 { 406*724ba675SRob Herring compatible = "hisilicon,cpuctrl"; 407*724ba675SRob Herring #address-cells = <1>; 408*724ba675SRob Herring #size-cells = <1>; 409*724ba675SRob Herring reg = <0x00a22000 0x2000>; 410*724ba675SRob Herring ranges = <0 0x00a22000 0x2000>; 411*724ba675SRob Herring 412*724ba675SRob Herring clock: clock@0 { 413*724ba675SRob Herring compatible = "hisilicon,hix5hd2-clock"; 414*724ba675SRob Herring reg = <0 0x2000>; 415*724ba675SRob Herring #clock-cells = <1>; 416*724ba675SRob Herring }; 417*724ba675SRob Herring }; 418*724ba675SRob Herring 419*724ba675SRob Herring /* unremovable emmc as mmcblk0 */ 420*724ba675SRob Herring mmc: mmc@1830000 { 421*724ba675SRob Herring compatible = "snps,dw-mshc"; 422*724ba675SRob Herring reg = <0x1830000 0x1000>; 423*724ba675SRob Herring interrupts = <0 35 4>; 424*724ba675SRob Herring clocks = <&clock HIX5HD2_MMC_CIU_RST>, 425*724ba675SRob Herring <&clock HIX5HD2_MMC_BIU_CLK>; 426*724ba675SRob Herring clock-names = "biu", "ciu"; 427*724ba675SRob Herring }; 428*724ba675SRob Herring 429*724ba675SRob Herring sd: mmc@1820000 { 430*724ba675SRob Herring compatible = "snps,dw-mshc"; 431*724ba675SRob Herring reg = <0x1820000 0x1000>; 432*724ba675SRob Herring interrupts = <0 34 4>; 433*724ba675SRob Herring clocks = <&clock HIX5HD2_SD_CIU_RST>, 434*724ba675SRob Herring <&clock HIX5HD2_SD_BIU_CLK>; 435*724ba675SRob Herring clock-names = "biu", "ciu"; 436*724ba675SRob Herring }; 437*724ba675SRob Herring 438*724ba675SRob Herring gmac0: ethernet@1840000 { 439*724ba675SRob Herring compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1"; 440*724ba675SRob Herring reg = <0x1840000 0x1000>,<0x184300c 0x4>; 441*724ba675SRob Herring interrupts = <0 71 4>; 442*724ba675SRob Herring clocks = <&clock HIX5HD2_MAC0_CLK>; 443*724ba675SRob Herring clock-names = "mac_core"; 444*724ba675SRob Herring status = "disabled"; 445*724ba675SRob Herring }; 446*724ba675SRob Herring 447*724ba675SRob Herring gmac1: ethernet@1841000 { 448*724ba675SRob Herring compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1"; 449*724ba675SRob Herring reg = <0x1841000 0x1000>,<0x1843010 0x4>; 450*724ba675SRob Herring interrupts = <0 72 4>; 451*724ba675SRob Herring clocks = <&clock HIX5HD2_MAC1_CLK>; 452*724ba675SRob Herring clock-names = "mac_core"; 453*724ba675SRob Herring status = "disabled"; 454*724ba675SRob Herring }; 455*724ba675SRob Herring 456*724ba675SRob Herring usb0: usb@1890000 { 457*724ba675SRob Herring compatible = "generic-ehci"; 458*724ba675SRob Herring reg = <0x1890000 0x1000>; 459*724ba675SRob Herring interrupts = <0 66 4>; 460*724ba675SRob Herring clocks = <&clock HIX5HD2_USB_CLK>; 461*724ba675SRob Herring }; 462*724ba675SRob Herring 463*724ba675SRob Herring usb1: usb@1880000 { 464*724ba675SRob Herring compatible = "generic-ohci"; 465*724ba675SRob Herring reg = <0x1880000 0x1000>; 466*724ba675SRob Herring interrupts = <0 67 4>; 467*724ba675SRob Herring clocks = <&clock HIX5HD2_USB_CLK>; 468*724ba675SRob Herring }; 469*724ba675SRob Herring 470*724ba675SRob Herring peripheral_ctrl: syscon@a20000 { 471*724ba675SRob Herring compatible = "hisilicon,peri-subctrl", "syscon"; 472*724ba675SRob Herring reg = <0xa20000 0x1000>; 473*724ba675SRob Herring }; 474*724ba675SRob Herring 475*724ba675SRob Herring sata_phy: phy@1900000 { 476*724ba675SRob Herring compatible = "hisilicon,hix5hd2-sata-phy"; 477*724ba675SRob Herring reg = <0x1900000 0x10000>; 478*724ba675SRob Herring #phy-cells = <0>; 479*724ba675SRob Herring hisilicon,peripheral-syscon = <&peripheral_ctrl>; 480*724ba675SRob Herring hisilicon,power-reg = <0x8 10>; 481*724ba675SRob Herring }; 482*724ba675SRob Herring 483*724ba675SRob Herring ahci: sata@1900000 { 484*724ba675SRob Herring compatible = "hisilicon,hisi-ahci"; 485*724ba675SRob Herring reg = <0x1900000 0x10000>; 486*724ba675SRob Herring interrupts = <0 70 4>; 487*724ba675SRob Herring clocks = <&clock HIX5HD2_SATA_CLK>; 488*724ba675SRob Herring }; 489*724ba675SRob Herring 490*724ba675SRob Herring ir: ir@1000 { 491*724ba675SRob Herring compatible = "hisilicon,hix5hd2-ir"; 492*724ba675SRob Herring reg = <0x001000 0x1000>; 493*724ba675SRob Herring interrupts = <0 47 4>; 494*724ba675SRob Herring clocks = <&clock HIX5HD2_FIXED_24M>; 495*724ba675SRob Herring hisilicon,power-syscon = <&sysctrl>; 496*724ba675SRob Herring }; 497*724ba675SRob Herring 498*724ba675SRob Herring i2c0: i2c@b10000 { 499*724ba675SRob Herring compatible = "hisilicon,hix5hd2-i2c"; 500*724ba675SRob Herring reg = <0xb10000 0x1000>; 501*724ba675SRob Herring interrupts = <0 38 4>; 502*724ba675SRob Herring clocks = <&clock HIX5HD2_I2C0_RST>; 503*724ba675SRob Herring #address-cells = <1>; 504*724ba675SRob Herring #size-cells = <0>; 505*724ba675SRob Herring status = "disabled"; 506*724ba675SRob Herring }; 507*724ba675SRob Herring 508*724ba675SRob Herring i2c1: i2c@b11000 { 509*724ba675SRob Herring compatible = "hisilicon,hix5hd2-i2c"; 510*724ba675SRob Herring reg = <0xb11000 0x1000>; 511*724ba675SRob Herring interrupts = <0 39 4>; 512*724ba675SRob Herring clocks = <&clock HIX5HD2_I2C1_RST>; 513*724ba675SRob Herring #address-cells = <1>; 514*724ba675SRob Herring #size-cells = <0>; 515*724ba675SRob Herring status = "disabled"; 516*724ba675SRob Herring }; 517*724ba675SRob Herring 518*724ba675SRob Herring i2c2: i2c@b12000 { 519*724ba675SRob Herring compatible = "hisilicon,hix5hd2-i2c"; 520*724ba675SRob Herring reg = <0xb12000 0x1000>; 521*724ba675SRob Herring interrupts = <0 40 4>; 522*724ba675SRob Herring clocks = <&clock HIX5HD2_I2C2_RST>; 523*724ba675SRob Herring #address-cells = <1>; 524*724ba675SRob Herring #size-cells = <0>; 525*724ba675SRob Herring status = "disabled"; 526*724ba675SRob Herring }; 527*724ba675SRob Herring 528*724ba675SRob Herring i2c3: i2c@b13000 { 529*724ba675SRob Herring compatible = "hisilicon,hix5hd2-i2c"; 530*724ba675SRob Herring reg = <0xb13000 0x1000>; 531*724ba675SRob Herring interrupts = <0 41 4>; 532*724ba675SRob Herring clocks = <&clock HIX5HD2_I2C3_RST>; 533*724ba675SRob Herring #address-cells = <1>; 534*724ba675SRob Herring #size-cells = <0>; 535*724ba675SRob Herring status = "disabled"; 536*724ba675SRob Herring }; 537*724ba675SRob Herring 538*724ba675SRob Herring i2c4: i2c@b16000 { 539*724ba675SRob Herring compatible = "hisilicon,hix5hd2-i2c"; 540*724ba675SRob Herring reg = <0xb16000 0x1000>; 541*724ba675SRob Herring interrupts = <0 43 4>; 542*724ba675SRob Herring clocks = <&clock HIX5HD2_I2C4_RST>; 543*724ba675SRob Herring #address-cells = <1>; 544*724ba675SRob Herring #size-cells = <0>; 545*724ba675SRob Herring status = "disabled"; 546*724ba675SRob Herring }; 547*724ba675SRob Herring 548*724ba675SRob Herring i2c5: i2c@b17000 { 549*724ba675SRob Herring compatible = "hisilicon,hix5hd2-i2c"; 550*724ba675SRob Herring reg = <0xb17000 0x1000>; 551*724ba675SRob Herring interrupts = <0 44 4>; 552*724ba675SRob Herring clocks = <&clock HIX5HD2_I2C5_RST>; 553*724ba675SRob Herring #address-cells = <1>; 554*724ba675SRob Herring #size-cells = <0>; 555*724ba675SRob Herring status = "disabled"; 556*724ba675SRob Herring }; 557*724ba675SRob Herring }; 558*724ba675SRob Herring}; 559