1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree file for Cortina systems Gemini SoC 4*724ba675SRob Herring */ 5*724ba675SRob Herring 6*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 7*724ba675SRob Herring#include <dt-bindings/clock/cortina,gemini-clock.h> 8*724ba675SRob Herring#include <dt-bindings/reset/cortina,gemini-reset.h> 9*724ba675SRob Herring#include <dt-bindings/gpio/gpio.h> 10*724ba675SRob Herring 11*724ba675SRob Herring/ { 12*724ba675SRob Herring soc { 13*724ba675SRob Herring #address-cells = <1>; 14*724ba675SRob Herring #size-cells = <1>; 15*724ba675SRob Herring ranges; 16*724ba675SRob Herring compatible = "simple-bus"; 17*724ba675SRob Herring interrupt-parent = <&intcon>; 18*724ba675SRob Herring 19*724ba675SRob Herring flash: flash@30000000 { 20*724ba675SRob Herring compatible = "cortina,gemini-flash", "cfi-flash"; 21*724ba675SRob Herring syscon = <&syscon>; 22*724ba675SRob Herring pinctrl-names = "default"; 23*724ba675SRob Herring pinctrl-0 = <&pflash_default_pins>; 24*724ba675SRob Herring bank-width = <2>; 25*724ba675SRob Herring status = "disabled"; 26*724ba675SRob Herring }; 27*724ba675SRob Herring 28*724ba675SRob Herring syscon: syscon@40000000 { 29*724ba675SRob Herring compatible = "cortina,gemini-syscon", 30*724ba675SRob Herring "syscon", "simple-mfd"; 31*724ba675SRob Herring reg = <0x40000000 0x1000>; 32*724ba675SRob Herring #clock-cells = <1>; 33*724ba675SRob Herring #reset-cells = <1>; 34*724ba675SRob Herring 35*724ba675SRob Herring syscon-reboot { 36*724ba675SRob Herring compatible = "syscon-reboot"; 37*724ba675SRob Herring regmap = <&syscon>; 38*724ba675SRob Herring /* GLOBAL_RESET register */ 39*724ba675SRob Herring offset = <0x0c>; 40*724ba675SRob Herring /* RESET_GLOBAL | RESET_CPU1 */ 41*724ba675SRob Herring mask = <0xC0000000>; 42*724ba675SRob Herring }; 43*724ba675SRob Herring 44*724ba675SRob Herring pinctrl { 45*724ba675SRob Herring compatible = "cortina,gemini-pinctrl"; 46*724ba675SRob Herring regmap = <&syscon>; 47*724ba675SRob Herring /* Hog the DRAM pins */ 48*724ba675SRob Herring pinctrl-names = "default"; 49*724ba675SRob Herring pinctrl-0 = <&dram_default_pins>, <&system_default_pins>, 50*724ba675SRob Herring <&vcontrol_default_pins>; 51*724ba675SRob Herring 52*724ba675SRob Herring dram_default_pins: pinctrl-dram { 53*724ba675SRob Herring mux { 54*724ba675SRob Herring function = "dram"; 55*724ba675SRob Herring groups = "dramgrp"; 56*724ba675SRob Herring }; 57*724ba675SRob Herring }; 58*724ba675SRob Herring rtc_default_pins: pinctrl-rtc { 59*724ba675SRob Herring mux { 60*724ba675SRob Herring function = "rtc"; 61*724ba675SRob Herring groups = "rtcgrp"; 62*724ba675SRob Herring }; 63*724ba675SRob Herring }; 64*724ba675SRob Herring power_default_pins: pinctrl-power { 65*724ba675SRob Herring mux { 66*724ba675SRob Herring function = "power"; 67*724ba675SRob Herring groups = "powergrp"; 68*724ba675SRob Herring }; 69*724ba675SRob Herring }; 70*724ba675SRob Herring cir_default_pins: pinctrl-cir { 71*724ba675SRob Herring mux { 72*724ba675SRob Herring function = "cir"; 73*724ba675SRob Herring groups = "cirgrp"; 74*724ba675SRob Herring }; 75*724ba675SRob Herring }; 76*724ba675SRob Herring system_default_pins: pinctrl-system { 77*724ba675SRob Herring mux { 78*724ba675SRob Herring function = "system"; 79*724ba675SRob Herring groups = "systemgrp"; 80*724ba675SRob Herring }; 81*724ba675SRob Herring }; 82*724ba675SRob Herring vcontrol_default_pins: pinctrl-vcontrol { 83*724ba675SRob Herring mux { 84*724ba675SRob Herring function = "vcontrol"; 85*724ba675SRob Herring groups = "vcontrolgrp"; 86*724ba675SRob Herring }; 87*724ba675SRob Herring }; 88*724ba675SRob Herring ice_default_pins: pinctrl-ice { 89*724ba675SRob Herring mux { 90*724ba675SRob Herring function = "ice"; 91*724ba675SRob Herring groups = "icegrp"; 92*724ba675SRob Herring }; 93*724ba675SRob Herring }; 94*724ba675SRob Herring uart_default_pins: pinctrl-uart { 95*724ba675SRob Herring mux { 96*724ba675SRob Herring function = "uart"; 97*724ba675SRob Herring groups = "uartrxtxgrp"; 98*724ba675SRob Herring }; 99*724ba675SRob Herring }; 100*724ba675SRob Herring pflash_default_pins: pinctrl-pflash { 101*724ba675SRob Herring mux { 102*724ba675SRob Herring function = "pflash"; 103*724ba675SRob Herring groups = "pflashgrp"; 104*724ba675SRob Herring }; 105*724ba675SRob Herring }; 106*724ba675SRob Herring usb_default_pins: pinctrl-usb { 107*724ba675SRob Herring mux { 108*724ba675SRob Herring function = "usb"; 109*724ba675SRob Herring groups = "usbgrp"; 110*724ba675SRob Herring }; 111*724ba675SRob Herring }; 112*724ba675SRob Herring gmii_default_pins: pinctrl-gmii { 113*724ba675SRob Herring /* 114*724ba675SRob Herring * Only activate GMAC0 by default since 115*724ba675SRob Herring * GMAC1 will overlap with 8 GPIO lines 116*724ba675SRob Herring * gpio2a, gpio2b. Overlay groups with 117*724ba675SRob Herring * "gmii_gmac0_grp", "gmii_gmac1_grp" for 118*724ba675SRob Herring * both ethernet interfaces. 119*724ba675SRob Herring */ 120*724ba675SRob Herring mux { 121*724ba675SRob Herring function = "gmii"; 122*724ba675SRob Herring groups = "gmii_gmac0_grp"; 123*724ba675SRob Herring }; 124*724ba675SRob Herring }; 125*724ba675SRob Herring pci_default_pins: pinctrl-pci { 126*724ba675SRob Herring mux { 127*724ba675SRob Herring function = "pci"; 128*724ba675SRob Herring groups = "pcigrp"; 129*724ba675SRob Herring }; 130*724ba675SRob Herring }; 131*724ba675SRob Herring sata_default_pins: pinctrl-sata { 132*724ba675SRob Herring mux { 133*724ba675SRob Herring function = "sata"; 134*724ba675SRob Herring groups = "satagrp"; 135*724ba675SRob Herring }; 136*724ba675SRob Herring }; 137*724ba675SRob Herring /* Activate both groups of pins for this state */ 138*724ba675SRob Herring sata_and_ide_pins: pinctrl-sata-ide { 139*724ba675SRob Herring mux0 { 140*724ba675SRob Herring function = "sata"; 141*724ba675SRob Herring groups = "satagrp"; 142*724ba675SRob Herring }; 143*724ba675SRob Herring mux1 { 144*724ba675SRob Herring function = "ide"; 145*724ba675SRob Herring groups = "idegrp"; 146*724ba675SRob Herring }; 147*724ba675SRob Herring }; 148*724ba675SRob Herring tvc_default_pins: pinctrl-tvc { 149*724ba675SRob Herring mux { 150*724ba675SRob Herring function = "tvc"; 151*724ba675SRob Herring groups = "tvcgrp"; 152*724ba675SRob Herring }; 153*724ba675SRob Herring }; 154*724ba675SRob Herring }; 155*724ba675SRob Herring }; 156*724ba675SRob Herring 157*724ba675SRob Herring watchdog@41000000 { 158*724ba675SRob Herring compatible = "cortina,gemini-watchdog", "faraday,ftwdt010"; 159*724ba675SRob Herring reg = <0x41000000 0x1000>; 160*724ba675SRob Herring interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; 161*724ba675SRob Herring resets = <&syscon GEMINI_RESET_WDOG>; 162*724ba675SRob Herring clocks = <&syscon GEMINI_CLK_APB>; 163*724ba675SRob Herring clock-names = "PCLK"; 164*724ba675SRob Herring }; 165*724ba675SRob Herring 166*724ba675SRob Herring uart0: serial@42000000 { 167*724ba675SRob Herring compatible = "ns16550a"; 168*724ba675SRob Herring reg = <0x42000000 0x100>; 169*724ba675SRob Herring resets = <&syscon GEMINI_RESET_UART>; 170*724ba675SRob Herring clocks = <&syscon GEMINI_CLK_UART>; 171*724ba675SRob Herring interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 172*724ba675SRob Herring pinctrl-names = "default"; 173*724ba675SRob Herring pinctrl-0 = <&uart_default_pins>; 174*724ba675SRob Herring reg-shift = <2>; 175*724ba675SRob Herring }; 176*724ba675SRob Herring 177*724ba675SRob Herring timer@43000000 { 178*724ba675SRob Herring compatible = "faraday,fttmr010"; 179*724ba675SRob Herring reg = <0x43000000 0x1000>; 180*724ba675SRob Herring interrupt-parent = <&intcon>; 181*724ba675SRob Herring interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ 182*724ba675SRob Herring <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ 183*724ba675SRob Herring <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ 184*724ba675SRob Herring resets = <&syscon GEMINI_RESET_TIMER>; 185*724ba675SRob Herring /* APB clock or RTC clock */ 186*724ba675SRob Herring clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>; 187*724ba675SRob Herring clock-names = "PCLK", "EXTCLK"; 188*724ba675SRob Herring syscon = <&syscon>; 189*724ba675SRob Herring }; 190*724ba675SRob Herring 191*724ba675SRob Herring rtc@45000000 { 192*724ba675SRob Herring compatible = "cortina,gemini-rtc", "faraday,ftrtc010"; 193*724ba675SRob Herring reg = <0x45000000 0x100>; 194*724ba675SRob Herring interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; 195*724ba675SRob Herring resets = <&syscon GEMINI_RESET_RTC>; 196*724ba675SRob Herring clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>; 197*724ba675SRob Herring clock-names = "PCLK", "EXTCLK"; 198*724ba675SRob Herring pinctrl-names = "default"; 199*724ba675SRob Herring pinctrl-0 = <&rtc_default_pins>; 200*724ba675SRob Herring }; 201*724ba675SRob Herring 202*724ba675SRob Herring sata: sata@46000000 { 203*724ba675SRob Herring compatible = "cortina,gemini-sata-bridge"; 204*724ba675SRob Herring reg = <0x46000000 0x100>; 205*724ba675SRob Herring resets = <&syscon GEMINI_RESET_SATA0>, 206*724ba675SRob Herring <&syscon GEMINI_RESET_SATA1>; 207*724ba675SRob Herring reset-names = "sata0", "sata1"; 208*724ba675SRob Herring clocks = <&syscon GEMINI_CLK_GATE_SATA0>, 209*724ba675SRob Herring <&syscon GEMINI_CLK_GATE_SATA1>; 210*724ba675SRob Herring clock-names = "SATA0_PCLK", "SATA1_PCLK"; 211*724ba675SRob Herring /* 212*724ba675SRob Herring * This defines the special "ide" state that needs 213*724ba675SRob Herring * to be explicitly enabled to enable the IDE pins, 214*724ba675SRob Herring * as these pins are normally used for other things. 215*724ba675SRob Herring */ 216*724ba675SRob Herring pinctrl-names = "default", "ide"; 217*724ba675SRob Herring pinctrl-0 = <&sata_default_pins>; 218*724ba675SRob Herring pinctrl-1 = <&sata_and_ide_pins>; 219*724ba675SRob Herring syscon = <&syscon>; 220*724ba675SRob Herring status = "disabled"; 221*724ba675SRob Herring }; 222*724ba675SRob Herring 223*724ba675SRob Herring intcon: interrupt-controller@48000000 { 224*724ba675SRob Herring compatible = "faraday,ftintc010"; 225*724ba675SRob Herring reg = <0x48000000 0x1000>; 226*724ba675SRob Herring resets = <&syscon GEMINI_RESET_INTCON0>; 227*724ba675SRob Herring interrupt-controller; 228*724ba675SRob Herring #interrupt-cells = <2>; 229*724ba675SRob Herring }; 230*724ba675SRob Herring 231*724ba675SRob Herring power-controller@4b000000 { 232*724ba675SRob Herring compatible = "cortina,gemini-power-controller"; 233*724ba675SRob Herring reg = <0x4b000000 0x100>; 234*724ba675SRob Herring interrupts = <26 IRQ_TYPE_EDGE_RISING>; 235*724ba675SRob Herring pinctrl-names = "default"; 236*724ba675SRob Herring pinctrl-0 = <&power_default_pins>; 237*724ba675SRob Herring }; 238*724ba675SRob Herring 239*724ba675SRob Herring gpio0: gpio@4d000000 { 240*724ba675SRob Herring compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; 241*724ba675SRob Herring reg = <0x4d000000 0x100>; 242*724ba675SRob Herring interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 243*724ba675SRob Herring resets = <&syscon GEMINI_RESET_GPIO0>; 244*724ba675SRob Herring clocks = <&syscon GEMINI_CLK_APB>; 245*724ba675SRob Herring gpio-controller; 246*724ba675SRob Herring #gpio-cells = <2>; 247*724ba675SRob Herring interrupt-controller; 248*724ba675SRob Herring #interrupt-cells = <2>; 249*724ba675SRob Herring }; 250*724ba675SRob Herring 251*724ba675SRob Herring gpio1: gpio@4e000000 { 252*724ba675SRob Herring compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; 253*724ba675SRob Herring reg = <0x4e000000 0x100>; 254*724ba675SRob Herring interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 255*724ba675SRob Herring resets = <&syscon GEMINI_RESET_GPIO1>; 256*724ba675SRob Herring clocks = <&syscon GEMINI_CLK_APB>; 257*724ba675SRob Herring gpio-controller; 258*724ba675SRob Herring #gpio-cells = <2>; 259*724ba675SRob Herring interrupt-controller; 260*724ba675SRob Herring #interrupt-cells = <2>; 261*724ba675SRob Herring }; 262*724ba675SRob Herring 263*724ba675SRob Herring gpio2: gpio@4f000000 { 264*724ba675SRob Herring compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; 265*724ba675SRob Herring reg = <0x4f000000 0x100>; 266*724ba675SRob Herring interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; 267*724ba675SRob Herring resets = <&syscon GEMINI_RESET_GPIO2>; 268*724ba675SRob Herring clocks = <&syscon GEMINI_CLK_APB>; 269*724ba675SRob Herring gpio-controller; 270*724ba675SRob Herring #gpio-cells = <2>; 271*724ba675SRob Herring interrupt-controller; 272*724ba675SRob Herring #interrupt-cells = <2>; 273*724ba675SRob Herring }; 274*724ba675SRob Herring 275*724ba675SRob Herring pci@50000000 { 276*724ba675SRob Herring compatible = "cortina,gemini-pci", "faraday,ftpci100"; 277*724ba675SRob Herring /* 278*724ba675SRob Herring * The first 256 bytes in the IO range is actually used 279*724ba675SRob Herring * to configure the host bridge. 280*724ba675SRob Herring */ 281*724ba675SRob Herring reg = <0x50000000 0x100>; 282*724ba675SRob Herring resets = <&syscon GEMINI_RESET_PCI>; 283*724ba675SRob Herring clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>; 284*724ba675SRob Herring clock-names = "PCLK", "PCICLK"; 285*724ba675SRob Herring pinctrl-names = "default"; 286*724ba675SRob Herring pinctrl-0 = <&pci_default_pins>; 287*724ba675SRob Herring device_type = "pci"; 288*724ba675SRob Herring #address-cells = <3>; 289*724ba675SRob Herring #size-cells = <2>; 290*724ba675SRob Herring status = "disabled"; 291*724ba675SRob Herring 292*724ba675SRob Herring #interrupt-cells = <1>; 293*724ba675SRob Herring interrupt-map-mask = <0xf800 0 0 7>; 294*724ba675SRob Herring interrupt-map = 295*724ba675SRob Herring <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ 296*724ba675SRob Herring <0x4800 0 0 2 &pci_intc 1>, 297*724ba675SRob Herring <0x4800 0 0 3 &pci_intc 2>, 298*724ba675SRob Herring <0x4800 0 0 4 &pci_intc 3>, 299*724ba675SRob Herring <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ 300*724ba675SRob Herring <0x5000 0 0 2 &pci_intc 2>, 301*724ba675SRob Herring <0x5000 0 0 3 &pci_intc 3>, 302*724ba675SRob Herring <0x5000 0 0 4 &pci_intc 0>, 303*724ba675SRob Herring <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ 304*724ba675SRob Herring <0x5800 0 0 2 &pci_intc 3>, 305*724ba675SRob Herring <0x5800 0 0 3 &pci_intc 0>, 306*724ba675SRob Herring <0x5800 0 0 4 &pci_intc 1>, 307*724ba675SRob Herring <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ 308*724ba675SRob Herring <0x6000 0 0 2 &pci_intc 0>, 309*724ba675SRob Herring <0x6000 0 0 3 &pci_intc 1>, 310*724ba675SRob Herring <0x6000 0 0 4 &pci_intc 2>; 311*724ba675SRob Herring 312*724ba675SRob Herring bus-range = <0x00 0xff>; 313*724ba675SRob Herring /* PCI ranges mappings */ 314*724ba675SRob Herring ranges = 315*724ba675SRob Herring /* 1MiB I/O space 0x50000000-0x500fffff */ 316*724ba675SRob Herring <0x01000000 0 0 0x50000000 0 0x00100000>, 317*724ba675SRob Herring /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */ 318*724ba675SRob Herring <0x02000000 0 0x58000000 0x58000000 0 0x08000000>; 319*724ba675SRob Herring 320*724ba675SRob Herring /* DMA ranges */ 321*724ba675SRob Herring dma-ranges = 322*724ba675SRob Herring /* 128MiB at 0x00000000-0x07ffffff */ 323*724ba675SRob Herring <0x02000000 0 0x00000000 0x00000000 0 0x08000000>, 324*724ba675SRob Herring /* 64MiB at 0x00000000-0x03ffffff */ 325*724ba675SRob Herring <0x02000000 0 0x00000000 0x00000000 0 0x04000000>, 326*724ba675SRob Herring /* 64MiB at 0x00000000-0x03ffffff */ 327*724ba675SRob Herring <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; 328*724ba675SRob Herring 329*724ba675SRob Herring /* 330*724ba675SRob Herring * This PCI host bridge variant has a cascaded interrupt 331*724ba675SRob Herring * controller embedded in the host bridge. 332*724ba675SRob Herring */ 333*724ba675SRob Herring pci_intc: interrupt-controller { 334*724ba675SRob Herring interrupt-parent = <&intcon>; 335*724ba675SRob Herring interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 336*724ba675SRob Herring interrupt-controller; 337*724ba675SRob Herring #address-cells = <0>; 338*724ba675SRob Herring #interrupt-cells = <1>; 339*724ba675SRob Herring }; 340*724ba675SRob Herring }; 341*724ba675SRob Herring 342*724ba675SRob Herring ethernet: ethernet@60000000 { 343*724ba675SRob Herring compatible = "cortina,gemini-ethernet"; 344*724ba675SRob Herring reg = <0x60000000 0x4000>, /* Global registers, queue */ 345*724ba675SRob Herring <0x60004000 0x2000>, /* V-bit */ 346*724ba675SRob Herring <0x60006000 0x2000>; /* A-bit */ 347*724ba675SRob Herring pinctrl-names = "default"; 348*724ba675SRob Herring pinctrl-0 = <&gmii_default_pins>; 349*724ba675SRob Herring status = "disabled"; 350*724ba675SRob Herring #address-cells = <1>; 351*724ba675SRob Herring #size-cells = <1>; 352*724ba675SRob Herring ranges; 353*724ba675SRob Herring 354*724ba675SRob Herring gmac0: ethernet-port@0 { 355*724ba675SRob Herring compatible = "cortina,gemini-ethernet-port"; 356*724ba675SRob Herring reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */ 357*724ba675SRob Herring <0x6000a000 0x2000>; /* Port 0 GMAC */ 358*724ba675SRob Herring interrupt-parent = <&intcon>; 359*724ba675SRob Herring interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 360*724ba675SRob Herring resets = <&syscon GEMINI_RESET_GMAC0>; 361*724ba675SRob Herring clocks = <&syscon GEMINI_CLK_GATE_GMAC0>; 362*724ba675SRob Herring clock-names = "PCLK"; 363*724ba675SRob Herring }; 364*724ba675SRob Herring 365*724ba675SRob Herring gmac1: ethernet-port@1 { 366*724ba675SRob Herring compatible = "cortina,gemini-ethernet-port"; 367*724ba675SRob Herring reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */ 368*724ba675SRob Herring <0x6000e000 0x2000>; /* Port 1 GMAC */ 369*724ba675SRob Herring interrupt-parent = <&intcon>; 370*724ba675SRob Herring interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 371*724ba675SRob Herring resets = <&syscon GEMINI_RESET_GMAC1>; 372*724ba675SRob Herring clocks = <&syscon GEMINI_CLK_GATE_GMAC1>; 373*724ba675SRob Herring clock-names = "PCLK"; 374*724ba675SRob Herring }; 375*724ba675SRob Herring }; 376*724ba675SRob Herring 377*724ba675SRob Herring crypto: crypto@62000000 { 378*724ba675SRob Herring compatible = "cortina,sl3516-crypto"; 379*724ba675SRob Herring reg = <0x62000000 0x10000>; 380*724ba675SRob Herring interrupts = <7 IRQ_TYPE_EDGE_RISING>; 381*724ba675SRob Herring resets = <&syscon GEMINI_RESET_SECURITY>; 382*724ba675SRob Herring clocks = <&syscon GEMINI_CLK_GATE_SECURITY>; 383*724ba675SRob Herring }; 384*724ba675SRob Herring 385*724ba675SRob Herring ide0: ide@63000000 { 386*724ba675SRob Herring compatible = "cortina,gemini-pata", "faraday,ftide010"; 387*724ba675SRob Herring reg = <0x63000000 0x1000>; 388*724ba675SRob Herring interrupts = <4 IRQ_TYPE_EDGE_RISING>; 389*724ba675SRob Herring resets = <&syscon GEMINI_RESET_IDE>; 390*724ba675SRob Herring clocks = <&syscon GEMINI_CLK_GATE_IDE>; 391*724ba675SRob Herring clock-names = "PCLK"; 392*724ba675SRob Herring sata = <&sata>; 393*724ba675SRob Herring status = "disabled"; 394*724ba675SRob Herring #address-cells = <1>; 395*724ba675SRob Herring #size-cells = <0>; 396*724ba675SRob Herring }; 397*724ba675SRob Herring 398*724ba675SRob Herring ide1: ide@63400000 { 399*724ba675SRob Herring compatible = "cortina,gemini-pata", "faraday,ftide010"; 400*724ba675SRob Herring reg = <0x63400000 0x1000>; 401*724ba675SRob Herring interrupts = <5 IRQ_TYPE_EDGE_RISING>; 402*724ba675SRob Herring resets = <&syscon GEMINI_RESET_IDE>; 403*724ba675SRob Herring clocks = <&syscon GEMINI_CLK_GATE_IDE>; 404*724ba675SRob Herring clock-names = "PCLK"; 405*724ba675SRob Herring sata = <&sata>; 406*724ba675SRob Herring status = "disabled"; 407*724ba675SRob Herring #address-cells = <1>; 408*724ba675SRob Herring #size-cells = <0>; 409*724ba675SRob Herring }; 410*724ba675SRob Herring 411*724ba675SRob Herring dma-controller@67000000 { 412*724ba675SRob Herring compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell"; 413*724ba675SRob Herring /* Faraday Technology FTDMAC020 variant */ 414*724ba675SRob Herring arm,primecell-periphid = <0x0003b080>; 415*724ba675SRob Herring reg = <0x67000000 0x1000>; 416*724ba675SRob Herring interrupts = <9 IRQ_TYPE_EDGE_RISING>; 417*724ba675SRob Herring resets = <&syscon GEMINI_RESET_DMAC>; 418*724ba675SRob Herring clocks = <&syscon GEMINI_CLK_AHB>; 419*724ba675SRob Herring clock-names = "apb_pclk"; 420*724ba675SRob Herring /* Bus interface AHB1 (AHB0) is totally tilted */ 421*724ba675SRob Herring lli-bus-interface-ahb2; 422*724ba675SRob Herring mem-bus-interface-ahb2; 423*724ba675SRob Herring memcpy-burst-size = <256>; 424*724ba675SRob Herring memcpy-bus-width = <32>; 425*724ba675SRob Herring #dma-cells = <2>; 426*724ba675SRob Herring }; 427*724ba675SRob Herring 428*724ba675SRob Herring display-controller@6a000000 { 429*724ba675SRob Herring compatible = "cortina,gemini-tvc", "faraday,tve200"; 430*724ba675SRob Herring reg = <0x6a000000 0x1000>; 431*724ba675SRob Herring interrupts = <13 IRQ_TYPE_EDGE_RISING>; 432*724ba675SRob Herring resets = <&syscon GEMINI_RESET_TVC>; 433*724ba675SRob Herring clocks = <&syscon GEMINI_CLK_GATE_TVC>, 434*724ba675SRob Herring <&syscon GEMINI_CLK_TVC>; 435*724ba675SRob Herring clock-names = "PCLK", "TVE"; 436*724ba675SRob Herring pinctrl-names = "default"; 437*724ba675SRob Herring pinctrl-0 = <&tvc_default_pins>; 438*724ba675SRob Herring status = "disabled"; 439*724ba675SRob Herring }; 440*724ba675SRob Herring 441*724ba675SRob Herring usb0: usb@68000000 { 442*724ba675SRob Herring compatible = "cortina,gemini-usb", "faraday,fotg200"; 443*724ba675SRob Herring reg = <0x68000000 0x1000>; 444*724ba675SRob Herring interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 445*724ba675SRob Herring resets = <&syscon GEMINI_RESET_USB0>; 446*724ba675SRob Herring clocks = <&syscon GEMINI_CLK_GATE_USB0>; 447*724ba675SRob Herring clock-names = "PCLK"; 448*724ba675SRob Herring /* 449*724ba675SRob Herring * This will claim pins for USB0 and USB1 at the same 450*724ba675SRob Herring * time as they are using some common pins. If you for 451*724ba675SRob Herring * some reason have a system using USB1 at 96000000 but 452*724ba675SRob Herring * NOT using USB0 at 68000000 you wll have to add the 453*724ba675SRob Herring * usb_default_pins to the USB controller at 96000000 454*724ba675SRob Herring * in your .dts for the board. 455*724ba675SRob Herring */ 456*724ba675SRob Herring pinctrl-names = "default"; 457*724ba675SRob Herring pinctrl-0 = <&usb_default_pins>; 458*724ba675SRob Herring /* Default to host mode */ 459*724ba675SRob Herring dr_mode = "host"; 460*724ba675SRob Herring syscon = <&syscon>; 461*724ba675SRob Herring status = "disabled"; 462*724ba675SRob Herring }; 463*724ba675SRob Herring 464*724ba675SRob Herring usb1: usb@69000000 { 465*724ba675SRob Herring compatible = "cortina,gemini-usb", "faraday,fotg200"; 466*724ba675SRob Herring reg = <0x69000000 0x1000>; 467*724ba675SRob Herring interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 468*724ba675SRob Herring resets = <&syscon GEMINI_RESET_USB1>; 469*724ba675SRob Herring clocks = <&syscon GEMINI_CLK_GATE_USB1>; 470*724ba675SRob Herring clock-names = "PCLK"; 471*724ba675SRob Herring syscon = <&syscon>; 472*724ba675SRob Herring status = "disabled"; 473*724ba675SRob Herring }; 474*724ba675SRob Herring }; 475*724ba675SRob Herring}; 476