1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*724ba675SRob Herring/*
3*724ba675SRob Herring * Copyright 2022 Broadcom Ltd.
4*724ba675SRob Herring */
5*724ba675SRob Herring
6*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h>
7*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h>
8*724ba675SRob Herring
9*724ba675SRob Herring/ {
10*724ba675SRob Herring	compatible = "brcm,bcm6846", "brcm,bcmbca";
11*724ba675SRob Herring	#address-cells = <1>;
12*724ba675SRob Herring	#size-cells = <1>;
13*724ba675SRob Herring
14*724ba675SRob Herring	interrupt-parent = <&gic>;
15*724ba675SRob Herring
16*724ba675SRob Herring	cpus {
17*724ba675SRob Herring		#address-cells = <1>;
18*724ba675SRob Herring		#size-cells = <0>;
19*724ba675SRob Herring
20*724ba675SRob Herring		CA7_0: cpu@0 {
21*724ba675SRob Herring			device_type = "cpu";
22*724ba675SRob Herring			compatible = "arm,cortex-a7";
23*724ba675SRob Herring			reg = <0x0>;
24*724ba675SRob Herring			next-level-cache = <&L2_0>;
25*724ba675SRob Herring			enable-method = "psci";
26*724ba675SRob Herring		};
27*724ba675SRob Herring
28*724ba675SRob Herring		CA7_1: cpu@1 {
29*724ba675SRob Herring			device_type = "cpu";
30*724ba675SRob Herring			compatible = "arm,cortex-a7";
31*724ba675SRob Herring			reg = <0x1>;
32*724ba675SRob Herring			next-level-cache = <&L2_0>;
33*724ba675SRob Herring			enable-method = "psci";
34*724ba675SRob Herring		};
35*724ba675SRob Herring
36*724ba675SRob Herring		L2_0: l2-cache0 {
37*724ba675SRob Herring			compatible = "cache";
38*724ba675SRob Herring			cache-level = <2>;
39*724ba675SRob Herring			cache-unified;
40*724ba675SRob Herring		};
41*724ba675SRob Herring	};
42*724ba675SRob Herring
43*724ba675SRob Herring	timer {
44*724ba675SRob Herring		compatible = "arm,armv7-timer";
45*724ba675SRob Herring		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
46*724ba675SRob Herring			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
47*724ba675SRob Herring			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
48*724ba675SRob Herring			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
49*724ba675SRob Herring		arm,cpu-registers-not-fw-configured;
50*724ba675SRob Herring	};
51*724ba675SRob Herring
52*724ba675SRob Herring	pmu: pmu {
53*724ba675SRob Herring		compatible = "arm,cortex-a7-pmu";
54*724ba675SRob Herring		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
55*724ba675SRob Herring			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
56*724ba675SRob Herring		interrupt-affinity = <&CA7_0>, <&CA7_1>;
57*724ba675SRob Herring	};
58*724ba675SRob Herring
59*724ba675SRob Herring	clocks: clocks {
60*724ba675SRob Herring		periph_clk: periph-clk {
61*724ba675SRob Herring			compatible = "fixed-clock";
62*724ba675SRob Herring			#clock-cells = <0>;
63*724ba675SRob Herring			clock-frequency = <200000000>;
64*724ba675SRob Herring		};
65*724ba675SRob Herring
66*724ba675SRob Herring		hsspi_pll: hsspi-pll {
67*724ba675SRob Herring			compatible = "fixed-clock";
68*724ba675SRob Herring			#clock-cells = <0>;
69*724ba675SRob Herring			clock-frequency = <400000000>;
70*724ba675SRob Herring		};
71*724ba675SRob Herring	};
72*724ba675SRob Herring
73*724ba675SRob Herring	psci {
74*724ba675SRob Herring		compatible = "arm,psci-0.2";
75*724ba675SRob Herring		method = "smc";
76*724ba675SRob Herring	};
77*724ba675SRob Herring
78*724ba675SRob Herring	axi@81000000 {
79*724ba675SRob Herring		compatible = "simple-bus";
80*724ba675SRob Herring		#address-cells = <1>;
81*724ba675SRob Herring		#size-cells = <1>;
82*724ba675SRob Herring		ranges = <0 0x81000000 0x8000>;
83*724ba675SRob Herring
84*724ba675SRob Herring		gic: interrupt-controller@1000 {
85*724ba675SRob Herring			compatible = "arm,cortex-a7-gic";
86*724ba675SRob Herring			#interrupt-cells = <3>;
87*724ba675SRob Herring			interrupt-controller;
88*724ba675SRob Herring			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
89*724ba675SRob Herring			reg = <0x1000 0x1000>,
90*724ba675SRob Herring				<0x2000 0x2000>,
91*724ba675SRob Herring				<0x4000 0x2000>,
92*724ba675SRob Herring				<0x6000 0x2000>;
93*724ba675SRob Herring		};
94*724ba675SRob Herring	};
95*724ba675SRob Herring
96*724ba675SRob Herring	bus@ff800000 {
97*724ba675SRob Herring		compatible = "simple-bus";
98*724ba675SRob Herring		#address-cells = <1>;
99*724ba675SRob Herring		#size-cells = <1>;
100*724ba675SRob Herring		ranges = <0 0xff800000 0x800000>;
101*724ba675SRob Herring
102*724ba675SRob Herring		uart0: serial@640 {
103*724ba675SRob Herring			compatible = "brcm,bcm6345-uart";
104*724ba675SRob Herring			reg = <0x640 0x1b>;
105*724ba675SRob Herring			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
106*724ba675SRob Herring			clocks = <&periph_clk>;
107*724ba675SRob Herring			clock-names = "refclk";
108*724ba675SRob Herring			status = "disabled";
109*724ba675SRob Herring		};
110*724ba675SRob Herring
111*724ba675SRob Herring		hsspi: spi@1000 {
112*724ba675SRob Herring			#address-cells = <1>;
113*724ba675SRob Herring			#size-cells = <0>;
114*724ba675SRob Herring			compatible = "brcm,bcm6846-hsspi", "brcm,bcmbca-hsspi-v1.0";
115*724ba675SRob Herring			reg = <0x1000 0x600>;
116*724ba675SRob Herring			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
117*724ba675SRob Herring			clocks = <&hsspi_pll &hsspi_pll>;
118*724ba675SRob Herring			clock-names = "hsspi", "pll";
119*724ba675SRob Herring			num-cs = <8>;
120*724ba675SRob Herring			status = "disabled";
121*724ba675SRob Herring		};
122*724ba675SRob Herring	};
123*724ba675SRob Herring};
124