1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Broadcom BCM63138 DSL SoCs Device Tree 4*724ba675SRob Herring */ 5*724ba675SRob Herring 6*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 7*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 8*724ba675SRob Herring 9*724ba675SRob Herring/ { 10*724ba675SRob Herring #address-cells = <1>; 11*724ba675SRob Herring #size-cells = <1>; 12*724ba675SRob Herring compatible = "brcm,bcm63138", "brcm,bcmbca"; 13*724ba675SRob Herring model = "Broadcom BCM963138 Reference Board"; 14*724ba675SRob Herring interrupt-parent = <&gic>; 15*724ba675SRob Herring 16*724ba675SRob Herring aliases { 17*724ba675SRob Herring uart0 = &serial0; 18*724ba675SRob Herring uart1 = &serial1; 19*724ba675SRob Herring }; 20*724ba675SRob Herring 21*724ba675SRob Herring cpus { 22*724ba675SRob Herring #address-cells = <1>; 23*724ba675SRob Herring #size-cells = <0>; 24*724ba675SRob Herring 25*724ba675SRob Herring cpu@0 { 26*724ba675SRob Herring device_type = "cpu"; 27*724ba675SRob Herring compatible = "arm,cortex-a9"; 28*724ba675SRob Herring next-level-cache = <&L2>; 29*724ba675SRob Herring reg = <0>; 30*724ba675SRob Herring enable-method = "brcm,bcm63138"; 31*724ba675SRob Herring }; 32*724ba675SRob Herring 33*724ba675SRob Herring cpu@1 { 34*724ba675SRob Herring device_type = "cpu"; 35*724ba675SRob Herring compatible = "arm,cortex-a9"; 36*724ba675SRob Herring next-level-cache = <&L2>; 37*724ba675SRob Herring reg = <1>; 38*724ba675SRob Herring enable-method = "brcm,bcm63138"; 39*724ba675SRob Herring resets = <&pmb0 4 1>; 40*724ba675SRob Herring }; 41*724ba675SRob Herring }; 42*724ba675SRob Herring 43*724ba675SRob Herring clocks { 44*724ba675SRob Herring /* UBUS peripheral clock */ 45*724ba675SRob Herring periph_clk: periph_clk { 46*724ba675SRob Herring #clock-cells = <0>; 47*724ba675SRob Herring compatible = "fixed-clock"; 48*724ba675SRob Herring clock-frequency = <50000000>; 49*724ba675SRob Herring clock-output-names = "periph"; 50*724ba675SRob Herring }; 51*724ba675SRob Herring 52*724ba675SRob Herring /* peripheral clock for system timer */ 53*724ba675SRob Herring axi_clk: axi_clk { 54*724ba675SRob Herring #clock-cells = <0>; 55*724ba675SRob Herring compatible = "fixed-factor-clock"; 56*724ba675SRob Herring clocks = <&armpll>; 57*724ba675SRob Herring clock-div = <2>; 58*724ba675SRob Herring clock-mult = <1>; 59*724ba675SRob Herring }; 60*724ba675SRob Herring 61*724ba675SRob Herring /* APB bus clock */ 62*724ba675SRob Herring apb_clk: apb_clk { 63*724ba675SRob Herring #clock-cells = <0>; 64*724ba675SRob Herring compatible = "fixed-factor-clock"; 65*724ba675SRob Herring clocks = <&armpll>; 66*724ba675SRob Herring clock-div = <4>; 67*724ba675SRob Herring clock-mult = <1>; 68*724ba675SRob Herring }; 69*724ba675SRob Herring 70*724ba675SRob Herring hsspi_pll: hsspi-pll { 71*724ba675SRob Herring compatible = "fixed-clock"; 72*724ba675SRob Herring #clock-cells = <0>; 73*724ba675SRob Herring clock-frequency = <400000000>; 74*724ba675SRob Herring }; 75*724ba675SRob Herring }; 76*724ba675SRob Herring 77*724ba675SRob Herring /* ARM bus */ 78*724ba675SRob Herring axi@80000000 { 79*724ba675SRob Herring compatible = "simple-bus"; 80*724ba675SRob Herring ranges = <0 0x80000000 0x784000>; 81*724ba675SRob Herring #address-cells = <1>; 82*724ba675SRob Herring #size-cells = <1>; 83*724ba675SRob Herring 84*724ba675SRob Herring L2: cache-controller@1d000 { 85*724ba675SRob Herring compatible = "arm,pl310-cache"; 86*724ba675SRob Herring reg = <0x1d000 0x1000>; 87*724ba675SRob Herring cache-unified; 88*724ba675SRob Herring cache-level = <2>; 89*724ba675SRob Herring cache-size = <524288>; 90*724ba675SRob Herring cache-sets = <1024>; 91*724ba675SRob Herring cache-line-size = <32>; 92*724ba675SRob Herring interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; 93*724ba675SRob Herring }; 94*724ba675SRob Herring 95*724ba675SRob Herring scu: scu@1e000 { 96*724ba675SRob Herring compatible = "arm,cortex-a9-scu"; 97*724ba675SRob Herring reg = <0x1e000 0x100>; 98*724ba675SRob Herring }; 99*724ba675SRob Herring 100*724ba675SRob Herring gic: interrupt-controller@1f000 { 101*724ba675SRob Herring compatible = "arm,cortex-a9-gic"; 102*724ba675SRob Herring reg = <0x1f000 0x1000 103*724ba675SRob Herring 0x1e100 0x100>; 104*724ba675SRob Herring #interrupt-cells = <3>; 105*724ba675SRob Herring #address-cells = <0>; 106*724ba675SRob Herring interrupt-controller; 107*724ba675SRob Herring }; 108*724ba675SRob Herring 109*724ba675SRob Herring global_timer: timer@1e200 { 110*724ba675SRob Herring compatible = "arm,cortex-a9-global-timer"; 111*724ba675SRob Herring reg = <0x1e200 0x20>; 112*724ba675SRob Herring interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; 113*724ba675SRob Herring clocks = <&axi_clk>; 114*724ba675SRob Herring }; 115*724ba675SRob Herring 116*724ba675SRob Herring local_timer: local-timer@1e600 { 117*724ba675SRob Herring compatible = "arm,cortex-a9-twd-timer"; 118*724ba675SRob Herring reg = <0x1e600 0x20>; 119*724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 120*724ba675SRob Herring IRQ_TYPE_EDGE_RISING)>; 121*724ba675SRob Herring clocks = <&axi_clk>; 122*724ba675SRob Herring }; 123*724ba675SRob Herring 124*724ba675SRob Herring twd_watchdog: watchdog@1e620 { 125*724ba675SRob Herring compatible = "arm,cortex-a9-twd-wdt"; 126*724ba675SRob Herring reg = <0x1e620 0x20>; 127*724ba675SRob Herring interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 128*724ba675SRob Herring IRQ_TYPE_LEVEL_HIGH)>; 129*724ba675SRob Herring }; 130*724ba675SRob Herring 131*724ba675SRob Herring armpll: armpll@20000 { 132*724ba675SRob Herring #clock-cells = <0>; 133*724ba675SRob Herring compatible = "brcm,bcm63138-armpll"; 134*724ba675SRob Herring clocks = <&periph_clk>; 135*724ba675SRob Herring reg = <0x20000 0xf00>; 136*724ba675SRob Herring }; 137*724ba675SRob Herring 138*724ba675SRob Herring pmb0: reset-controller@4800c0 { 139*724ba675SRob Herring compatible = "brcm,bcm63138-pmb"; 140*724ba675SRob Herring reg = <0x4800c0 0x10>; 141*724ba675SRob Herring #reset-cells = <2>; 142*724ba675SRob Herring }; 143*724ba675SRob Herring 144*724ba675SRob Herring pmb1: reset-controller@4800e0 { 145*724ba675SRob Herring compatible = "brcm,bcm63138-pmb"; 146*724ba675SRob Herring reg = <0x4800e0 0x10>; 147*724ba675SRob Herring #reset-cells = <2>; 148*724ba675SRob Herring }; 149*724ba675SRob Herring 150*724ba675SRob Herring ahci: sata@a000 { 151*724ba675SRob Herring compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci"; 152*724ba675SRob Herring reg-names = "ahci", "top-ctrl"; 153*724ba675SRob Herring reg = <0xa000 0x9ac>, <0x8040 0x24>; 154*724ba675SRob Herring interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 155*724ba675SRob Herring #address-cells = <1>; 156*724ba675SRob Herring #size-cells = <0>; 157*724ba675SRob Herring resets = <&pmb0 3 1>; 158*724ba675SRob Herring reset-names = "ahci"; 159*724ba675SRob Herring status = "disabled"; 160*724ba675SRob Herring 161*724ba675SRob Herring sata0: sata-port@0 { 162*724ba675SRob Herring reg = <0>; 163*724ba675SRob Herring phys = <&sata_phy0>; 164*724ba675SRob Herring }; 165*724ba675SRob Herring }; 166*724ba675SRob Herring 167*724ba675SRob Herring sata_phy: sata-phy@8100 { 168*724ba675SRob Herring compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3"; 169*724ba675SRob Herring reg = <0x8100 0x1e00>; 170*724ba675SRob Herring reg-names = "phy"; 171*724ba675SRob Herring #address-cells = <1>; 172*724ba675SRob Herring #size-cells = <0>; 173*724ba675SRob Herring status = "disabled"; 174*724ba675SRob Herring 175*724ba675SRob Herring sata_phy0: sata-phy@0 { 176*724ba675SRob Herring reg = <0>; 177*724ba675SRob Herring #phy-cells = <0>; 178*724ba675SRob Herring }; 179*724ba675SRob Herring }; 180*724ba675SRob Herring }; 181*724ba675SRob Herring 182*724ba675SRob Herring /* Legacy UBUS base */ 183*724ba675SRob Herring ubus@fffe8000 { 184*724ba675SRob Herring compatible = "simple-bus"; 185*724ba675SRob Herring #address-cells = <1>; 186*724ba675SRob Herring #size-cells = <1>; 187*724ba675SRob Herring ranges = <0 0xfffe8000 0x8100>; 188*724ba675SRob Herring 189*724ba675SRob Herring timer: timer@80 { 190*724ba675SRob Herring compatible = "brcm,bcm6328-timer", "syscon"; 191*724ba675SRob Herring reg = <0x80 0x3c>; 192*724ba675SRob Herring }; 193*724ba675SRob Herring 194*724ba675SRob Herring serial0: serial@600 { 195*724ba675SRob Herring compatible = "brcm,bcm6345-uart"; 196*724ba675SRob Herring reg = <0x600 0x1b>; 197*724ba675SRob Herring interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 198*724ba675SRob Herring clocks = <&periph_clk>; 199*724ba675SRob Herring clock-names = "periph"; 200*724ba675SRob Herring status = "disabled"; 201*724ba675SRob Herring }; 202*724ba675SRob Herring 203*724ba675SRob Herring serial1: serial@620 { 204*724ba675SRob Herring compatible = "brcm,bcm6345-uart"; 205*724ba675SRob Herring reg = <0x620 0x1b>; 206*724ba675SRob Herring interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 207*724ba675SRob Herring clocks = <&periph_clk>; 208*724ba675SRob Herring clock-names = "periph"; 209*724ba675SRob Herring status = "disabled"; 210*724ba675SRob Herring }; 211*724ba675SRob Herring 212*724ba675SRob Herring hsspi: spi@1000 { 213*724ba675SRob Herring #address-cells = <1>; 214*724ba675SRob Herring #size-cells = <0>; 215*724ba675SRob Herring compatible = "brcm,bcm63138-hsspi", "brcm,bcmbca-hsspi-v1.0"; 216*724ba675SRob Herring reg = <0x1000 0x600>; 217*724ba675SRob Herring interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 218*724ba675SRob Herring clocks = <&hsspi_pll &hsspi_pll>; 219*724ba675SRob Herring clock-names = "hsspi", "pll"; 220*724ba675SRob Herring num-cs = <8>; 221*724ba675SRob Herring status = "disabled"; 222*724ba675SRob Herring }; 223*724ba675SRob Herring 224*724ba675SRob Herring nand_controller: nand-controller@2000 { 225*724ba675SRob Herring #address-cells = <1>; 226*724ba675SRob Herring #size-cells = <0>; 227*724ba675SRob Herring compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand"; 228*724ba675SRob Herring reg = <0x2000 0x600>, <0xf0 0x10>; 229*724ba675SRob Herring reg-names = "nand", "nand-int-base"; 230*724ba675SRob Herring status = "disabled"; 231*724ba675SRob Herring interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 232*724ba675SRob Herring interrupt-names = "nand"; 233*724ba675SRob Herring }; 234*724ba675SRob Herring 235*724ba675SRob Herring bootlut: bootlut@8000 { 236*724ba675SRob Herring compatible = "brcm,bcm63138-bootlut"; 237*724ba675SRob Herring reg = <0x8000 0x50>; 238*724ba675SRob Herring }; 239*724ba675SRob Herring 240*724ba675SRob Herring reboot { 241*724ba675SRob Herring compatible = "syscon-reboot"; 242*724ba675SRob Herring regmap = <&timer>; 243*724ba675SRob Herring offset = <0x34>; 244*724ba675SRob Herring mask = <1>; 245*724ba675SRob Herring }; 246*724ba675SRob Herring }; 247*724ba675SRob Herring}; 248