1*724ba675SRob Herring/* 2*724ba675SRob Herring * Broadcom BCM470X / BCM5301X ARM platform code. 3*724ba675SRob Herring * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, 4*724ba675SRob Herring * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs 5*724ba675SRob Herring * 6*724ba675SRob Herring * Licensed under the GNU/GPL. See COPYING for details. 7*724ba675SRob Herring */ 8*724ba675SRob Herring 9*724ba675SRob Herring#include "bcm-ns.dtsi" 10*724ba675SRob Herring 11*724ba675SRob Herring/ { 12*724ba675SRob Herring mpcore-bus@19000000 { 13*724ba675SRob Herring a9pll: arm_clk@0 { 14*724ba675SRob Herring #clock-cells = <0>; 15*724ba675SRob Herring compatible = "brcm,nsp-armpll"; 16*724ba675SRob Herring clocks = <&osc>; 17*724ba675SRob Herring reg = <0x00000 0x1000>; 18*724ba675SRob Herring }; 19*724ba675SRob Herring 20*724ba675SRob Herring watchdog@20620 { 21*724ba675SRob Herring compatible = "arm,cortex-a9-twd-wdt"; 22*724ba675SRob Herring reg = <0x20620 0x20>; 23*724ba675SRob Herring interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 24*724ba675SRob Herring IRQ_TYPE_EDGE_RISING)>; 25*724ba675SRob Herring clocks = <&periph_clk>; 26*724ba675SRob Herring }; 27*724ba675SRob Herring }; 28*724ba675SRob Herring 29*724ba675SRob Herring pmu { 30*724ba675SRob Herring compatible = "arm,cortex-a9-pmu"; 31*724ba675SRob Herring interrupts = 32*724ba675SRob Herring <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 33*724ba675SRob Herring <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 34*724ba675SRob Herring }; 35*724ba675SRob Herring 36*724ba675SRob Herring clocks { 37*724ba675SRob Herring #address-cells = <1>; 38*724ba675SRob Herring #size-cells = <1>; 39*724ba675SRob Herring ranges; 40*724ba675SRob Herring 41*724ba675SRob Herring osc: oscillator { 42*724ba675SRob Herring #clock-cells = <0>; 43*724ba675SRob Herring compatible = "fixed-clock"; 44*724ba675SRob Herring clock-frequency = <25000000>; 45*724ba675SRob Herring }; 46*724ba675SRob Herring 47*724ba675SRob Herring iprocmed: iprocmed { 48*724ba675SRob Herring #clock-cells = <0>; 49*724ba675SRob Herring compatible = "fixed-factor-clock"; 50*724ba675SRob Herring clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; 51*724ba675SRob Herring clock-div = <2>; 52*724ba675SRob Herring clock-mult = <1>; 53*724ba675SRob Herring }; 54*724ba675SRob Herring 55*724ba675SRob Herring iprocslow: iprocslow { 56*724ba675SRob Herring #clock-cells = <0>; 57*724ba675SRob Herring compatible = "fixed-factor-clock"; 58*724ba675SRob Herring clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; 59*724ba675SRob Herring clock-div = <4>; 60*724ba675SRob Herring clock-mult = <1>; 61*724ba675SRob Herring }; 62*724ba675SRob Herring 63*724ba675SRob Herring periph_clk: periph_clk { 64*724ba675SRob Herring #clock-cells = <0>; 65*724ba675SRob Herring compatible = "fixed-factor-clock"; 66*724ba675SRob Herring clocks = <&a9pll>; 67*724ba675SRob Herring clock-div = <2>; 68*724ba675SRob Herring clock-mult = <1>; 69*724ba675SRob Herring }; 70*724ba675SRob Herring }; 71*724ba675SRob Herring 72*724ba675SRob Herring mdio-mux@18003000 { 73*724ba675SRob Herring compatible = "mdio-mux-mmioreg", "mdio-mux"; 74*724ba675SRob Herring mdio-parent-bus = <&mdio>; 75*724ba675SRob Herring #address-cells = <1>; 76*724ba675SRob Herring #size-cells = <0>; 77*724ba675SRob Herring reg = <0x18003000 0x4>; 78*724ba675SRob Herring mux-mask = <0x200>; 79*724ba675SRob Herring 80*724ba675SRob Herring mdio@0 { 81*724ba675SRob Herring reg = <0x0>; 82*724ba675SRob Herring #address-cells = <1>; 83*724ba675SRob Herring #size-cells = <0>; 84*724ba675SRob Herring 85*724ba675SRob Herring usb3_phy: usb3-phy@10 { 86*724ba675SRob Herring compatible = "brcm,ns-ax-usb3-phy"; 87*724ba675SRob Herring reg = <0x10>; 88*724ba675SRob Herring usb3-dmp-syscon = <&usb3_dmp>; 89*724ba675SRob Herring #phy-cells = <0>; 90*724ba675SRob Herring status = "disabled"; 91*724ba675SRob Herring }; 92*724ba675SRob Herring }; 93*724ba675SRob Herring }; 94*724ba675SRob Herring 95*724ba675SRob Herring usb3_dmp: syscon@18105000 { 96*724ba675SRob Herring reg = <0x18105000 0x1000>; 97*724ba675SRob Herring }; 98*724ba675SRob Herring 99*724ba675SRob Herring i2c0: i2c@18009000 { 100*724ba675SRob Herring compatible = "brcm,iproc-i2c"; 101*724ba675SRob Herring reg = <0x18009000 0x50>; 102*724ba675SRob Herring interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 103*724ba675SRob Herring #address-cells = <1>; 104*724ba675SRob Herring #size-cells = <0>; 105*724ba675SRob Herring clock-frequency = <100000>; 106*724ba675SRob Herring status = "disabled"; 107*724ba675SRob Herring }; 108*724ba675SRob Herring 109*724ba675SRob Herring dmu-bus@1800c000 { 110*724ba675SRob Herring cru-bus@100 { 111*724ba675SRob Herring lcpll0: clock-controller@100 { 112*724ba675SRob Herring #clock-cells = <1>; 113*724ba675SRob Herring compatible = "brcm,nsp-lcpll0"; 114*724ba675SRob Herring reg = <0x100 0x14>; 115*724ba675SRob Herring clocks = <&osc>; 116*724ba675SRob Herring clock-output-names = "lcpll0", "pcie_phy", 117*724ba675SRob Herring "sdio", "ddr_phy"; 118*724ba675SRob Herring }; 119*724ba675SRob Herring 120*724ba675SRob Herring genpll: clock-controller@140 { 121*724ba675SRob Herring #clock-cells = <1>; 122*724ba675SRob Herring compatible = "brcm,nsp-genpll"; 123*724ba675SRob Herring reg = <0x140 0x24>; 124*724ba675SRob Herring clocks = <&osc>; 125*724ba675SRob Herring clock-output-names = "genpll", "phy", 126*724ba675SRob Herring "ethernetclk", 127*724ba675SRob Herring "usbclk", "iprocfast", 128*724ba675SRob Herring "sata1", "sata2"; 129*724ba675SRob Herring }; 130*724ba675SRob Herring }; 131*724ba675SRob Herring }; 132*724ba675SRob Herring 133*724ba675SRob Herring spi@18029200 { 134*724ba675SRob Herring compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; 135*724ba675SRob Herring reg = <0x18029200 0x184>, 136*724ba675SRob Herring <0x18029000 0x124>, 137*724ba675SRob Herring <0x1811b408 0x004>, 138*724ba675SRob Herring <0x180293a0 0x01c>; 139*724ba675SRob Herring reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; 140*724ba675SRob Herring interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 141*724ba675SRob Herring <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 142*724ba675SRob Herring <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 143*724ba675SRob Herring <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 144*724ba675SRob Herring <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 145*724ba675SRob Herring <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 146*724ba675SRob Herring <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 147*724ba675SRob Herring interrupt-names = "mspi_done", 148*724ba675SRob Herring "mspi_halted", 149*724ba675SRob Herring "spi_lr_fullness_reached", 150*724ba675SRob Herring "spi_lr_session_aborted", 151*724ba675SRob Herring "spi_lr_impatient", 152*724ba675SRob Herring "spi_lr_session_done", 153*724ba675SRob Herring "spi_lr_overread"; 154*724ba675SRob Herring clocks = <&iprocmed>; 155*724ba675SRob Herring num-cs = <2>; 156*724ba675SRob Herring #address-cells = <1>; 157*724ba675SRob Herring #size-cells = <0>; 158*724ba675SRob Herring 159*724ba675SRob Herring spi_nor: flash@0 { 160*724ba675SRob Herring compatible = "jedec,spi-nor"; 161*724ba675SRob Herring reg = <0>; 162*724ba675SRob Herring spi-max-frequency = <20000000>; 163*724ba675SRob Herring status = "disabled"; 164*724ba675SRob Herring 165*724ba675SRob Herring partitions { 166*724ba675SRob Herring compatible = "brcm,bcm947xx-cfe-partitions"; 167*724ba675SRob Herring }; 168*724ba675SRob Herring }; 169*724ba675SRob Herring }; 170*724ba675SRob Herring}; 171