1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright 2022 Broadcom Ltd. 4*724ba675SRob Herring */ 5*724ba675SRob Herring 6*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 7*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 8*724ba675SRob Herring 9*724ba675SRob Herring/ { 10*724ba675SRob Herring compatible = "brcm,bcm47622", "brcm,bcmbca"; 11*724ba675SRob Herring #address-cells = <1>; 12*724ba675SRob Herring #size-cells = <1>; 13*724ba675SRob Herring 14*724ba675SRob Herring interrupt-parent = <&gic>; 15*724ba675SRob Herring 16*724ba675SRob Herring cpus { 17*724ba675SRob Herring #address-cells = <1>; 18*724ba675SRob Herring #size-cells = <0>; 19*724ba675SRob Herring 20*724ba675SRob Herring CA7_0: cpu@0 { 21*724ba675SRob Herring device_type = "cpu"; 22*724ba675SRob Herring compatible = "arm,cortex-a7"; 23*724ba675SRob Herring reg = <0x0>; 24*724ba675SRob Herring next-level-cache = <&L2_0>; 25*724ba675SRob Herring enable-method = "psci"; 26*724ba675SRob Herring }; 27*724ba675SRob Herring 28*724ba675SRob Herring CA7_1: cpu@1 { 29*724ba675SRob Herring device_type = "cpu"; 30*724ba675SRob Herring compatible = "arm,cortex-a7"; 31*724ba675SRob Herring reg = <0x1>; 32*724ba675SRob Herring next-level-cache = <&L2_0>; 33*724ba675SRob Herring enable-method = "psci"; 34*724ba675SRob Herring }; 35*724ba675SRob Herring 36*724ba675SRob Herring CA7_2: cpu@2 { 37*724ba675SRob Herring device_type = "cpu"; 38*724ba675SRob Herring compatible = "arm,cortex-a7"; 39*724ba675SRob Herring reg = <0x2>; 40*724ba675SRob Herring next-level-cache = <&L2_0>; 41*724ba675SRob Herring enable-method = "psci"; 42*724ba675SRob Herring }; 43*724ba675SRob Herring 44*724ba675SRob Herring CA7_3: cpu@3 { 45*724ba675SRob Herring device_type = "cpu"; 46*724ba675SRob Herring compatible = "arm,cortex-a7"; 47*724ba675SRob Herring reg = <0x3>; 48*724ba675SRob Herring next-level-cache = <&L2_0>; 49*724ba675SRob Herring enable-method = "psci"; 50*724ba675SRob Herring }; 51*724ba675SRob Herring 52*724ba675SRob Herring L2_0: l2-cache0 { 53*724ba675SRob Herring compatible = "cache"; 54*724ba675SRob Herring cache-level = <2>; 55*724ba675SRob Herring cache-unified; 56*724ba675SRob Herring }; 57*724ba675SRob Herring }; 58*724ba675SRob Herring 59*724ba675SRob Herring timer { 60*724ba675SRob Herring compatible = "arm,armv7-timer"; 61*724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 62*724ba675SRob Herring <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 63*724ba675SRob Herring <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 64*724ba675SRob Herring <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 65*724ba675SRob Herring arm,cpu-registers-not-fw-configured; 66*724ba675SRob Herring }; 67*724ba675SRob Herring 68*724ba675SRob Herring pmu: pmu { 69*724ba675SRob Herring compatible = "arm,cortex-a7-pmu"; 70*724ba675SRob Herring interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 71*724ba675SRob Herring <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 72*724ba675SRob Herring <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 73*724ba675SRob Herring <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 74*724ba675SRob Herring interrupt-affinity = <&CA7_0>, <&CA7_1>, 75*724ba675SRob Herring <&CA7_2>, <&CA7_3>; 76*724ba675SRob Herring }; 77*724ba675SRob Herring 78*724ba675SRob Herring clocks: clocks { 79*724ba675SRob Herring periph_clk: periph-clk { 80*724ba675SRob Herring compatible = "fixed-clock"; 81*724ba675SRob Herring #clock-cells = <0>; 82*724ba675SRob Herring clock-frequency = <200000000>; 83*724ba675SRob Herring }; 84*724ba675SRob Herring 85*724ba675SRob Herring uart_clk: uart-clk { 86*724ba675SRob Herring compatible = "fixed-factor-clock"; 87*724ba675SRob Herring #clock-cells = <0>; 88*724ba675SRob Herring clocks = <&periph_clk>; 89*724ba675SRob Herring clock-div = <4>; 90*724ba675SRob Herring clock-mult = <1>; 91*724ba675SRob Herring }; 92*724ba675SRob Herring 93*724ba675SRob Herring hsspi_pll: hsspi-pll { 94*724ba675SRob Herring compatible = "fixed-clock"; 95*724ba675SRob Herring #clock-cells = <0>; 96*724ba675SRob Herring clock-frequency = <200000000>; 97*724ba675SRob Herring }; 98*724ba675SRob Herring }; 99*724ba675SRob Herring 100*724ba675SRob Herring psci { 101*724ba675SRob Herring compatible = "arm,psci-0.2"; 102*724ba675SRob Herring method = "smc"; 103*724ba675SRob Herring }; 104*724ba675SRob Herring 105*724ba675SRob Herring axi@81000000 { 106*724ba675SRob Herring compatible = "simple-bus"; 107*724ba675SRob Herring #address-cells = <1>; 108*724ba675SRob Herring #size-cells = <1>; 109*724ba675SRob Herring ranges = <0 0x81000000 0x8000>; 110*724ba675SRob Herring 111*724ba675SRob Herring gic: interrupt-controller@1000 { 112*724ba675SRob Herring compatible = "arm,cortex-a7-gic"; 113*724ba675SRob Herring #interrupt-cells = <3>; 114*724ba675SRob Herring interrupt-controller; 115*724ba675SRob Herring interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 116*724ba675SRob Herring reg = <0x1000 0x1000>, 117*724ba675SRob Herring <0x2000 0x2000>, 118*724ba675SRob Herring <0x4000 0x2000>, 119*724ba675SRob Herring <0x6000 0x2000>; 120*724ba675SRob Herring }; 121*724ba675SRob Herring }; 122*724ba675SRob Herring 123*724ba675SRob Herring bus@ff800000 { 124*724ba675SRob Herring compatible = "simple-bus"; 125*724ba675SRob Herring #address-cells = <1>; 126*724ba675SRob Herring #size-cells = <1>; 127*724ba675SRob Herring ranges = <0 0xff800000 0x800000>; 128*724ba675SRob Herring 129*724ba675SRob Herring hsspi: spi@1000 { 130*724ba675SRob Herring #address-cells = <1>; 131*724ba675SRob Herring #size-cells = <0>; 132*724ba675SRob Herring compatible = "brcm,bcm47622-hsspi", "brcm,bcmbca-hsspi-v1.0"; 133*724ba675SRob Herring reg = <0x1000 0x600>; 134*724ba675SRob Herring interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 135*724ba675SRob Herring clocks = <&hsspi_pll &hsspi_pll>; 136*724ba675SRob Herring clock-names = "hsspi", "pll"; 137*724ba675SRob Herring num-cs = <8>; 138*724ba675SRob Herring status = "disabled"; 139*724ba675SRob Herring }; 140*724ba675SRob Herring 141*724ba675SRob Herring uart0: serial@12000 { 142*724ba675SRob Herring compatible = "arm,pl011", "arm,primecell"; 143*724ba675SRob Herring reg = <0x12000 0x1000>; 144*724ba675SRob Herring interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 145*724ba675SRob Herring clocks = <&uart_clk>, <&uart_clk>; 146*724ba675SRob Herring clock-names = "uartclk", "apb_pclk"; 147*724ba675SRob Herring status = "disabled"; 148*724ba675SRob Herring }; 149*724ba675SRob Herring }; 150*724ba675SRob Herring}; 151