1*724ba675SRob Herring#include "bcm283x.dtsi" 2*724ba675SRob Herring#include "bcm2835-common.dtsi" 3*724ba675SRob Herring 4*724ba675SRob Herring/ { 5*724ba675SRob Herring compatible = "brcm,bcm2837"; 6*724ba675SRob Herring 7*724ba675SRob Herring soc { 8*724ba675SRob Herring ranges = <0x7e000000 0x3f000000 0x1000000>, 9*724ba675SRob Herring <0x40000000 0x40000000 0x00001000>; 10*724ba675SRob Herring dma-ranges = <0xc0000000 0x00000000 0x3f000000>; 11*724ba675SRob Herring 12*724ba675SRob Herring local_intc: local_intc@40000000 { 13*724ba675SRob Herring compatible = "brcm,bcm2836-l1-intc"; 14*724ba675SRob Herring reg = <0x40000000 0x100>; 15*724ba675SRob Herring interrupt-controller; 16*724ba675SRob Herring #interrupt-cells = <2>; 17*724ba675SRob Herring interrupt-parent = <&local_intc>; 18*724ba675SRob Herring }; 19*724ba675SRob Herring }; 20*724ba675SRob Herring 21*724ba675SRob Herring arm-pmu { 22*724ba675SRob Herring compatible = "arm,cortex-a53-pmu"; 23*724ba675SRob Herring interrupt-parent = <&local_intc>; 24*724ba675SRob Herring interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 25*724ba675SRob Herring }; 26*724ba675SRob Herring 27*724ba675SRob Herring timer { 28*724ba675SRob Herring compatible = "arm,armv7-timer"; 29*724ba675SRob Herring interrupt-parent = <&local_intc>; 30*724ba675SRob Herring interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI 31*724ba675SRob Herring <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI 32*724ba675SRob Herring <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI 33*724ba675SRob Herring <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI 34*724ba675SRob Herring always-on; 35*724ba675SRob Herring }; 36*724ba675SRob Herring 37*724ba675SRob Herring cpus: cpus { 38*724ba675SRob Herring #address-cells = <1>; 39*724ba675SRob Herring #size-cells = <0>; 40*724ba675SRob Herring enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit 41*724ba675SRob Herring 42*724ba675SRob Herring /* Source for d/i-cache-line-size and d/i-cache-sets 43*724ba675SRob Herring * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system 44*724ba675SRob Herring * /about-the-l1-memory-system?lang=en 45*724ba675SRob Herring * 46*724ba675SRob Herring * Source for d/i-cache-size 47*724ba675SRob Herring * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks 48*724ba675SRob Herring */ 49*724ba675SRob Herring cpu0: cpu@0 { 50*724ba675SRob Herring device_type = "cpu"; 51*724ba675SRob Herring compatible = "arm,cortex-a53"; 52*724ba675SRob Herring reg = <0>; 53*724ba675SRob Herring enable-method = "spin-table"; 54*724ba675SRob Herring cpu-release-addr = <0x0 0x000000d8>; 55*724ba675SRob Herring d-cache-size = <0x8000>; 56*724ba675SRob Herring d-cache-line-size = <64>; 57*724ba675SRob Herring d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 58*724ba675SRob Herring i-cache-size = <0x8000>; 59*724ba675SRob Herring i-cache-line-size = <64>; 60*724ba675SRob Herring i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 61*724ba675SRob Herring next-level-cache = <&l2>; 62*724ba675SRob Herring }; 63*724ba675SRob Herring 64*724ba675SRob Herring cpu1: cpu@1 { 65*724ba675SRob Herring device_type = "cpu"; 66*724ba675SRob Herring compatible = "arm,cortex-a53"; 67*724ba675SRob Herring reg = <1>; 68*724ba675SRob Herring enable-method = "spin-table"; 69*724ba675SRob Herring cpu-release-addr = <0x0 0x000000e0>; 70*724ba675SRob Herring d-cache-size = <0x8000>; 71*724ba675SRob Herring d-cache-line-size = <64>; 72*724ba675SRob Herring d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 73*724ba675SRob Herring i-cache-size = <0x8000>; 74*724ba675SRob Herring i-cache-line-size = <64>; 75*724ba675SRob Herring i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 76*724ba675SRob Herring next-level-cache = <&l2>; 77*724ba675SRob Herring }; 78*724ba675SRob Herring 79*724ba675SRob Herring cpu2: cpu@2 { 80*724ba675SRob Herring device_type = "cpu"; 81*724ba675SRob Herring compatible = "arm,cortex-a53"; 82*724ba675SRob Herring reg = <2>; 83*724ba675SRob Herring enable-method = "spin-table"; 84*724ba675SRob Herring cpu-release-addr = <0x0 0x000000e8>; 85*724ba675SRob Herring d-cache-size = <0x8000>; 86*724ba675SRob Herring d-cache-line-size = <64>; 87*724ba675SRob Herring d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 88*724ba675SRob Herring i-cache-size = <0x8000>; 89*724ba675SRob Herring i-cache-line-size = <64>; 90*724ba675SRob Herring i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 91*724ba675SRob Herring next-level-cache = <&l2>; 92*724ba675SRob Herring }; 93*724ba675SRob Herring 94*724ba675SRob Herring cpu3: cpu@3 { 95*724ba675SRob Herring device_type = "cpu"; 96*724ba675SRob Herring compatible = "arm,cortex-a53"; 97*724ba675SRob Herring reg = <3>; 98*724ba675SRob Herring enable-method = "spin-table"; 99*724ba675SRob Herring cpu-release-addr = <0x0 0x000000f0>; 100*724ba675SRob Herring d-cache-size = <0x8000>; 101*724ba675SRob Herring d-cache-line-size = <64>; 102*724ba675SRob Herring d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 103*724ba675SRob Herring i-cache-size = <0x8000>; 104*724ba675SRob Herring i-cache-line-size = <64>; 105*724ba675SRob Herring i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 106*724ba675SRob Herring next-level-cache = <&l2>; 107*724ba675SRob Herring }; 108*724ba675SRob Herring 109*724ba675SRob Herring /* Source for cache-line-size + cache-sets 110*724ba675SRob Herring * https://developer.arm.com/documentation/ddi0500 111*724ba675SRob Herring * /e/level-2-memory-system/about-the-l2-memory-system?lang=en 112*724ba675SRob Herring * Source for cache-size 113*724ba675SRob Herring * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf 114*724ba675SRob Herring */ 115*724ba675SRob Herring l2: l2-cache0 { 116*724ba675SRob Herring compatible = "cache"; 117*724ba675SRob Herring cache-unified; 118*724ba675SRob Herring cache-size = <0x80000>; 119*724ba675SRob Herring cache-line-size = <64>; 120*724ba675SRob Herring cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set 121*724ba675SRob Herring cache-level = <2>; 122*724ba675SRob Herring }; 123*724ba675SRob Herring }; 124*724ba675SRob Herring}; 125*724ba675SRob Herring 126*724ba675SRob Herring/* Make the BCM2835-style global interrupt controller be a child of the 127*724ba675SRob Herring * CPU-local interrupt controller. 128*724ba675SRob Herring */ 129*724ba675SRob Herring&intc { 130*724ba675SRob Herring compatible = "brcm,bcm2836-armctrl-ic"; 131*724ba675SRob Herring reg = <0x7e00b200 0x200>; 132*724ba675SRob Herring interrupt-parent = <&local_intc>; 133*724ba675SRob Herring interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 134*724ba675SRob Herring}; 135*724ba675SRob Herring 136*724ba675SRob Herring&cpu_thermal { 137*724ba675SRob Herring coefficients = <(-538) 412000>; 138*724ba675SRob Herring}; 139*724ba675SRob Herring 140*724ba675SRob Herring/* enable thermal sensor with the correct compatible property set */ 141*724ba675SRob Herring&thermal { 142*724ba675SRob Herring compatible = "brcm,bcm2837-thermal"; 143*724ba675SRob Herring status = "okay"; 144*724ba675SRob Herring}; 145